Solid-state imaging device, driving method for solid-state imaging device, and electronic apparatus

Abstract

Provided are a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, which can reduce the memory circuit of a column reading system, thereby reducing the layout area of the column reading system and achieving miniaturization. The column reading circuit (40) includes: an AD conversion unit (420) that converts the read reset signal VRST11 and the read signal VSIG11 of the pixel signal Pixout read out to the vertical signal line LSGN from analog signals into n-bit digital pixel signals ADC[n] (RST ADC[n] and SIG ADC[n]); and an arithmetic unit (430) that includes an n-bit asynchronous counter (431) having a holding circuit with a control logic function that obtains the difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit (420).

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor has been put into practical use as a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates charges.

[0003] CMOS image sensors have been widely used as a part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile devices such as mobile phones.

[0004] A CMOS image sensor has a photodiode (photoelectric conversion element) and an FD amplifier having a floating diffusion layer (FD) in each pixel. The mainstream read type of this CMOS image sensor is a column parallel output type, that is, a certain row in the pixel array is selected, and these rows are read in the column output direction at the same time.

[0005] In addition, as a pixel configuration of a CMOS image sensor, a pixel configured with 4 transistors (4Tr) can be cited. For example, corresponding to 1 photodiode, it includes a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element, and a selection transistor as a selection element.

[0006] The transfer transistor is selected to be in a conductive state according to a control signal TG during a specified transfer period, and transfers the charges (electrons) photoelectrically converted and accumulated by the photodiode to the floating diffusion layer FD11.

[0007] The reset transistor is selected to be in a conductive state according to a control signal RST during a specified reset period, and resets the floating diffusion layer FD to the potential of the power supply line.

[0008] The selection transistor is selected to be in a conductive state during read scanning. Thus, the source follower transistor outputs a read signal Pixout of a column output after converting the charges of the floating diffusion layer FD into a voltage signal to a vertical signal line LSGN.

[0009] For example, during the read scan, after the floating diffusion layer FD is reset to the potential of, for example, a power supply line during the reset period, the charge of the floating diffusion layer FD is converted into a voltage signal by a source follower transistor and output as a read reset signal (voltage) VRST to the vertical signal line LSGN.

[0010] Next, during a prescribed transfer period, the charge (electrons) photoelectrically converted and accumulated in the photodiode is transferred to the floating diffusion layer FD. Then, the charge of the floating diffusion layer FD is converted into a voltage signal by a source follower transistor and output as a read signal (voltage) VSIG to the vertical signal line LSGN.

[0011] The output signal of the pixel is processed as a differential signal (VSIG - VRST).

[0012] Figure 1 It is a diagram showing a schematic configuration example of a column read system in a CMOS image sensor. Figure 2 (A) to (E) are used to explain Figure 1 The timing chart of the column read operation of the column read circuit.

[0013] In Figure 1 In the column read system 1, the pixel signal Pixout read from the pixel array 2 is output to the vertical signal line LSGN and sent to the column read circuit 3 through the AD conversion sample hold switch SW - SH.

[0014] In the column read circuit 3, the read reset signal (voltage) VRST is converted into an N - bit digital signal in the AD conversion unit 4 and stored in the reset memory 5 through the switch SW - RS.

[0015] Next, in the column read circuit 3, the read signal (voltage) VSIG is converted into an N - bit digital signal in the AD conversion unit 4 and stored in the signal memory 6 through the switch SW - RS.

[0016] Then, in the arithmetic unit 7, a differential signal (VSIG - VRST) is obtained using the stored information in the reset memory 5 and the signal memory 6.

[0017] In a CMOS image sensor, as Figure 1 shown, the luminance information is represented by the difference ΔV1 between the black level LB1 of the read reset signal VRST of the pixel signal Pixout and the signal level LS of the read signal VSIG.

[0018] In a CMOS image sensor, the black level LB1 and the signal level LS appear in the pixel output (Pixout) with a time difference, and the black level LB1 and the signal level LS are respectively AD - converted. InFigure 2 In this case, the black level LB1 is converted into a digital black level signal RST ADC, and the signal level LS is converted into a digital signal SIG ADC.

[0019] Then, in order to obtain the difference between the two data that appear with a time difference, it is necessary to store the output data of the AD conversion unit 4 in the memories 5 and 6 first.

[0020] Prior Art Documents

[0021] Patent Documents

[0022] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-62398. Summary of the Invention

[0023] Technical Problem to be Solved by the Invention

[0024] However, in the above-mentioned CMOS image sensor, the AD conversion unit and the memory circuit are restricted by the pixel width and become narrow, so the circuits are stacked vertically.

[0025] Therefore, stacking the reset (RST) circuit section, the signal (SIG) circuit section, and the two-stage memory vertically increases the layout area and the overall chip area, which is not conducive to cost.

[0026] In addition, when high speed is to be achieved in a CMOS image sensor, it is configured to access two rows simultaneously in parallel. However, in this case, as Figure 3 shown, reading circuits are respectively arranged above and below the pixel array, and the total area of the reading circuits becomes twice as large.

[0027] The present invention provides a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, which can reduce the memory circuit of the column reading system, thereby reducing the layout area of the column reading system and achieving miniaturization.

[0028] Solution to the Problem

[0029] The solid-state imaging device according to the first aspect of the present invention includes: a pixel section in which pixels that perform photoelectric conversion are arranged in a row-and-column manner; and a read circuit having an analog-to-digital (AD) conversion function of converting a pixel signal that is read out from the pixel to a signal line as a voltage signal into a digital pixel signal; the pixel signal read out from the pixel includes a read reset signal and a read signal that are sequentially read out from the pixel; the read circuit includes: an AD conversion section that converts the read reset signal and the read signal of the pixel signal read out to the signal line from an analog signal into an n-bit digital pixel signal; and an arithmetic section that includes an n-bit asynchronous counter, the asynchronous counter including a holding circuit having a control logic function, which obtains a difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion section; the arithmetic section sets the asynchronous counter to a non-operating state, outputs each bit of the n-bit read reset signal after AD conversion by the AD conversion section in synchronization with a read-in signal, receives and holds it in the holding circuit, then sets the asynchronous counter to an operating state, outputs each bit of the n-bit read signal after AD conversion by the AD conversion section in synchronization with the read-in signal, receives it, and adds it to the read reset signal held in the holding circuit to perform a counting operation, and performs an arithmetic process of the negative read reset signal and the positive read signal.

[0030] A second aspect of the present invention is a driving method for a solid-state imaging device, the solid-state imaging device including: a pixel section in which pixels that perform photoelectric conversion are arranged in a row-and-column manner; and a reading circuit having an analog-digital (AD) conversion function of converting a pixel signal, which is read out from the pixels to signal lines as a voltage signal, from an analog signal into a digital pixel signal; the reading circuit including: an AD conversion section that converts the reading reset signal and the reading signal of the pixel signal read out to the signal lines from an analog signal into an n-bit digital pixel signal; and an arithmetic section including an n-bit asynchronous counter, the asynchronous counter including a holding circuit having a control logic function, which obtains a difference between the n-bit reading reset signal and the n-bit reading signal after AD conversion performed by the AD conversion section; the pixel signal read out from the pixels includes a reading reset signal and a reading signal that are sequentially read out from the pixels; in the arithmetic section, the following arithmetic processing is performed: the asynchronous counter is set to a non-operating state, each bit of the n-bit reading reset signal after AD conversion performed by the AD conversion section is output in synchronization with a read-in signal and received and held in the holding circuit, then the asynchronous counter is set to an operating state, each bit of the n-bit reading signal after AD conversion performed by the AD conversion section is output in synchronization with the read-in signal and received and added to the reading reset signal held in the holding circuit to perform a counting operation, and an arithmetic processing of the negative reading reset signal and the positive reading signal is performed.

[0031] The electronic device according to the third aspect of the present invention includes: a solid-state imaging device; and an optical system that forms a subject image on the solid-state imaging device; the solid-state imaging device includes: a pixel unit in which pixels that perform photoelectric conversion are arranged in a row and column manner; and a reading circuit having an analog-to-digital (AD) conversion function that converts a pixel signal, which is read out from the pixel to a signal line as a voltage signal, from an analog signal to a digital pixel signal; the pixel signal read out from the pixel includes a reading reset signal and a reading signal that are sequentially read out from the pixel; the reading circuit includes: an AD conversion unit that converts the reading reset signal and the reading signal of the pixel signal read out to the signal line from an analog signal to an n-bit digital pixel signal; and an arithmetic unit that includes an n-bit asynchronous counter, and the asynchronous counter includes a holding circuit having a control logic function, and obtains a difference between the n-bit reading reset signal and the n-bit reading signal after AD conversion by the AD conversion unit; the arithmetic unit makes the asynchronous counter in a non-operating state, outputs each bit of the n-bit reading reset signal after AD conversion by the AD conversion unit in synchronization with an input signal, receives and holds it in the holding circuit, then makes the asynchronous counter in an operating state, outputs each bit of the n-bit reading signal after AD conversion by the AD conversion unit in synchronization with the input signal, receives it, and adds it to the reading reset signal held in the holding circuit to perform a counting operation, and performs an arithmetic process of the negative reading reset signal and the positive reading signal.

[0032] Effect of the Invention

[0033] According to the present invention, the memory circuit of the column reading system can be reduced, thereby reducing the layout area of the column reading system, and further achieving miniaturization. Description of the Drawings

[0034] Figure 1 It is a diagram showing a schematic configuration example of a column reading system in a CMOS image sensor.

[0035] Figure 2 It is used to illustrate Figure 1 The timing diagram of the column reading operation of the column reading circuit of.

[0036] Figure 3 It is a diagram showing the influence on the layout area in the case where the pixel reading directions are two directions, up and down, in a conventional column reading system.

[0037] Figure 4 It is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present invention.

[0038] Figure 5A circuit diagram showing an example of a pixel according to the first embodiment of the present invention.

[0039] Figure 6 A diagram showing the operation timing of shutter scanning and read scanning during normal pixel reading operation in the first embodiment of the present invention.

[0040] Figure 7 A diagram showing a basic configuration example of the column read system according to the first embodiment of the present invention.

[0041] Figure 8 For explaining Figure 7 A timing diagram showing the processing overview of the column read system.

[0042] Figure 9 A diagram showing a configuration example in which a signal inversion unit for inverting a reset signal is arranged on the output stage side of the AD conversion unit in the column read circuit according to the first embodiment of the present invention.

[0043] Figure 10 For explaining Figure 9 A timing diagram showing the operation overview of the column read circuit.

[0044] Figure 11 A block diagram showing the overall configuration example of an n-bit asynchronous counter including a holding circuit with control logic function in the arithmetic unit according to the first embodiment of the present invention.

[0045] Figure 12 For explaining Figure 11 A timing diagram showing the read-in processing of the digital pixel signal ADC in each asynchronous counter module.

[0046] Figure 13 A circuit diagram showing a specific configuration example of the logic circuit in the asynchronous counter module for each counter stage according to the first embodiment of the present invention.

[0047] Figure 14 A timing diagram showing an operation example in the case of the read-in mode PTN2 in which the signal output signal and the carry output signal are inverted in the asynchronous counter module according to the first embodiment of the present invention.

[0048] Figure 15 A timing diagram showing an operation example in the case of the read-in mode PTN4 in which the output signal and the carry output signal are inverted in the asynchronous counter module according to the first embodiment of the present invention.

[0049] Figure 16 A timing diagram showing an operation example in the case of performing an up-counting operation in the asynchronous counter module according to the first embodiment of the present invention.

[0050] Figure 17A block diagram showing a configuration example of an asynchronous counter corresponding to 2 bits of an arithmetic unit according to the first embodiment of the present invention.

[0051] Figure 18 For explaining Figure 17 A timing chart of the read-in process of the digital pixel signal ADC in each asynchronous counter module.

[0052] Figure 19 A basic configuration example diagram of a column reading system according to the second embodiment of the present invention.

[0053] Figure 20 A diagram for explaining the reading method in the column reading system of the solid-state imaging device according to the second embodiment of the present invention.

[0054] Figure 21 A diagram for explaining a method of dividing a digitized signal by the number of samplings when the read reset signal and the read signal read from the pixel are sampled multiple times.

[0055] Figure 22 A diagram showing an example of the configuration of an electronic device to which the solid-state imaging device according to the embodiment of the present invention is applied. Detailed implementation mode

[0056] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0057] (First embodiment)

[0058] Figure 4 A block diagram showing a configuration example of the solid-state imaging device according to the first embodiment of the present invention.

[0059] In the present embodiment, the solid-state imaging device 10 is constituted by, for example, a CMOS image sensor.

[0060] As Figure 4 shown, the solid-state imaging device 10 includes the following main constituent elements: a pixel unit 20 as a photographing unit, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60.

[0061] The reading unit 70 of the pixel signal is constituted by, for example, the vertical scanning circuit 30, the column reading circuit 40, and the timing control circuit 60 among these constituent elements.

[0062] As will be described later, in the present first embodiment, the column reading circuit 40 of the solid-state imaging device 10 has an analog-to-digital (AD) conversion function to convert a pixel signal, which is a voltage signal read out from a pixel that has performed photoelectric conversion in the pixel unit 20 to a vertical signal line, from an analog signal to a digital pixel signal.

[0063] In this first embodiment, the pixel signals read out from the pixels include a read reset signal VRST11 and a read signal VSIG11 that are sequentially read out from the pixels.

[0064] Moreover, the column read circuit 40 includes: an AD conversion unit that converts the read reset signal VRST11 and the read signal VSIG11 of the pixel signal Pixout read out to the vertical signal line LSGN from analog signals into n-bit digital pixel signals ADC[n] (RST ADC[n] and SIG ADC[n]); and an arithmetic unit that includes an n-bit asynchronous counter having a holding circuit with a control logic function for obtaining the difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit.

[0065] Moreover, in this first embodiment, the arithmetic unit sets the asynchronous counter to a non-operating state so that each bit output of the n-bit read reset signal RST ADC[n] after AD conversion by the AD conversion unit is synchronized with the read-in signal and received and held in the holding circuit.

[0066] Next, the arithmetic unit sets the asynchronous counter to an operating state, synchronizes each bit output of the n-bit read signal SIG ADC[n] after AD conversion by the AD conversion unit with the read-in signal and receives it, and adds it to the read reset signal RST ADC[n] held in the holding circuit to perform a counting operation, performing arithmetic processing (SIG - RST) of a negative (minus) read reset signal and a positive (plus) read signal.

[0067] In this arithmetic processing, if the outputs of the AD conversion unit are directly added, the value of (RST + SIG) will be obtained.

[0068] Therefore, in this first embodiment, the column read circuit inverts the output of the read reset signal RST ADC in order to obtain (SIG - RST) to obtain -RST ADC, and a signal inversion unit for inverting the n-bit read reset signal RST ADC after AD conversion is provided at the rear stage of the output unit of the AD conversion unit and at the front stage of the input unit of the holding circuit.

[0069] In this first embodiment, the reading unit 70 is configured to be able to perform: a first reading, in which during a first reading period following a reset period within one reading scan period, the read reset signal VRST11 (reset voltage Vrst) is read out; and a second reading, in which during a second reading period after a transfer period following the first reading period following the reset period, the read signal VSIG11 (signal voltage Vsig) corresponding to the accumulated charge of the photoelectric conversion element is read out.

[0070] In a normal pixel reading operation, driven by the reading unit 70, shutter scanning is performed first, and then reading scanning is performed. The first reading and the second reading are performed during the reading scanning.

[0071] Hereinafter, after briefly explaining the configuration and functions of each part of the solid-state imaging device 10, the circuit configuration of the column reading system and the related reading processes and the like will be described in detail.

[0072] (Configuration of Pixel Unit 20 and Pixel PXL)

[0073] In the pixel unit 20, a plurality of pixels including a photodiode (photoelectric conversion element) and an in-pixel amplifier are arranged in a two-dimensional row and column shape (matrix shape) of X rows × Y columns.

[0074] Figure 5 It is a circuit diagram showing an example of a pixel of the first embodiment of the present invention.

[0075] This pixel PXL includes, for example, a photoelectric conversion element, that is, a photodiode (PD).

[0076] For this photodiode PD, there is one transfer transistor TG-Tr as a transfer element, one reset transistor RST-Tr as a reset element, one source follower transistor SF-Tr as a source follower element, and one selection transistor SEL-Tr as a selection element, respectively.

[0077] The photodiode PD generates and accumulates a signal charge (here, electrons) corresponding to the incident light amount. Hereinafter, the case where the signal charge is electrons and each transistor is an n-type transistor will be described, but the signal charge may also be holes, and each transistor may also be a p-type transistor.

[0078] In addition, this first embodiment is also applicable to the case where each transistor is shared among a plurality of photodiodes, or the case of using a 3-transistor (3Tr) pixel without a selection transistor.

[0079] The transfer transistor TG-Tr is connected between the photodiode PD and the floating diffusion layer FD (Floating Diffusion), and is controlled by a control signal TG applied to the gate through a control line. The transfer transistor TG-Tr is selected and becomes conductive during the period when the control signal is at a high level (H), and transfers the charge (electrons) photoelectrically converted and accumulated by the photodiode PD to the floating diffusion layer FD.

[0080] The reset transistor RST-Tr is connected between the power supply line VRst and the floating diffusion layer FD, and is controlled by a control signal RST applied to the gate through a control line.

[0081] Furthermore, the reset transistor RST-Tr can also be configured to be connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion layer FD, and is controlled by the control signal RST applied to the gate through the control line. The reset transistor RST-Tr is selected and turned on during the period when the control signal RST is at the H level, and resets the floating diffusion layer FD to the potential of the power supply line VRst (or the power supply line Vdd of the power supply voltage VDD).

[0082] The source follower transistor SF-Tr and the selection transistor SEL-Tr are connected in series between the power supply line Vdd of the power supply voltage VDD and the vertical signal line LSGN11.

[0083] The floating diffusion layer FD is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled by the control signal SEL applied to the gate through the control line.

[0084] The selection transistor SEL-Tr is selected and turned on during the period when the control signal SEL is at the H level. Thereby, the source follower transistor SF-Tr outputs the read voltage (signal) VSL(PIXOUT) of the column output after converting the charge of the floating diffusion layer FD into a voltage signal to the vertical signal line LSGN11.

[0085] These operations can be performed simultaneously and in parallel for each pixel in one row because the gates of, for example, the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in units of rows.

[0086] Since the pixels PXL in the pixel section 20 are arranged in X rows × Y columns, there are N control lines for each of the control signals SEL, RST, and TG, and M vertical signal lines LSGN11.

[0087] In Figure 4 each, the control lines for the control signals SEL, RST, and TG are represented as one row scan control line.

[0088] The vertical scan circuit 30 drives the pixels through the row scan control line in the shutter row and the read row in accordance with the control of the timing control circuit 60.

[0089] In addition, the vertical scan circuit 30 outputs a row selection signal for the read row for signal reading and the row address of the shutter row for resetting the charge accumulated in the photodiode PD according to the address signal.

[0090] As described above, in the normal pixel reading operation, the shutter scan is performed by the driving of the vertical scan circuit 30 of the reading unit 70, and then the read scan is performed.

[0091] Figure 6 A diagram showing the operation timings of shutter scanning and read scanning during a normal pixel reading operation in the first embodiment of the present invention.

[0092] A control signal SEL for controlling ON (conductive) and OFF (non-conductive) of the control selection transistor SEL-Tr is set to a low level (L) during shutter scanning PSHT to keep the selection transistor SEL-Tr in a non-conductive state, and is set to a high level (H) during read scanning PRDO to keep the selection transistor SEL-Tr in a conductive state.

[0093] Moreover, during the shutter scanning PSHT, during a period when the control signal RST is at a high level (H), the control signal TG is set to a high level (H) within a specified period, and the photodiode PD and the floating diffusion layer FD are reset through the reset transistor RST-Tr and the transfer transistor TG-Tr.

[0094] During the read scanning PRDO, the control line RST is set to a high level (H) and the floating diffusion layer FD is reset through the reset transistor RST-Tr, and a pixel read signal VRST11 (reset voltage Vrst) in the reset state is read out during the first read period PRD1 after this reset period PR.

[0095] After the read period PRD1, within a specified period, the control signal TG is set to a high level (H) and the accumulated charge of the photodiode PD is transferred to the floating diffusion layer FD through the transfer transistor TG-Tr. During the second read period PRD2 after this transfer period PT, a pixel read signal VSIG11 (signal voltage Vsig) corresponding to the accumulated electrons (charges) is read out.

[0096] Furthermore, as Figure 6 shown, in the normal pixel reading operation of this first embodiment, the accumulation period (exposure period) EXP is the period from resetting the photodiode PD and the floating diffusion layer FD during the shutter scanning PSHT and switching the control signal TG to the L level, until switching the control signal TG to the L level to end the transfer period PT during the read scanning PRDO.

[0097] The column read circuit 40 can be configured to include a plurality of column signal processing circuits (not shown) arranged to correspond to the outputs of each column of the pixel section 20, and column parallel processing can be performed with the plurality of column signal processing circuits.

[0098] The column reading circuit 40 can be configured to include: a correlated double sampling (CDS) circuit or an ADC (analog-to-digital converter; AD converter), an amplifier (AMP), etc. The configuration and functions of the column reading circuit 40 will be described in detail later.

[0099] The horizontal scanning circuit 50 scans and transmits the signals processed by a plurality of column signal processing circuits such as the ADC of the column reading circuit 40 in the horizontal direction, and outputs them to a signal processing circuit (not shown).

[0100] The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the column reading circuit 40, the horizontal scanning circuit 50, etc.

[0101] Moreover, the column reading circuit 40 of the first embodiment includes: an AD conversion unit that converts the read reset signal VRST11 and the read signal VSIG11 of the pixel signal Pixout read out to the vertical signal line LSGN11 from analog signals into n-bit digital pixel signals ADC[n] (RST ADC[n] and SIG ADC[n]); and an arithmetic unit that includes an n-bit asynchronous counter including a hold circuit having a control logic function that obtains the difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit.

[0102] (Specific configuration example of the column reading circuit 40)

[0103] Hereinafter, a specific configuration example of the column reading circuit 40 of the first embodiment will be described centering on the configuration of the arithmetic unit.

[0104] Figure 7 It is a diagram showing a basic configuration example of the column reading system according to the first embodiment of the present invention.

[0105] Figure 7 The column reading circuit 40 is configured to include: an AD conversion sampling hold switch 410 (SW-SH), an AD conversion unit 420, and an arithmetic unit 430.

[0106] In addition, Figure 8 (A) to (F) are timing diagrams for explaining Figure 7 the processing outline of the column reading system.

[0107] Figure 8 (A) shows the control signal RST of the reset transistor RST-Tr, Figure 8 (B) shows the control signal TG of the transfer transistor TG-Tr, Figure 8 (C) shows the read level of the pixel signal Pixout, Figure 8(D) represents the control signal adc_S / H of the switch 410 for AD conversion sampling and holding, Figure 8 (E) represents the output signal (output data) adc_out of the AD conversion unit 420, Figure 8 (F) represents the output signal (output data) cds_logic_out of the arithmetic unit 430.

[0108] As Figure 8 shown in (A) to (D), the switch 410 sequentially sends the read reset signal VRST11 and the read signal VSIG11 of the pixel signal Pixout read from the pixel PXL of the pixel unit 20 to the vertical signal line LSGN11 to the AD conversion unit 420 according to the control signal adc_S / H.

[0109] As Figure 8 shown in (E), the AD conversion unit 420 converts the read reset signal VRST11 and the read signal VSIG11 of the pixel signal Pixout read from the pixel PXL to the vertical signal line LSGN11 and sent through the switch 410 from an analog signal to an n-bit digital pixel signal ADC[n] (RSTADC[n] and SIG ADC[n]), and outputs the n-bit digital pixel signal ADC[n] (RSTADC[n] and SIG ADC[n]) after AD conversion to the arithmetic unit 430.

[0110] The arithmetic unit 430 includes an n-bit asynchronous counter 431, which includes a holding circuit with a control logic function that obtains the difference between the n-bit read reset signal after AD conversion by the AD conversion unit 420 and the n-bit read signal (that is, the difference between the n-bit digital pixel signal ADC[n] after AD conversion, that is, the digital read reset signal RST ADC[n] and the digital read signal SIG ADC[n] (SIG ADC[n] - RST ADC[n])).

[0111] The arithmetic unit 430 is configured to combine the asynchronous counter 431 and the arithmetic circuit 432, and obtain the difference (SIG - RST) data through the cooperation of the two.

[0112] That is, the arithmetic unit 430, through the cooperation of the asynchronous counter 431 and the arithmetic circuit 432, first makes the asynchronous counter 431 in an inactive state, synchronizes and receives each bit output of the n-bit read reset signal RST ADC[n] after AD conversion by the AD conversion unit 420 with the input signal clk, and holds it in the holding circuit.

[0113] Next, the arithmetic unit 430 activates the asynchronous counter 431, synchronizes each bit output of the n-bit read signal SIG ADC[n] after AD conversion by the AD conversion unit 420 with the read signal clk, and adds it to the read reset signal RST ADC[n] held in the holding circuit to perform a counting operation. As shown in Figure 8 (F), arithmetic processing (SIG-RST) of a negative (minus) read reset signal and a positive (plus) read signal is performed.

[0114] Figure 9 FIG. for showing a configuration example of a signal inversion unit that inverts a reset signal on the output side of an AD conversion unit in a column read circuit according to the first embodiment of the present invention.

[0115] Figure 10 (A) to (C) are timing charts for explaining Figure 9 the operation outline of the column read circuit. Figure 10 (A) shows the output signal (output data) ADC out of the AD conversion unit 420, Figure 10 (B) shows the control signal cont of the signal inversion unit 440, Figure 10 (C) shows the input signal (input data) CDS_logic_in of the arithmetic unit 430.

[0116] In the above arithmetic processing in the arithmetic unit 430, if the output of the AD conversion unit 420 is directly added, the value of (RST+SIG) will be obtained.

[0117] Therefore, in the first embodiment, the column read circuit 400 inverts the output of the read reset signal RST ADC in order to obtain (SIG-RST) to obtain -RST ADC, and a signal inversion unit 440 that inverts the n-bit read reset signal RST ADC after AD conversion is arranged at the rear stage of the output unit of the AD conversion unit 420 and at the front stage of the input unit of the holding circuit.

[0118] In Figure 9 the example, a signal inversion unit 440 is arranged on the output side of the AD conversion unit 420. In this example, when the control signal cont is at an active high level, the signal inversion unit 440 inverts the n-bit read reset signal RST ADC after AD conversion.

[0119] The signal inversion unit 440 multiplies the n-bit read reset signal RST ADC output by the AD conversion unit 420 by (-1) (-1*RST ADC) to invert it.

[0120] (Specific configuration and function of the arithmetic unit 430)

[0121] Here, a more specific configuration and function of the arithmetic unit 430 of this first embodiment will be described.

[0122] Figure 11 FIG. is a block diagram showing an overall configuration example of an n-bit asynchronous counter 431 including a holding circuit having a control logic function, which is the arithmetic unit of the first embodiment of the present invention.

[0123] Figure 12 (A) and (B) are timing charts for explaining Figure 11 the read-in processing of the digital pixel signal ADC in each asynchronous counter module.

[0124] Figure 12 (A) shows the n-bit digital pixel signals ADC[n-1] to ADC[0] provided to each asynchronous counter module CMJ[n-1] to CMJ[0], Figure 12 (B) shows the read-in signals clk[n-1] to clk[0] for reading in the digital pixel signals ADC[n-1] to ADC[0] provided to each asynchronous counter module CMJ[n-1] to CMJ[0].

[0125] As Figure 11 shown, the arithmetic unit 430 is configured to include N asynchronous counter modules CMJ[n-1] to CMJ[0] arranged to correspond to each bit of the digital pixel signals ADC[n-1] to ADC[0] including the n-bit read reset signal RSTADC and the read signal SIG ADC.

[0126] Moreover, in the arithmetic unit 430, the asynchronous counter modules CMJ[n-1] to CMJ[0] are connected in series through carry output input lines. In this way, the asynchronous counter 431 is formed.

[0127] Each asynchronous counter module CMJ[n-1] to CMJ[0] includes: a digital pixel signal input terminal TIadc for inputting the corresponding bit of the read reset signal RST ADC and the read signal SIG ADC with a time difference; a read signal input terminal TIclk for inputting the read signal clk for reading in the corresponding bit of the read reset signal RST ADC and the read signal SIGADC; a carry signal input terminal TIcarry for inputting the carry signal Carry from the lower side; a signal output terminal TOout for outputting the output signal out of the module; a carry output terminal TOcarry for outputting the carry signal Carry to the upper side module; and a reset terminal TIrst for inputting the counter reset signal rst.

[0128] In addition, each asynchronous counter module CMJ[n-1] to CMJ[0] is configured to include: a logic circuit 450; and a D-type flip-flop (DFF) 460, which functions as a holding circuit for processing a clock signal Lclk corresponding to the logic circuit 450.

[0129] The logic circuit 450 generates a clock signal Lclk[n-1] through a logic operation related to the digital pixel signals ADC (RST ADC, SIG ADC) read in according to the read-in signal clk and the carry signal Carry[n-1] of the lower asynchronous counter module, and outputs the generated clock signal Lclk[n-1] to the clock terminal CK of the D-type flip-flop (DFF) 460.

[0130] The D-type flip-flop (DFF) 460 has its data output Q connected to the signal output terminal TOout, its data inverted output terminal QB connected to its own data input D and the carry output terminal TOcarry to which the carry signal input terminal TIcarry of the upper asynchronous counter module is connected, and its clock terminal CK connected to the output terminal of the clock signal Lclk of the logic circuit 450.

[0131] (Example of the configuration of the logic circuit 450)

[0132] Here, a specific configuration example of the logic circuit 450 in the arithmetic unit 430 will be described.

[0133] Figure 13 It is a circuit diagram showing a specific configuration example of the logic circuit in each counter stage of the asynchronous counter module according to the first embodiment of the present invention.

[0134] Figure 13 The logic circuit 450 is configured to include: a first logic gate 451, a second logic gate 452, a third logic gate 453, a fourth logic gate 454, a fifth logic gate 455, and a delay circuit 456.

[0135] The first logic gate 451 extracts a first signal An corresponding to the read reset signal RST ADC or the read signal SIG ADC through a logic operation (logical product: AND) of the read reset signal RST ADC or the read signal SIG ADC supplied to the first input terminal through the digital pixel signal input terminal TIadc and the read-in signal clk supplied to the second input terminal through the read-in signal input terminal TIclk.

[0136] The second logic gate 452 extracts a second signal XAn equivalent to the inverted signal of the read reset signal RST ADC or the read signal SIG ADC by performing a logical operation (negative logical product: NAND) on the read reset signal RST ADC or the read signal SIG ADC supplied to the first input terminal through the digital pixel signal input terminal TIadc and the delayed read signal dclkn that is delayed by a predetermined time by the delay circuit 456 and supplied to the second input terminal through the read signal input terminal TIclk.

[0137] The third logic gate 453 obtains a third signal Bn by performing a logical operation (logical product: AND) on the second signal XAn of the second logic gate 452 and the carry signal Carry[n - 1] from the lower bit side input through the carry signal input terminal TIcarry.

[0138] The fourth logic gate 454 obtains a fourth signal S454 by performing a logical operation (negative logical sum: NOR) on the first signal An and the third signal Bn.

[0139] The fifth logic gate 455 inverts the fourth signal S454 of the fourth logic gate 454 to obtain the clock signal Lclkn.

[0140] In the arithmetic unit 430 configured as described above, in the read mode PTN when the read signal clk[n] = 1 (the read signal clk[n] is in the valid state) of the digital pixel signal ADC in each stage of the asynchronous counter module CMJ1, when the carry signal of the lower - side asynchronous counter module CMJ[n - 1] is Carry[n - 1], the digital pixel signal of the AD conversion unit 420 is ADC[n], the digital value is high at '1' and low at '0', it is the following four modes PTN1, PTN2, PTN3, and PTN4.

[0141] PTN1.Carry[n - 1] = 0 / ADC[n] = 0

[0142] PTN2.Carry[n - 1] = 0 / ADC[n] = 1

[0143] PTN3.Carry[n - 1] = 1 / ADC[n] = 0

[0144] PTN4.Carry[n - 1] = 1 / ADC[n] = 1

[0145] In the asynchronous counter module CMJ[n], the output signal out[n] and the carry output signal Carry[n] are inverted when the digital pixel signal ADC[n] = 1 of the AD conversion unit 420 is read.

[0146] That is, among the above four patterns PTN1, PTN2, PTN3, and PTN4, in patterns PTN2 and PTN4 where the digital pixel signal ADC[n]=1 is read, the output signal out[n] and the carry output signal Carry[n] are inverted.

[0147] In addition, the asynchronous counter module CMJ[n] holds its value when the digital pixel signal ADC[n]=0 of the AD conversion unit 420 is read.

[0148] Figure 14 (A)-(J) are timing diagrams showing an operation example in the case of the read pattern PTN2 where the output signal out[n] and the carry output signal Carry[n] are inverted in the asynchronous counter module CMJ[n] of the first embodiment of the present invention.

[0149] Figure 15 (A)-(J) are timing diagrams showing an operation example in the case of the read pattern PTN4 where the output signal out[n] and the carry output signal Carry[n] are inverted in the asynchronous counter module CMJ[n] of the first embodiment of the present invention.

[0150] Figure 16 (A)-(J) are timing diagrams showing an operation example in the case of the up-counting operation in the asynchronous counter module CMJ[n] of the first embodiment of the present invention.

[0151] Figures 14 - 16 (A) shows the carry signal Carry[n-1] of the lower asynchronous counter module CMJ[n-1], Figures 14 - 16 (B) shows the digital pixel signal ADC[n] of the AD conversion unit 420, Figures 14 - 16 (C) shows the read signal clk[n] to the asynchronous counter module CMJ[n], Figures 14 - 16 (D) shows the delayed read signal dxlkn, Figures 14 - 16 (E) shows the second signal XAn, Figures 14 - 16 (F) shows the first signal An, Figures 14 - 16 (G) shows the third signal Bn, Figures 14 - 16 (H) shows the clock signal Lclk, Figures 14 - 16 (H) shows the carry signal Carry[n], Figures 14 - 16 (I) shows the output signal out[n].

[0152] As described above, as Figure 14 and Figure 15As shown, in modes PTN2 and PTN4 where the digital pixel signal ADC[n]=1 is read, when the carry signal Carry[n - 1] of the lower asynchronous counter module CMJ[n - 1] is either '0' or '1', the output signal out[n] and the carry output signal Carry[n] are inverted.

[0153] In addition, as Figure 16 shown, the asynchronous counter module CMJ[n] holds its value when the digital pixel signal ADC[n]=0 of the AD conversion unit 420 is read.

[0154] In addition, as Figure 16 shown, when the (n - 1)-bit signal is read and the carry signal Carry[n - 1] of the lower asynchronous counter module CMJ[n - 1] changes from '0' to '1', a toggle is sent to the clock signal Lclk of the n - bit asynchronous counter module, and the n - bit output signal (data) out[n] is also inverted to perform an up - counting operation.

[0155] Above, the configurations and functions of each part such as the arithmetic unit 430 of the column reading circuit 40 of the solid - state imaging device 10 have been described in detail.

[0156] Next, with reference to Figure 17 and Figure 18 (A) - (I), an example of the pixel signal reading process of the solid - state imaging device 10 according to the first embodiment of the present invention will be described.

[0157] Furthermore, the operation example of 2 bits, that is, the read reset signal RST ADC[1:0]=01 and the read signal SIGADC[1:0]=01, will be described below.

[0158] The expected value in this example is 2b'01 + 2b'01 = 2b'10.

[0159] Figure 17 is a block diagram showing a configuration example of the 2 - bit asynchronous counter 431 corresponding to the arithmetic unit of the first embodiment of the present invention.

[0160] Figure 17 The asynchronous counter of Figure 13 is formed by vertically connecting two

[0161] Figure 18 (A) - (I) are timing diagrams for explaining the read process of the digital pixel signal ADC in each asynchronous counter module of Figure 17 ​

[0162] Figure 18 (A) represents the carry signal Carry[n - 1] of the lower asynchronous counter module CMJ[0], Figure 18 (B) represents the digital pixel signal ADC[0] with an n-bit amplitude supplied to the asynchronous counter module CMJ[0], Figure 18 (C) represents the read signal clk[0] for reading the digital pixel signal ADC[0] supplied to the asynchronous counter module CMJ[0], Figure 18 (D) represents the digital pixel signal ADC[1] with an n-bit amplitude supplied to the asynchronous counter module CMJ[1], Figure 18 (E) represents the read signal clk[1] for reading the digital pixel signal ADC[1] supplied to the asynchronous counter module CMJ[1], Figure 18 (F) represents the output signal out[0] of the asynchronous counter module CMJ[0], Figure 18 (G) represents the carry signal Carry[0] of the asynchronous counter module CMJ[0], Figure 18 (H) represents the output signal out[1] of the asynchronous counter module CMJ[1], Figure 18 (I) represents the carry signal Carry[1] of the asynchronous counter module CMJ[1].

[0163] Step ST1:

[0164] When the 2-bit amplitude digital pixel signal RST ADC[0] supplied to the asynchronous counter module CMJ[0] is read (read) with the valid signal R0 of the read signal clk[0], it corresponds to the read mode PTN2. Therefore, the level of the output signal out[0] is inverted from '0' to '1' ('0' → '1').

[0165] Step ST2:

[0166] When the 2-bit amplitude digital pixel signal RST ADC[1] supplied to the asynchronous counter module CMJ[1] is read (read) with the valid signal R1 of the read signal clk[1], it corresponds to the read mode PTN1. Therefore, the level of the output signal out[1] remains '0' ('0' → '0').

[0167] Step ST3:

[0168] When the 2-bit amplitude digital pixel signal SIG ADC[0] supplied to the asynchronous counter module CMJ[0] is read (read) with the valid signal S0 of the read signal clk[0], the level of the output signal out[0] is inverted from '1' to '0' again.

[0169] At this time, the carry signal Carry[0] moves from '0' to '1' ('0' → '1'). Therefore, the level of the output signal out[1] of the asynchronous counter module CMJ[1] is inverted from '0' to '1' ('0' → '1').

[0170] Step ST4:

[0171] Read (fetch) the 2-bit digital pixel signal SIG ADC[1]=0 supplied to the asynchronous counter module CMJ[1] with the valid signal S1 of the read-in signal clk[1]. At this time, the level of the output signal out[1] is maintained at '1'.

[0172] When the read-in is completed, the output signal out[1:0]=2b'10, which is consistent with the expected value.

[0173] As described above, according to this first embodiment, the column reading circuit 40 includes: an AD conversion unit 420 that converts the read reset signal VRST11 and the read signal VSIG11 of the pixel signal Pixout read out to the vertical signal line LSGN from analog signals into n-bit digital pixel signals ADC[n] (RSTADC[n] and SIG ADC[n]); and an arithmetic unit 430 that includes an n-bit asynchronous counter 431 having a control logic function that obtains the difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit 420.

[0174] Moreover, the arithmetic unit 430 sets the asynchronous counter to a non-operating state so that each bit output of the n-bit read reset signal RST ADC[n] after AD conversion by the AD conversion unit 420 is synchronized with the read-in signal clk and received and held in the DFF460 as a holding circuit.

[0175] Next, the arithmetic unit 430 sets the asynchronous counter to an operating state, synchronizes each bit output of the n-bit read signal SIG ADC[n] after AD conversion by the AD conversion unit 420 with the read-in signal clk and receives it, and adds it to the read reset signal RST ADC[n] held in the DFF451 as a holding circuit to perform a counting operation, and performs an arithmetic process (SIG-RST) of a negative (minus) read reset signal and a positive (plus) read signal.

[0176] In this arithmetic process, in order to prevent the value of (RST + SIG) from being directly obtained by adding the outputs of the AD conversion section, in this first embodiment, the column reading circuit inverts the output of the read reset signal RST ADC to obtain -RST ADC in order to obtain (SIG - RST), and after the output section of the AD conversion section and before the input section of the holding circuit, a signal inversion section 440 that inverts the AD-converted n-bit read reset signal RST ADC is included.

[0177] Therefore, according to this first embodiment, the memory circuit of the column reading system can be reduced, thereby reducing the layout area of the column reading system, and further achieving miniaturization.

[0178] (Second Embodiment)

[0179] Figure 19 FIG. is a basic configuration example diagram of the column reading system of the second embodiment of the present invention.

[0180] Figure 20 (A) to (E) are diagrams for explaining the reading method in the column reading system of the solid-state imaging device of the second embodiment of the present invention.

[0181] Figure 21 FIG. is a diagram for explaining a method of dividing a digitized signal by the number of samplings in the case of sampling the read reset signal and the read signal read from the pixel multiple times.

[0182] The difference between the solid-state imaging device 10A of this second embodiment and the solid-state imaging device 10 of the above first embodiment is as follows.

[0183] In the solid-state imaging device 10 of the first embodiment, the column reading circuit 40 samples the read reset signal VRST11 and the read signal VSIG read from the pixel in the switch 410 once each, and takes them into (reads them into) the AD conversion section 420.

[0184] In contrast, in the solid-state imaging device 10A of this second embodiment, in order to achieve low-noise reading, the column reading circuit 40A samples and holds the read reset signal VRST11 and the read signal VSIG of the pixel signal read out to the vertical signal line LSGN11 multiple times (for example, 2 times), and takes them into the AD conversion section 420A.

[0185] The arithmetic unit 430A performs a process of dividing the two digital read reset signals and the two read signals by the number of samplings 2 to obtain the difference between the n-bit read reset signal RSTADC and the n-bit read signal SIG ADC after AD conversion by the AD conversion section 420A.

[0186] In addition, in this second embodiment, when the reading circuit 40A reads the digital pixel signal into the asynchronous counter module CMJ, the above-described process of dividing by the sampling number 2 is performed by taking in the bit after shifting by 1 bit.

[0187] In this way, when the read reset signal VRST11 is sampled twice and the read signal VSIG11 is sampled twice, and divided by the sampling number 2 (division operation), the noise component becomes 1 / sqrt(2).

[0188] The operation of dividing the read reset signal VRST11 and the read signal VSIG11 by 2 is, as Figure 21 shown, achieved by taking in the bit after shifting by 1 bit when taking in to the arithmetic unit 430A.

[0189] According to this second embodiment, not only the same effects as those of the above-described first embodiment can be achieved, but also a lower-noise reading can be realized.

[0190] The solid-state imaging devices 10 and 10A described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, portable terminals, surveillance cameras, and medical endoscope cameras.

[0191] Figure 22 FIG. is a diagram showing an example of the configuration of an electronic device of a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

[0192] This electronic device 800, as Figure 22 shown, includes a CMOS image sensor 310 to which the solid-state imaging devices 10 and 10A according to this embodiment can be applied.

[0193] Moreover, the electronic device 800 includes an optical system (such as a lens) 820 that guides incident light to the pixel region of the CMOS image sensor 810 (forms a subject image).

[0194] The electronic device 800 includes a signal processing circuit (PRC) 830 that processes the output signal of the CMOS image sensor 810.

[0195] The signal processing circuit 830 performs a predetermined signal processing on the output signal of the CMOS image sensor 810.

[0196] The image signal processed by the signal processing circuit 830 can be in various forms, can be displayed as a moving image on a monitor composed of a liquid crystal display or the like, or can be output to a printer, or directly recorded on a recording medium such as a memory card.

[0197] As described above, by mounting the solid-state imaging devices 10 and 10A as the CMOS image sensor 810, a high-performance, small-sized, and low-cost camera system can be provided.

[0198] Moreover, it is possible to implement an electronic device for use in applications where there are restrictions on the installation size, the number of connectable cables, the cable length, the installation height, etc. in the setting conditions of the camera, such as a surveillance camera, a camera for a medical endoscope, etc.

[0199] Main Component Symbol Explanation

[0200] 10, 10A: Solid-state imaging device

[0201] 20: Pixel section

[0202] 30: Vertical scanning circuit

[0203] 40, 40A: Column reading circuit

[0204] 410, 410A: Sample-and-hold switch

[0205] 420, 420A: AD conversion section

[0206] 430, 430A: Arithmetic section

[0207] 431: Asynchronous counter

[0208] 432: Arithmetic circuit

[0209] 440: Signal inversion section

[0210] 450: Logic circuit

[0211] 451: First logic gate

[0212] 452: Second logic gate

[0213] 453: Third logic gate

[0214] 454: Fourth logic gate

[0215] 455: Fifth logic gate

[0216] 460: D-type flip-flop

[0217] CMJ: Asynchronous counter module

[0218] Lclk: Clock signal

[0219] 800: Electronic device

[0220] 810: CMOS image sensor

[0221] 820: Optical system

[0222] 830: Signal processing circuit (PRC)

Claims

1. A solid-state imaging device, characterized in that Comprising: A pixel section in which pixels that perform photoelectric conversion are arranged in a row-and-column manner; And A read circuit having an analog-to-digital conversion function of converting a pixel signal, which is read out from the pixel to a signal line as a voltage signal, from an analog signal to a digital pixel signal; Wherein: The pixel signal read out from the pixel Includes a read reset signal and a read signal read out from the pixel in sequence; The read circuit includes: An AD conversion section that converts the read reset signal and the read signal of the pixel signal read out to the signal line from an analog signal to an n-bit digital pixel signal; and An arithmetic section that includes an n-bit asynchronous counter, and the asynchronous counter includes a holding circuit having a control logic function, and obtains a difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion section; The arithmetic section Makes the asynchronous counter in a non-operating state, synchronously receives and holds each bit output of the n-bit read reset signal after AD conversion by the AD conversion section in the holding circuit with the read-in signal, and then, Makes the asynchronous counter in an operating state, synchronously receives each bit output of the n-bit read signal after AD conversion by the AD conversion section with the read-in signal and adds it to the read reset signal held in the holding circuit to perform a counting operation, and performs an arithmetic process of the negative read reset signal and the positive read signal; Wherein: After the output section of the AD conversion section and before the input section of the holding circuit, a signal inversion section that inverts the n-bit read reset signal after AD conversion is included.

2. The solid-state imaging device according to claim 1, wherein: The arithmetic section Includes n asynchronous counter modules configured to correspond to each bit of a digital pixel signal including the n-bit read reset signal and the read signal, The n asynchronous counter modules for each bit are connected in series through carry signal input / output lines; The n asynchronous counter modules for each bit include: A logic circuit; and A D-type flip-flop having a function of the holding circuit that performs processing of a clock signal corresponding to the logic circuit; The logic circuit Generates the clock signal through a logical operation related to the digital pixel signal read in according to the read-in signal and the carry signal of the lower asynchronous counter module; In the D-type flip-flop, The data output Q is connected to a signal output terminal; The data inverted output terminal QB is connected to its own data input D and a carry signal output terminal to which a carry signal input terminal of the upper asynchronous counter module is connected; The clock terminal is connected to an output terminal of the clock signal of the logic circuit.

3. The solid-state imaging device according to claim 2, wherein: The n asynchronous counter modules for each bit include: A pixel signal input terminal for inputting the read reset signal and the read signal corresponding to a bit; A read-in signal input terminal for inputting a read-in signal for reading in the read reset signal and the read signal corresponding to a bit; A carry signal input terminal; A signal output terminal; A carry signal output terminal; A first logic gate for extracting a first signal equivalent to the read reset signal or the read signal through a logical operation of the read reset signal or the read signal supplied to a first input terminal and the read-in signal; A second logic gate for inverting the level of the read reset signal or the read signal through a logical operation of the read reset signal or the read signal supplied to the first input terminal and the read-in signal, and extracting a second signal that is the inverse of the first signal; A third logic gate for obtaining a third signal through a logical operation of the second signal of the second logic gate and a carry signal from the lower-bit side input from the carry signal input terminal; A fourth logic gate for obtaining a fourth signal through a negative logical sum of the first signal and the third signal; A fifth logic gate for inverting the fourth signal of the fourth logic gate to obtain a clock signal; In the D flip-flop, The data output Q is connected to the signal output terminal; The data inverted output terminal QB is connected to its own data input D and the carry signal output terminal; The clock terminal is connected to the output terminal of the clock signal of the fifth logic gate; The carry signal input terminal is connected to the carry output terminal of the asynchronous counter module on the lower side; The carry signal output terminal is connected to the carry signal input terminal of the asynchronous counter module on the upper side.

4. The solid-state imaging device according to claim 3, wherein : When the read-in signal of the digital pixel signal ADC of each stage of the asynchronous counter module is in an effective state, the read-in mode is as follows. When the carry signal of the asynchronous counter module on the lower side is Carry[n - 1], the digital pixel signal of the AD conversion unit is ADC[n], and the digital value is high as '1' and low as '0', it is the following four modes PTN1, PTN2, PTN3, PTN4: PTN1.Carry[n - 1] = 0 / ADC[n] = 0; PTN2.Carry[n - 1] = 0 / ADC[n] = 1; PTN3.Carry[n - 1] = 1 / ADC[n] = 0; PTN4.Carry[n - 1] = 1 / ADC[n] = 1.

5. The solid-state imaging device according to claim 4, wherein : In the asynchronous counter module, the output signal out[n] and the carry output signal carry[n] are inverted when the digital pixel signal ADC[n] = 1 of the AD conversion unit is read in.

6. The solid-state imaging device according to claim 5, wherein : The asynchronous counter module, Maintains its value when the digital pixel signal ADC[n] = 0 of the AD conversion unit is read in.

7. The solid-state imaging device according to claim 4, wherein : When reading an (n - 1)-bit signal, when the carry signal Carry[n - 1] of the asynchronous counter module on the lower side reverses from '0' to '1', the inversion is conveyed to the clock signal of the n-bit asynchronous counter module and the n-bit data also inverts to perform an up-counting operation.

8. The solid-state imaging device according to claim 2, characterized in that: The reading circuit, Samples the read reset signal and the read signal of the pixel signal read out to the signal line multiple times and takes them into the AD conversion unit; The arithmetic unit, Performs a process of dividing a plurality of digital read reset signals and a plurality of read signals by the number of sampling times to obtain a difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit.

9. The solid-state imaging device according to claim 8, characterized in that: The reading circuit, When reading the digital pixel signal into the asynchronous counter module, takes it into the bit after bit shifting to perform a process of dividing by the number of sampling times.

10. The solid-state imaging device according to claim 9, characterized in that: The reading circuit, Performs the sampling 2 times, When reading the digital pixel signal into the asynchronous counter module, takes it into the bit after shifting 1 bit to perform a process of dividing by the number of sampling times 2.

11. A driving method for a solid-state imaging device, characterized in that A driving method for a solid-state imaging device, the solid-state imaging device comprising: A pixel unit in which pixels performing photoelectric conversion are arranged in a row and column; and A reading circuit having an analog-to-digital conversion function of converting a pixel signal read out from the pixel to the signal line as a voltage signal from an analog signal into a digital pixel signal; The pixel signal read out from the pixel, Includes a read reset signal and a read signal sequentially read out from the pixel; The reading circuit includes: An AD conversion unit that converts the read reset signal and the read signal of the pixel signal read out to the signal line from an analog signal into an n-bit digital pixel signal; and An arithmetic unit including an n-bit asynchronous counter, the asynchronous counter including a holding circuit having a control logic function, which obtains a difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit; In the arithmetic unit, the following arithmetic process is performed: Makes the asynchronous counter in a non-operating state, receives and holds each bit output of the n-bit read reset signal after AD conversion by the AD conversion unit in the holding circuit synchronously with the input signal, and then, Makes the asynchronous counter in an operating state, receives each bit output of the n-bit read signal after AD conversion by the AD conversion unit synchronously with the input signal and adds it to the read reset signal held in the holding circuit to perform a counting operation, and performs an arithmetic process of the negative read reset signal and the positive read signal; Wherein: A signal inversion unit that inverts the n-bit read reset signal after AD conversion is included at a subsequent stage of the output unit of the AD conversion unit and at a preceding stage of the input unit of the holding circuit.

12. An electronic device, characterized in that Comprising: A solid-state imaging device; And An optical system that forms a subject image on the solid-state imaging device; The solid-state imaging device includes: A pixel unit in which pixels that perform photoelectric conversion are arranged in a row-and-column manner; and A read circuit having an analog-to-digital conversion function that converts a pixel signal, which is read out from the pixels to signal lines as a voltage signal, from an analog signal into a digital pixel signal; The pixel signal read out from the pixels Includes a read reset signal and a read signal that are sequentially read out from the pixels; The read circuit includes: An AD conversion unit that converts the read reset signal and the read signal of the pixel signal read out to the signal lines from analog signals into n-bit digital pixel signals; and An arithmetic unit that includes an n-bit asynchronous counter, and the asynchronous counter includes a holding circuit having a control logic function, and obtains a difference between the n-bit read reset signal and the n-bit read signal after AD conversion by the AD conversion unit; The arithmetic unit Sets the asynchronous counter to a non-operating state, receives and holds each bit output of the n-bit read reset signal after AD conversion by the AD conversion unit in synchronization with the read-in signal in the holding circuit, and then Sets the asynchronous counter to an operating state, receives each bit output of the n-bit read signal after AD conversion by the AD conversion unit in synchronization with the read-in signal, adds it to the read reset signal held in the holding circuit, and performs a counting operation, and performs an arithmetic process of the negative read reset signal and the positive read signal; Wherein: A signal inversion unit that inverts the n-bit read reset signal after AD conversion is included at a subsequent stage of the output unit of the AD conversion unit and at a preceding stage of the input unit of the holding circuit.

Images