Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a substrate, the substrate being provided with a plurality of first grooves extending along a first direction and a plurality of second grooves extending along a second direction, the depth of the first grooves being less than the depth of the second grooves; forming a first isolation structure to cover the substrate and fill the first grooves and the second grooves; forming a plurality of third grooves, the third grooves being located in the substrate at the bottom of the first grooves and extending along the first direction; forming a second isolation structure to fill the first grooves and the third grooves; forming a gate structure, the gate structure surrounding the substrate between the first grooves along the second direction, in the first direction, the projection of the gate structure and the projection of the second grooves being parallel to each other and alternately spaced; and forming a conductive structure, the conductive structure being located in the second grooves, and in the first direction, the conductive structures being spaced in the second grooves, so as to improve the integration density of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration density of dynamic memory develops towards a higher direction, while studying the arrangement of transistors in the dynamic memory array structure, how to reduce the size of individual functional devices in the dynamic memory array structure and improve the electrical performance of small-sized functional devices are issues that need to be urgently addressed.

[0003] Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and gate-all-around (GAA) structures. In a GAA structure, the gate structure completely surrounds the conductive channel, allowing the transistor to maximize control of the current flowing therein. However, the GAA fabrication process requires forming a gate structure that surrounds the transistor on all sides, which increases the difficulty of semiconductor structure fabrication and places higher demands on improving the integration density of the semiconductor structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, so as to improve the integration density of the semiconductor structure.

[0005] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, on which are provided a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, the depth of the first trenches being less than the depth of the second trenches; forming a first isolation structure covering the substrate and filling the first trenches and the second trenches; forming a plurality of third trenches, the third trenches being located in the substrate at the bottom of the first trenches and extending along the first direction; forming a second isolation structure filling the first trenches and the third trenches; forming a gate structure, the gate structure surrounding the substrate between the first trenches along the second direction, the projection of the gate structure and the projection of the second trench being parallel to each other and alternately spaced in the first direction; forming a conductive structure, the conductive structure being located in the second trenches, and the conductive structure being spaced in the second trenches in the first direction.

[0006] In some embodiments, the step of forming a first isolation structure includes: forming a first isolation layer, the first isolation layer fills the first trench and covers the top surface of the substrate; forming a second isolation layer, the second isolation layer fills the second trench, and the top surface of the second isolation layer is flush with the top surface of the first isolation layer.

[0007] In some embodiments, the material forming the first isolation layer is different from the material forming the second isolation layer.

[0008] In some embodiments, the step of forming multiple third trenches includes: forming an etching opening, the etching opening is located in the first isolation structure of the first trench, and the size of the etching opening in the first direction is less than or equal to the size of the first trench; forming third trenches based on the etching opening, and adjacent third trenches in the second direction are connected to each other.

[0009] In some embodiments, the step of forming a gate structure includes: forming a channel region, wherein the channel region exposes the substrate surface of the first trench and the third trench along the second direction, and the projection of the channel region and the projection of the second trench in the first direction are parallel to each other and alternately spaced; filling the channel region to form a gate structure.

[0010] In some embodiments, after forming the channel region and before forming the gate structure, the method further includes performing rounding on the substrate between the first trenches so that the morphology of the substrate exposed between the first trenches conforms to a preset pattern.

[0011] In some embodiments, the corner rounding process is implemented based on a thermal oxidation process, an etching process, and / or a hydrogen annealing process.

[0012] In some embodiments, the preset shape includes: a cylinder, an elliptical cylinder, or a polygonal prism.

[0013] In some embodiments, after forming the channel region and before forming the gate structure, the method further includes: performing a planarization process on the substrate at the bottom of the channel region.

[0014] In some embodiments, forming the gate structure includes: forming a gate dielectric layer, the gate dielectric layer covering the surface of the substrate in the channel region; and forming a gate conductive layer, the gate conductive layer filling the gap between the substrate in the channel region.

[0015] In some embodiments, after forming the gate structure and before forming the conductive structure, the method further includes forming a third isolation structure, wherein the third isolation structure covers a top surface of the gate structure and a top portion thereof is flush with a top surface of the first isolation structure.

[0016] In some embodiments, the step of forming the conductive structure includes: patterning the first isolation structure and the second isolation structure to expose the second trenches at intervals in the first direction; and filling the second trenches to form the conductive structure.

[0017] In some embodiments, the material forming the conductive structure includes at least one of metal silicide, copper, or tungsten.

[0018] In some embodiments, the angle between the first direction and the second direction is greater than 0°.

[0019] In some embodiments, after forming the conductive structure, it also includes: forming a fourth isolation structure, the fourth isolation structure covering the surface of the first isolation structure, the second isolation structure, the gate structure and the conductive structure; forming a plurality of bit line contact lines, the bit line contact lines are located in the fourth isolation structure and extend along the third direction; one end of the bit line contact line is connected to the conductive structure, and the other end is connected to the bit line extension line, the bit line extension line is located in the fourth isolation structure and extends along the first direction.

[0020] In some embodiments, an angle between the third direction and the plane where the first direction and the second direction are located is greater than 0°.

[0021] In some embodiments, after forming the conductive structure, it also includes: forming a capacitor contact isolation layer, the capacitor contact isolation layer covers the surface of the fourth isolation structure and the bit line extension line; forming a capacitor contact, the capacitor contact structure is located in the second trench and the capacitor contact isolation layer, extending along the third direction, and the capacitor contact structure and the conductive structure are alternately arranged in the first direction; forming a capacitor structure, the capacitor structure is located on the top surface of the capacitor contact structure.

[0022] An embodiment of the present disclosure also provides a semiconductor structure, which adopts the manufacturing method of the semiconductor structure in the above embodiment, including: a substrate, on which are provided a plurality of first trenches extending along a first direction, a plurality of second trenches extending along a second direction, and a plurality of third trenches extending along the first direction, wherein the depth of the first trench is less than the depth of the second trench, and the third trench is located in the substrate at the bottom of the first trench; a gate structure, which surrounds the substrate between the first trenches along the second direction, and in the first direction, the projection of the gate structure is parallel to the projection of the second trench and is arranged alternately at intervals; a conductive structure, which is located in the second trench, and in the first direction, the conductive structure is spaced apart in the second trench; a first isolation structure, which fills the first trench and the second trench between the gate structure and the conductive structure; and a second isolation structure, which fills the first trench and the third trench between the gate structure and the conductive structure.

[0023] In some embodiments, the gate structure includes: a gate dielectric layer covering the substrate surface of the first trench and the third trench; and a gate conductive layer covering the surface of the gate dielectric layer and filling the first trench and the third trench.

[0024] In some embodiments, the semiconductor structure also includes: a fourth isolation structure covering the top surfaces of the first isolation structure, the second isolation structure, the gate structure and the conductive structure; a plurality of bit line contact lines located within the fourth isolation structure and extending along a third direction; one end of the bit line contact line is connected to the conductive structure and the other end is connected to a bit line extension line, and the bit line extension line is located within the fourth isolation structure and extends along the first direction.

[0025] In some embodiments, the semiconductor structure further includes: a capacitor contact isolation layer covering the surface of the fourth isolation structure and the bit line extension line; a capacitor contact structure located within the second trench and the capacitor contact isolation layer, extending along a third direction, and the capacitor contact structure and the conductive structure are alternately arranged in the first direction; and a capacitor structure located on the top surface of the capacitor contact structure.

[0026] In some embodiments, the capacitor structures are arranged in a hexagonal pattern in the first direction and the second direction.

[0027] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by forming a plurality of first trenches extending along a first direction, a plurality of second trenches extending along a second direction, and a plurality of third trenches extending along the first direction; in the second direction, a gate structure is formed around the substrate between the first trenches and the third trenches; in the first direction, a conductive structure is formed at intervals within the second trenches; thereby forming a transistor with a full-surround gate structure, thereby increasing the contact area of ​​the transistor channel region, thereby improving the transistor's ability to control current, thereby improving the performance of the semiconductor structure, and the full-surround gate structure can increase the integration density of the semiconductor structure. In the second direction, two adjacent rows of transistors are connected to the same conductive structure, that is, the two rows of transistors share the same bit line, thereby improving the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure, and also simplifying the bit line formation process of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figures 1 to 15 Schematic diagram of the structures corresponding to the steps of the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As can be seen from the background technology, it is difficult to improve the integration density of the GAA semiconductor structure.

[0031] Analysis found that the causes of the above problems include: the gate structure in the GAA structure completely surrounds the conductive channel to maximize the control of the current therein. At the same time, the gate structure in the GAA structure surrounds the channel region to improve the integration density of the semiconductor structure. However, in the manufacturing process of the GAA structure, it is necessary to form a gate structure surrounding the transistor on all sides, which increases the difficulty of semiconductor structure manufacturing and puts forward higher requirements for further improving the integration density of the semiconductor structure.

[0032] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can be used to manufacture a GAA structure and applied to memories, such as DRAM (Dynamic random access memory) memory, SRAM (static random access memory) memory or ROM (Read only memory), to improve the integration density of the semiconductor structure.

[0033] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0034] Figures 1 to 15 The schematic diagram of the structure corresponding to each step of the method for manufacturing the semiconductor structure provided in this embodiment, wherein: Figure 6 for Figure 5 Schematic diagram of the cross-section structure along the AA1 direction, Figures 9 to 11 for Figure 8 FIG14( b ) is a schematic diagram of the cross-sectional structure along the BB1 ​​direction. FIG14( b ) is a schematic diagram of the structure of the corresponding relationship between the conductive structure, the bit line contact line, and the bit line extension line in FIG14( a ). The following is a detailed description of the method for manufacturing the semiconductor structure provided in this embodiment in conjunction with the accompanying drawings, as follows:

[0035] A method for manufacturing a semiconductor structure, comprising:

[0036] refer to Figure 1 A substrate 100 is provided, on which a plurality of first grooves 101 extending along a first direction Y and a plurality of second grooves 102 extending along a second direction X are provided, wherein the depth of the first grooves 101 is less than the depth of the second grooves 102, wherein an angle between the first direction Y and the second direction X is greater than 0°.

[0037] The substrate 100 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0038] It should be noted that, in this embodiment, the angle between the first direction Y and the second direction X is 90°. In other embodiments, the angle between the first direction Y and the second direction X may be 45°, 60°, or 80°. This embodiment does not constitute a limitation on the angle between the first direction Y and the second direction X.

[0039] refer to Figure 2 , forming a first isolation structure 11 covering the substrate 100 and filling the first trench 101 and the second trench 102 .

[0040] As for the first isolation structure 11 , the material forming the first isolation structure 11 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0041] In some embodiments, reference Figure 3 The steps of forming the first isolation junction 11 include: forming a first isolation layer 201, the first isolation layer 201 fills the first trench 101 and covers the top surface of the substrate 100; forming a second isolation layer 202, the second isolation layer 202 fills the second trench 102, and the top surface is flush with the top surface of the first isolation layer 201.

[0042] The first isolation layer 201 and the second isolation layer 202 may be formed of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material forming the first isolation layer 201 and the material forming the second isolation layer 202 are the same, and subsequent figures will be represented by the same filler. In other embodiments, the materials forming the first isolation layer 201 and the second isolation layer 202 may be different.

[0043] In some embodiments, the process of forming the first isolation layer 201 and the process of forming the second isolation layer 202 may be a deposition process, and the deposition process may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0044] In other embodiments, a method of providing a substrate and forming a first isolation structure includes: providing a substrate and forming a first isolation layer, the first isolation layer covering a surface of the substrate; patterning the first isolation layer and a portion of the substrate to form a first trench, and filling the first trench with the first isolation layer; patterning the first isolation layer and a portion of the substrate to form a second trench, and filling the second trench with a second isolation layer, wherein a top surface of the second isolation layer is flush with a top surface of the first isolation layer, the first isolation layer and the second isolation layer together forming a first isolation structure. Forming the first isolation layer on the surface of the substrate first can protect the substrate surface from contamination or damage during the patterning of the first isolation layer and the substrate, thereby preventing the performance of the semiconductor structure from being affected.

[0045] A plurality of third trenches are formed. The third trenches are located in the substrate 100 at the bottom of the first trenches and extend along the first direction.

[0046] Specifically, refer to Figure 4 and Figure 5 , a method for forming a third trench, comprising: referring to Figure 4 , patterning a portion of the first isolation structure 11 to form an etched opening 111, the etched opening 111 is located within the first isolation structure 11 of the first trench 101, and the size of the etched opening 111 in the first direction Y is less than or equal to the size of the first trench 101; Figure 5 Based on the etching opening 111, a portion of the substrate 100 is removed to form a plurality of third trenches 103. The third trenches 103 extend along the first direction Y and are located in the substrate 100 at the bottom of the first trench 101. The top of the third trench 103 is connected to the bottom of the first trench 101, and in the second direction X, adjacent third trenches 103 are connected to each other. It should be noted that the third trenches 103 are located in the substrate 100 at the bottom of the first trench 101, with reference to Figure 6 That is, in the first direction Y, the second trench 102 intercepts the third trench 103, and the first isolation structure 11 located in the second trench 102 can serve as a supporting structure to prevent the remaining substrate 100 between the first trenches 101 from collapsing and causing damage to the semiconductor structure.

[0047] It is understood that the size of the etching opening 111 in the first direction Y is less than or equal to the first trench 101, so that the first isolation structure 11 on the surface of the substrate 100 on the sidewall portion of the first trench 101 can be retained. This prevents the surface of the substrate 100 on the sidewall portion of the first trench 101 from being contaminated or damaged during the subsequent etching to form the third trench 103, thereby improving the stability of the semiconductor structure. Based on the remaining substrate 100 between the first trench 101 and the third trench 103, a transistor with a full-surround gate structure can be formed in a subsequent process to increase the contact area between the transistor channel region and the gate structure, thereby increasing the transistor's ability to control current in the semiconductor structure and thus improving the performance of the semiconductor structure. At the same time, the full-surround gate structure can form a three-dimensional transistor structure to increase the integration density of the semiconductor structure.

[0048] In some embodiments, the process of forming the etched opening 111 and removing a portion of the substrate 100 may be an etching process, and the etching may be dry etching or wet etching.

[0049] refer to Figure 7 , a second isolation structure 12 is formed to fill the first trench 101 and the third trench 103 , and a top surface of the second isolation structure 12 is flush with a top surface of the first isolation structure 11 .

[0050] The second isolation structure 12 may be formed of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the second isolation structure 12 is formed of the same material as the first isolation structure 11. In other embodiments, the second isolation structure 12 may be formed of a different material than the first isolation structure 11.

[0051] In some embodiments, the process of forming the second isolation junction 12 may be a deposition process, and the deposition process may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0052] A gate structure is formed, and the gate structure surrounds the substrate between the first trenches along the second direction. In the first direction, the projection of the gate structure and the projection of the second trenches are parallel to each other and alternately arranged.

[0053] Specifically, the steps of forming the gate structure include: referring to Figure 8 , the first isolation structure 11 and the second isolation structure 12 are removed along the second direction X to form a channel region, and the channel region exposes the surface of the substrate 100 of the first trench 101 and the third trench 103 in the second direction X. In the first direction Y, the channel region and the remaining first isolation structure 11 and the second isolation structure 12 are alternately arranged, and the projections of the channel region and the second trench 102 on the substrate 100 are parallel to each other and alternately arranged.

[0054] In some embodiments, the method of forming a channel region may include: forming a mask layer along a second direction, the mask layer covering the top surface of the first isolation structure and the second isolation structure above the second trench, and the width of the mask layer is greater than the width of the second trench; removing the first isolation structure and the second isolation structure outside the mask layer along the second direction, exposing the surface of the substrate to form a channel region, and removing the mask layer.

[0055] For the mask layer, in some embodiments, the material forming the mask layer can be silicon nitride, silicon carbonitride or silicon carbon nitride oxide; in other embodiments, the material of the mask layer can be photoresist, and the area that needs to be covered by the mask layer is defined based on the exposure range of the photoresist.

[0056] In some embodiments, the method of removing the first isolation structure and the second isolation structure outside the mask layer along the second direction to expose the surface of the substrate to form the channel region may be an etching process, and the etching process may be dry etching or wet etching.

[0057] Further, refer to Figures 9 and 10 After forming the channel region and before forming the gate structure, the method may further include performing rounding on the remaining substrate 100 between the first trenches 101 so that the morphology of the remaining substrate 100 exposed between the first trenches 101 conforms to a preset pattern. Figure 9 After removing the first isolation structure 11 and the second isolation structure 12 in the first trench 101 and the third trench 103, a tip will be formed on the surface of the remaining substrate 100. The tip will cause the formed gate structure to have tip discharge or leakage, affecting the performance of the semiconductor structure; Figure 10 After the rounded corners are processed, the surface of the substrate 100 has a smooth transition, which is beneficial to avoid tip discharge or leakage of the gate structure formed in the channel region, and further improves the electrical performance of the semiconductor structure.

[0058] It should be noted that in this embodiment, the preset pattern is cylindrical; in other embodiments, the preset pattern may also be an elliptical cylinder, a polygonal prism, or other irregular shapes. It is understood that when the preset pattern is a polygonal prism, the corners formed by the adjacent sidewalls of the polygonal prism can be rounded, which can also avoid the problem of tip discharge. The polygonal prism can be a cubic columnar structure or a rectangular parallelepiped columnar structure.

[0059] In some embodiments, the corner rounding process is implemented based on a thermal oxidation process, an etching process, and / or a hydrogen annealing process.

[0060] In some embodiments, continue to refer to Figure 10, after forming the channel region and before forming the gate structure, it also includes: flattening the substrate 100 at the bottom of the channel region. It can be understood that along the second direction X, the third trenches 103 are interconnected, and the substrate 100 between the bottoms of the third trenches 103 is prone to form tips, which causes the gate structure formed in the channel region to have tip discharge or leakage. Therefore, flattening the substrate 100 at the bottom of the channel region can improve the electrical performance of the semiconductor structure. It should be noted that in this embodiment, the substrate 100 at the bottom of the channel region is flattened to make the surface of the substrate 100 at the bottom of the channel region flat and smooth; in other embodiments, the flattening of the substrate 100 at the bottom of the channel region can only be used to round the tips. This embodiment does not limit the specific morphology of the flattening treatment.

[0061] refer to Figure 11 , filling the channel region to form a gate structure. Specifically, forming the gate structure 300 includes: forming a gate dielectric layer 301, the gate dielectric layer 301 surrounding the remaining surface of the substrate 100 between the first trenches 101 in the channel region and also covering the substrate 100 at the bottom of the third trench 103, that is, the gate dielectric layer 301 covers the surface of the substrate 100 in the channel region; and forming a gate conductive layer 302, the gate conductive layer 302 filling the gaps between the substrate 100 in the channel region. The gate dielectric layer 301 covers the surface of the substrate 100 between the first trenches 101 and also covers the surface of the substrate 100 at the bottom of the third trench 103, which can prevent the gate conductive layer 302 from reacting with the substrate 100 in subsequent processes, thereby preventing damage to the semiconductor structure.

[0062] Regarding the gate dielectric layer 301 , the material forming the gate dielectric layer 301 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0063] Regarding the gate conductive layer 302 , the material forming the gate conductive layer 302 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.

[0064] In some embodiments, the process of forming the gate dielectric layer 301 and the gate conductive layer 302 may be a deposition process, and the deposition process may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0065] Further, refer to Figure 12In some embodiments, after forming the gate structure 300, the following may be included: forming a third isolation structure 13, wherein the third isolation structure 13 covers the surface of the gate structure 300, and the top surface is flush with the top surface of the first isolation structure 11. The third isolation structure 13 covers the surface of the gate structure 300, which can protect the gate structure 300 from contamination or damage during subsequent processes, thereby avoiding affecting the performance of the semiconductor structure. At the same time, the third isolation structure 13 can isolate different devices from each other, avoiding damage to the semiconductor structure caused by conduction between adjacent devices. The top surface of the third isolation structure 13 is flush with the top surface of the first isolation structure 11, which can avoid a height difference between the first isolation structure 11 and the third isolation structure 13, thereby preventing impact on subsequent processes.

[0066] The third isolation structure 13 may be formed of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the third isolation structure 13 is formed of the same material as the first isolation structure 11. In other embodiments, the third isolation structure 13 may be formed of a different material than the first isolation structure 11.

[0067] In some embodiments, the process of forming the third isolation structure 13 may be a deposition process, and the deposition process may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0068] refer to Figure 13 , forming a conductive structure 400 , the conductive structure 400 is located in the second trench 102 , and in the first direction Y, the conductive structure 400 is spaced apart in the second trench 102 .

[0069] Specifically, the steps of forming the conductive structure include: patterning the first isolation structure and the second isolation structure to expose a portion of the height of the second trench at intervals in the first direction; and filling the second trench to form a conductive structure, wherein the conductive structure is spaced apart within the second trench in the first direction. Exposing the second trenches 102 at intervals in the first direction Y and forming the conductive structure 400 allows the same conductive structure 400 to connect the remaining substrate 100 between two adjacent rows of first trenches 101. In other words, the bitline structure formed by the same conductive structure 400 can be coupled to the transistors in two adjacent rows, thereby reducing the number of bitline structures, further miniaturizing the semiconductor structure, and improving the integration density of the semiconductor structure. This also simplifies the process flow for manufacturing the semiconductor structure and improves the manufacturing efficiency of the semiconductor structure.

[0070] In some embodiments, the material forming the conductive structure 400 includes at least one of metal silicide, copper, or tungsten. In other embodiments, the material forming the conductive structure 400 may be a single metal, a metal compound, or an alloy. The single metal may be copper, aluminum, tungsten, gold, or silver; the metal compound may be tantalum nitride or titanium nitride; and the alloy may be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. Using a metal material as the material of the conductive structure 400 can give the conductive structure 400 a lower resistivity, which is beneficial to the resistance of the conductive structure 400, increases the transmission rate of electrical signals in the conductive structure 400, reduces the parasitic capacitance of the conductive structure 400, and reduces heat loss to reduce power consumption.

[0071] Further, referring to FIG. 14( a ), in some embodiments, after forming the conductive structure 400, the method further includes: forming a fourth isolation junction 14, the fourth isolation structure 14 partially covering the surface of the first isolation structure 11, the second isolation structure 12, and the conductive structure 400; forming a plurality of bitline contact lines 401, the bitline contact lines 401 being located within the fourth isolation structure 14 and extending along a third direction Z; one end of the bitline contact line 401 being connected to the conductive structure 400 and the other end being connected to a bitline extension line 402, the bitline extension line 402 being located within the fourth isolation structure 14 and extending along a first direction Y. The angle between the third direction Z and the plane containing the first direction Y and the second direction X is greater than 0°. In this embodiment, the angle between the third direction Z and the plane containing the first direction Y and the second direction X is 90°. In other embodiments, the angle between the third direction Z and the plane containing the first direction Y and the second direction X may be 60° or 45°. This embodiment does not limit the angle between the third direction Z and the plane containing the first direction Y and the second direction X.

[0072] By using the bitline contact lines 401 and the bitline extension lines 402, the conductive structure 400 extending in the second direction X can be transformed to extend in the first direction Y, thereby differentiating the extension directions of the gate structure 300 and the conductive structure 400. This prevents mutual interference between the gate structure 300 and the conductive structure 400 during subsequent processing, thereby avoiding complexity in the semiconductor structure. It should be noted that, referring to the structural schematic diagram of the corresponding relationship between the conductive structure 400, the bitline contact lines 401, and the bitline extension lines 402 in FIG14( b ), each conductive structure 400 only needs to be connected to one set of bitline contact lines 401 and bitline extension lines 402. It can be understood that, along the second direction X, two rows of transistors can share one conductive structure 400. By forming a set of bitline contact lines 401 and bitline extension lines 402, one bitline extension line 402 can be coupled to multiple transistors contacted by the corresponding conductive structure 400.

[0073] The material of the bitline contact line 401 and the bitline extension line 402 can be at least one of metal silicide, copper, or tungsten. In other embodiments, the material forming the bitline contact line 401 and the bitline extension line 402 can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver; the metal compound can be tantalum nitride or titanium nitride; and the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver.

[0074] In some embodiments, the material forming the bit line contact line 401 may be the same as the material forming the conductive structure 400, and the material forming the bit line extension line 402 may be the same as the material forming the conductive structure 400; in other embodiments, the material forming the bit line contact line 401 may be different from the material forming the conductive structure 400, and the material forming the bit line extension line 402 may be different from the material forming the conductive structure 400.

[0075] Furthermore, refer to Figure 15 In some embodiments, after forming the conductive structure 400, the following steps are further included: forming a capacitor contact isolation layer 15, the capacitor contact isolation layer 15 covering the surface of the fourth isolation structure 14 and the bit line extension line 402; removing a portion of the first isolation structure 11 located within the second trench 102 to form a capacitor contact structure 501, the capacitor contact structure 501 extending along the third direction Z, with the capacitor contact structures 501 and the conductive structure 400 alternating in the first direction Y; and forming a capacitor structure on the capacitor contact structure 501. The capacitor contact structure 501 can couple the capacitor structure on the surface of the capacitor contact isolation layer 15 to the transistor. Furthermore, on the surface of the capacitor contact isolation layer 15, the capacitor structure can be arranged in a hexagonal closest packing manner to improve the space utilization of the semiconductor structure, thereby increasing the integration density of the semiconductor structure.

[0076] In some embodiments, the material forming the capacitor contact structure 501 may be at least one of metal silicides of tungsten, titanium, tantalum, copper, polysilicon, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0077] In other embodiments, the process of forming the capacitor contact structure can be performed simultaneously with the process of forming the conductive structure. Specifically, the first isolation structure and the second isolation structure are patterned to expose the second trench; the conductive structure and the capacitor contact structure are formed, and the conductive structure and the capacitor contact structure fill the second trench. The conductive structure and the capacitor contact structure are alternately arranged in the first direction, and each capacitor contact structure corresponds to a transistor. This can reduce the number of steps in fabricating the conductive structure and the capacitor contact structure, simplify the semiconductor structure fabrication process, and improve the efficiency of semiconductor structure fabrication.

[0078] The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure forms a plurality of first trenches 101 extending in a first direction Y, a plurality of second trenches 102 extending in a second direction X, and a plurality of third trenches 103 extending in the first direction Y. In the second direction X, a gate structure 300 is formed surrounding the substrate 100 between the first trenches 101 and the third trenches 103. In the first direction Y, conductive structures 400 are formed at intervals within the second trenches 102. The gate structure 300 surrounds the substrate 100 to form a transistor that fully surrounds the gate structure 300, increasing the contact area of ​​the transistor channel region and improving the transistor's ability to control current, thereby improving the performance and integration density of the semiconductor structure. Furthermore, along the second direction X, two adjacent rows of transistors are connected to the same conductive structure 400, meaning that the two rows of transistors share the same bit line. This improves the space utilization of the semiconductor structure, further increasing the integration density of the semiconductor structure, and also simplifies the bit line formation process of the semiconductor structure.

[0079] Another embodiment of the present disclosure provides a semiconductor structure that utilizes the above-described method for fabricating the semiconductor structure to improve the performance of the resulting semiconductor structure. It should be noted that for portions that are identical or corresponding to the above-described embodiments, reference may be made to the corresponding descriptions of the aforementioned embodiments, and will not be further elaborated upon below.

[0080] Continue to refer Figure 13 , the semiconductor structure provided by this embodiment includes:

[0081] The substrate 100 is provided with a plurality of first trenches 101 extending along a first direction Y, a plurality of second trenches 102 extending along a second direction X, and a plurality of third trenches 103 extending along the first direction Y, wherein the depth of the first trench 101 is less than the depth of the second trench 102, the third trench 103 is located in the substrate 100 at the bottom of the first trench 101, the top of the third trench 103 is connected to the bottom of the first trench 101, and in the second direction X, adjacent third trenches 103 are connected to each other; the gate structure 300 is located in the first trench 101 and the third trench 103, and is arranged in a circular manner along the second direction X. Around the substrate 100 located between the first trenches 101, the projection of the gate structure 300 and the projection of the second trenches 102 in the first direction Y are parallel and arranged alternately; the conductive structure 400 is located above the first isolation structure 11 in the second trench 102, and along the first direction Y, the conductive structure 400 is spaced apart in the second trench 102; the first isolation structure 11 fills the first trench 101 and the second trench 102 between the gate structure 300 and the conductive structure 400; the second isolation structure 12 fills the first trench 101 and the third trench 103 between the gate structure 300 and the conductive structure 400.

[0082] The substrate 100 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0083] The first isolation structure 11 and the second isolation structure 12 may be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the first isolation structure 11 is different from the material of the second isolation structure 12; in other embodiments, the material of the first isolation structure 11 is the same as the material of the second isolation structure 12. The first isolation structure 11 and the second isolation structure 12 are located between the gate structure 300 and the conductive structure 400, and the transistors formed by the isolation gate structure 300 and the conductive structure 400 can prevent the performance of the semiconductor structure from being degraded due to mutual conduction between different transistors, thereby increasing the stability of the semiconductor structure and improving the performance of the semiconductor structure.

[0084] Continue to refer Figure 13 In some embodiments, the gate structure 300 includes: a gate dielectric layer 301 covering the surface of the substrate 100 in the first trench 101 and the third trench 103; and a gate conductive layer 302 covering the surface of the gate dielectric layer 301 and filling the first trench 101 and the third trench 103. The gate structure 300 surrounds the channel region, and transistors in the same row along the second direction X share the same gate structure 300, simplifying the semiconductor structure's fabrication process and increasing its integration density. Furthermore, the fully surrounding gate structure increases the contact area of ​​the transistor channel region, improving the transistor's ability to control current, thereby enhancing the performance of the semiconductor structure.

[0085] Regarding the gate dielectric layer 301 , the material of the gate dielectric layer 301 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0086] Regarding the gate conductive layer 302 , the material of the gate conductive layer 302 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, or tungsten.

[0087] Referring to FIG. 14( a ), in some embodiments, the semiconductor structure further includes: a fourth isolation structure 14 covering the surfaces of the first isolation structure 11 , the second isolation structure 12 , and the conductive structure 400 ; a plurality of bitline contact lines 401 located within the fourth isolation structure 14 and extending along a third direction Z; one end of the bitline contact line 401 is connected to the conductive structure 400 , and the other end is connected to a bitline extension line 402 , which is located within the fourth isolation structure 14 and extends along a first direction Y. The bitline contact lines 401 and the bitline extension lines 402 can be used to transform the conductive structure 400 extending along the second direction X into extending along the first direction Y, thereby differentiating the extension directions of the gate structure 300 and the conductive structure 400 . This prevents mutual interference between the gate structure 300 and the conductive structure 400 during subsequent processing, thereby avoiding degradation of the semiconductor structure's performance.

[0088] refer to Figure 15 In some embodiments, the semiconductor structure further includes: a capacitor contact isolation layer 15 covering the surface of the fourth isolation structure 14 and the bit line extension line 402; a capacitor contact structure 501 located within the second trench 102 and extending along the third direction Z, wherein the angle between the third direction Z and the plane containing the first direction Y and the second direction X is greater than 0°; the capacitor contact structures 501 and the conductive structures 400 are alternately arranged along the first direction Y; and a capacitor structure located on the surface of the capacitor contact structure 501. The capacitor contact structures 501 enable coupling between the capacitor and the transistor. Furthermore, on the surface of the capacitor contact isolation layer 15, the capacitor structures can be arranged in a hexagonal closest packing manner in the first and second directions to improve the space utilization of the semiconductor structure, thereby increasing the integration density of the semiconductor structure.

[0089] In some embodiments, the material of the capacitor contact structure 501 may be at least one of metal silicides of tungsten, titanium, tantalum, copper, polysilicon, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0090] The semiconductor structure provided by the present disclosure utilizes the semiconductor structure fabrication method described in the aforementioned embodiment to form transistors having a fully wrapped gate structure. Transistors in the same row share the same gate structure, simplifying the semiconductor structure's fabrication process and improving its integration density. The fully wrapped gate structure increases the contact area of ​​the transistor channel region, enhancing the transistor's ability to control current, thereby improving the semiconductor structure's performance. Furthermore, along the second direction, transistors in two adjacent rows are coupled to the same conductive structure, meaning that transistors in two adjacent rows share the same bit line. This simplifies the semiconductor structure's fabrication process, improves the semiconductor structure's space utilization, and further increases its integration density.

[0091] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, on which a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction are provided, wherein the depth of the first trenches is smaller than the depth of the second trenches; forming a first isolation structure covering the substrate and filling the first trench and the second trench; forming a plurality of third trenches, wherein the third trenches are located in the substrate at the bottom of the first trench and extend along the first direction; forming a second isolation structure to fill the first trench and the third trench; forming a gate structure, wherein the gate structure surrounds the substrate between the first trenches along the second direction, wherein a projection of the gate structure and a projection of the second trenches are parallel to each other and alternately arranged in the first direction; A conductive structure is formed, where the conductive structure is located in the second trench, and in the first direction, the conductive structure is spaced apart in the second trench.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming the first isolation structure includes: forming a first isolation layer, wherein the first isolation layer fills the first trench and covers the top surface of the substrate; A second isolation layer is formed, where the second isolation layer fills the second trench, and a top surface of the second isolation layer is flush with a top surface of the first isolation layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The material forming the first isolation layer is different from the material forming the second isolation layer.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming a plurality of third trenches includes: forming an etched opening, wherein the etched opening is located within the first isolation structure of the first trench, and a size of the etched opening in the first direction is smaller than or equal to a size of the first trench; The third trenches are formed based on the etched openings, and the adjacent third trenches are connected to each other in the second direction.

5. The method for manufacturing a semiconductor structure according to claim 1 , wherein the step of forming a gate structure comprises: forming a channel region, wherein the channel region exposes the substrate surface of the first trench and the third trench along the second direction, and a projection of the channel region and a projection of the second trench in the first direction are parallel to each other and alternately arranged; The channel region is filled to form the gate structure.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: After forming the channel region and before forming the gate structure, the method further includes performing rounding on the substrate between the first trenches so that the morphology of the substrate exposed between the first trenches conforms to a preset pattern.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The rounded corner processing is achieved based on a thermal oxidation process, an etching process and / or a hydrogen annealing process.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The preset shapes include: cylindrical, elliptical or polygonal shapes.

9. The method for manufacturing a semiconductor structure according to claim 5, wherein: After forming the channel region and before forming the gate structure, the method further includes: performing a planarization process on the substrate at the bottom of the channel region.

10. The method for manufacturing a semiconductor structure according to claim 5, wherein: Forming the gate structure includes: forming a gate dielectric layer, wherein the gate dielectric layer covers the surface of the substrate in the channel region; A gate conductive layer is formed, wherein the gate conductive layer fills the gap between the substrates in the channel region.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the gate structure and before forming the conductive structure, the method further includes: forming a third isolation structure, wherein the third isolation structure covers the top surface of the gate structure and the top is flush with the top surface of the first isolation structure.

12. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming the conductive structure includes: patterning the first isolation structure and the second isolation structure to expose the second trenches at intervals in the first direction; The second trench is filled to form the conductive structure.

13. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material forming the conductive structure includes at least one of metal silicide, copper or tungsten.

14. The method for manufacturing a semiconductor structure according to claim 1, wherein: An included angle between the first direction and the second direction is greater than 0°.

15. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the conductive structure, the method further includes: forming a fourth isolation structure, wherein the fourth isolation structure covers surfaces of the first isolation structure, the second isolation structure, the gate structure, and the conductive structure; A plurality of bit line contact lines are formed, wherein the bit line contact lines are located in the fourth isolation structure and extend along the third direction; one end of the bit line contact line is connected to the conductive structure, and the other end is connected to the bit line extension line, wherein the bit line extension line is located in the fourth isolation structure and extends along the first direction.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein: An angle formed between the third direction and a plane containing the first direction and the second direction is greater than 0°.

17. The method for manufacturing a semiconductor structure according to claim 15, wherein: After forming the conductive structure, the method further includes: forming a capacitor contact isolation layer, wherein the capacitor contact isolation layer covers surfaces of the fourth isolation structure and the bit line extension line; forming a capacitor contact, wherein the capacitor contact structure is located in the second trench and the capacitor contact isolation layer and extends along the third direction, and the capacitor contact structure and the conductive structure are alternately arranged in the first direction; A capacitor structure is formed, wherein the capacitor structure is located on a top surface of the capacitor contact structure.

18. A semiconductor structure, comprising the method for manufacturing the semiconductor structure according to any one of claims 1 to 17, wherein: include: a substrate, wherein a plurality of first trenches extending along the first direction, a plurality of second trenches extending along the second direction, and a plurality of third trenches extending along the first direction are provided on the substrate, wherein the depth of the first trenches is smaller than the depth of the second trenches, and the third trenches are located in the substrate at the bottom of the first trenches; a gate structure surrounding the substrate between the first trenches along the second direction, wherein in the first direction, a projection of the gate structure and a projection of the second trenches are parallel and arranged alternately; a conductive structure located in the second trench, and along the first direction, the conductive structures are arranged in the second trench at intervals; a first isolation structure filling the first trench and the second trench between the gate structure and the conductive structure; A second isolation structure is filled in the first trench and the third trench between the gate structure and the conductive structure.

19. The semiconductor structure according to claim 18, wherein: The gate structure includes: a gate dielectric layer covering the substrate surface of the first trench and the third trench; A gate conductive layer covers the surface of the gate dielectric layer and fills the first trench and the third trench.

20. The semiconductor structure according to claim 18, wherein Also includes: a fourth isolation structure covering top surfaces of the first isolation structure, the second isolation structure, the gate structure, and the conductive structure; a plurality of bit line contact lines, located in the fourth isolation structure and extending along a third direction; One end of the bit line contact line is connected to the conductive structure, and the other end is connected to a bit line extension line. The bit line extension line is located in the fourth isolation structure and extends along the first direction.

21. The semiconductor structure according to claim 20, wherein Also includes: a capacitor contact isolation layer covering surfaces of the fourth isolation structure and the bit line extension line; a capacitor contact structure, located in the second trench and the capacitor contact isolation layer, extending along the third direction, wherein the capacitor contact structure and the conductive structure are alternately arranged in the first direction; The capacitor structure is located on the top surface of the capacitor contact structure.

22. The semiconductor structure according to claim 21, wherein The capacitor structures are arranged in a hexagonal pattern in the first direction and the second direction.

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