A method for preparing a superconducting integrated circuit device

Abstract

The present invention provides a method for preparing a superconducting integrated circuit device. When forming a third insulating material layer, a certain thickness of insulating material is first deposited on the surface of the third superconducting material layer to form the third insulating material layer. Since the third insulating material layer is relatively thick, it is easy to form bulges at convex corners. Then, the third insulating material layer having a first thickness is removed by ion beam etching, thereby eliminating the bulges. Finally, insulating material having a first thickness is redeposited on the surface of the above structure, ultimately obtaining a third insulating material layer having a smooth surface. The method for preparing a superconducting integrated circuit device provided by the present invention solves the problem of bulges that are easily generated when forming a thick insulating material layer, thereby effectively improving the etching residue problem of the inductor layer of the superconducting integrated device and avoiding the short circuit problem that is easily generated when the metal connection within the layer is connected. In addition, the method for preparing a superconducting integrated circuit device provided by the present invention is simple to operate and greatly improves production efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of superconducting integrated circuit device design, and in particular to a method for preparing a superconducting integrated circuit device. Background Art

[0002] In recent years, superconducting electronics has found widespread application in fields such as quantum computing, high-performance digital integrated circuits, highly sensitive magnetic field detection, and precision physical quantity calibration. Superconducting integrated circuit devices are a key technology within this field. Superconducting integrated circuit devices are typically composed of a Josephson junction, a resistor, and an inductor. These two components are the primary structures of superconducting integrated circuits. Josephson junctions are fabricated from multilayer superconducting thin films. Inductors are typically fabricated from superconducting Nb through growth, photolithography, and etching, with SiO2 used as an insulating layer between the metal layers.

[0003] During device fabrication, to ensure complete coverage of the steps in each film layer, the film thickness is increased incrementally. This means that as the thickness of the metal Nb layer increases, the thickness of the insulating SiO2 layer also increases. However, thicker SiO2 layers have larger step fluctuations, which can easily form bulges at convex corners. This causes the SiO2 layer covering the metal Nb to bulge at these corners, which in turn creates narrow concave areas. Etching of the upper metal Nb layer can leave etch residue trapped in these dead corners, leading to short circuits in the metal connections within the final layer. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention provides a method for preparing a superconducting integrated circuit device. When forming a third insulating material layer, a certain thickness of insulating material is first deposited on the surface of the third superconducting material layer to form the third insulating material layer. Since the thickness of the third insulating material layer is relatively large, it is easy to form bulges at the convex corners; then, the third insulating material layer with the first thickness is removed by ion beam etching, thereby eliminating the bulges; finally, the insulating material with the first thickness is re-deposited on the surface of the above structure, and finally a third insulating material layer with a smooth surface is obtained. The method for preparing a superconducting integrated circuit device provided by the present invention solves the problem of bulges that are easy to generate when forming a thick insulating material layer, thereby effectively improving the etching residue problem of the inductor layer of the superconducting integrated device and avoiding the short circuit problem that is easy to generate when the metal connection within the layer is connected; and the method for preparing a superconducting integrated circuit device provided by the present invention is simple to operate, greatly improving production efficiency.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a superconducting integrated circuit device, comprising the following steps:

[0006] S1: providing a substrate and forming a bypass resistor on the substrate;

[0007] S2: forming a patterned first insulating material layer having a first opening on the surface of the structure obtained in step S1, wherein the first opening exposes the bypass resistor;

[0008] S3: forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer in sequence on the surface of the structure obtained in step S2, and etching the three-layer thin film structure to form a Josephson junction;

[0009] S4: forming a patterned second insulating material layer and a patterned third superconducting material layer in sequence on the surface of the structure obtained in step S3;

[0010] S5: depositing an insulating material on the surface of the structure obtained in step S4 to form a patterned third insulating material layer, and trimming the third insulating material layer by ion beam etching to remove the insulating material having the first thickness, thereby obtaining the third insulating material layer having a flat surface;

[0011] S6: depositing the insulating material with a first thickness on the surface of the structure obtained in step S5, and patterning the third insulating material layer.

[0012] Optionally, after step S6, the method further includes: forming a patterned fourth superconducting material layer on the surface of the structure obtained in step S6.

[0013] Optionally, in step S4, the second insulating material layer is etched to form a second opening, and the second opening exposes the upper surface of the Josephson junction.

[0014] Optionally, the bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer.

[0015] Optionally, the first superconducting material layer includes at least one of a niobium nitride layer and a niobium layer; the second superconducting material layer includes at least one of a niobium nitride layer and a niobium layer; and the barrier material layer includes at least one of an aluminum oxide layer and an aluminum nitride layer.

[0016] Optionally, the first superconducting material layer is a niobium layer; the second superconducting material layer is a niobium layer; and the barrier material layer is a stack of an aluminum layer and an aluminum oxide layer or a stack of an aluminum layer and an aluminum nitride layer.

[0017] Optionally, the material of the first insulating material layer includes SiO2 or SiN x .

[0018] Optionally, the first thickness is between 100 nm and 150 nm.

[0019] Optionally, the thickness of the first superconducting material layer is between 150 nm and 170 nm; the thickness of the third superconducting material layer is between 300 nm and 330 nm; and the thickness of the fourth superconducting material layer is between 500 nm and 540 nm.

[0020] Optionally, the thickness of the first insulating material layer is between 100 nm and 120 nm; the thickness of the second insulating material layer is between 250 nm and 280 nm; and the thickness of the third insulating material layer is between 350 nm and 420 nm.

[0021] The method for preparing a superconducting integrated circuit device provided by the present invention has at least the following technical effects:

[0022] The method for preparing a superconducting integrated circuit device provided by the present invention solves the problem of bulging that is easily generated when forming a thick insulating material layer, thereby effectively improving the etching residue problem of the inductor layer of the superconducting integrated device and avoiding the short circuit problem that is easily generated when the metal connection within the layer; and the method for preparing a superconducting integrated circuit device provided by the present invention is simple to operate, greatly improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A flow chart showing a method for manufacturing a superconducting integrated circuit device according to an embodiment is shown.

[0024] Figure 2 A schematic diagram showing the structure obtained in step S1 of the embodiment is shown.

[0025] Figure 3 Shown as Figure 2 Schematic diagram of the structure in which a first insulating material layer is formed on the surface of the structure.

[0026] Figure 4 Shown as Figure 3 Schematic diagram of the structure with a three-layer thin film structure formed on the surface of the structure.

[0027] Figure 5 Shown is a schematic structural diagram of the Josephson junction obtained in step S3 of the embodiment.

[0028] Figure 6 Shown as Figure 5 Schematic diagram of the structure with a second insulating material layer formed on the surface of the structure.

[0029] Figure 7 Shown as Figure 6 Schematic diagram of the structure in which a third superconducting material layer is formed on the surface of the structure.

[0030] Figure 8 Shown as Figure 7 Schematic diagram of a structure in which a third insulating material layer with bulges is formed on the surface of the structure.

[0031] Figure 9 The schematic diagram shows a structure in which a third insulating material layer having a first thickness is removed.

[0032] Figure 10 Shown is a schematic structural diagram of the superconducting integrated circuit device obtained in step S6 of the embodiment.

[0033] Component number description

[0034] 1 substrate

[0035] 2. Bypass resistor

[0036] 3. First insulating material layer

[0037] 30 First opening

[0038] 4 First superconducting material layer

[0039] 5 Barrier material layer

[0040] 6 Second superconducting material layer

[0041] 40 lower electrode layer

[0042] 50 Barrier layer

[0043] 60 Upper electrode layer

[0044] 7 Second insulating material layer

[0045] 70 Second opening

[0046] 8 The third superconducting material layer

[0047] 9 Third insulating material layer

[0048] 10 Fourth superconducting material layer DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0051] Example

[0052] This embodiment provides a method for preparing a superconducting integrated circuit device, such as Figure 1 As shown, the following steps are included:

[0053] S1: providing a substrate 1 and forming a bypass resistor 2 on the substrate 1;

[0054] As an example, the substrate 1 may include at least one of a silicon substrate, a silicon oxide substrate, a magnesium oxide substrate, a sapphire substrate and a silicon carbide substrate, but is not limited thereto. Any substrate suitable for preparing superconducting integrated circuit devices may be used.

[0055] As an example, the specific method of forming the bypass resistor 2 includes: first forming a bypass resistor material layer on the substrate 1, and then performing photolithography-etching on the bypass resistor material layer to achieve patterning of the bypass resistor material layer to obtain the bypass resistor 2, referring to Figure 2 As shown. As an example, the bypass resistor 2 can be a single Mo layer; it can also be a stacked structure of a Pd layer and a Ti layer, where the Ti layer serves as an adhesion layer and the Pd layer serves as the main resistance material layer. The Ti layer can achieve good adhesion between the substrate and the Pd layer. Generally, the thickness of the Ti layer is relatively thin, about 6nm to 20nm. The thickness of the Pd layer is set according to the specific resistance size requirements, generally between 20nm and 100nm.

[0056] S2: forming a patterned first insulating material layer 3 having a first opening 30 on the surface of the structure obtained in step S1, wherein the first opening 30 exposes the bypass resistor 2;

[0057] First, a first insulating material layer 3 is formed on the surface of the structure obtained in step S1 by using plasma enhanced chemical vapor deposition (PECVD). As an example, the thickness of the first insulating material layer 3 is between 100nm and 120nm; the material of the first insulating material layer 3 includes SiO2 or SiN x However, it is not limited thereto, and other materials with better insulation performance may also be used.

[0058] Then, if Figure 3 As shown, the first insulating material layer 3 is patterned by photolithography and etching to form a first opening 30 , and the first opening 30 exposes the bypass resistor 2 .

[0059] S3: forming a three-layer thin film structure of a first superconducting material layer 4, a barrier material layer 5, and a second superconducting material layer 6 in sequence on the surface of the structure obtained in step S2, and etching the three-layer thin film structure to form a Josephson junction;

[0060] First, if Figure 4 As shown, a first superconducting material layer 4, a barrier material layer 5, and a second superconducting material layer 6 are sequentially formed on the surface of the structure obtained in step S2. As an example, the first superconducting material layer 4 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be a laminated structure composed of one of them or two of them; the second superconducting material layer 6 includes at least one of a niobium nitride layer and a niobium layer, that is, it can be a laminated structure composed of one of them or two of them; in addition, the barrier material layer 5 is an aluminum-containing material layer, which includes at least one of an aluminum layer, an aluminum oxide layer and an aluminum nitride layer, that is, it can be a laminated structure composed of one of them or two or more of them. In this embodiment, the first superconducting material layer 4 is a Nb layer, and the thickness of the first superconducting material layer 4 is between 150nm and 170nm; the second superconducting material layer 6 is a Nb layer; the barrier material layer 5 is Al-AlO x layer.

[0061] Then, if Figure 5 As shown, the three-layer thin film structure is etched from top to bottom using different patterns to form a Josephson junction. Specifically, the second superconducting material layer 6 is first photolithographically etched to form the upper electrode layer 60; then the barrier material layer 5 is photolithographically etched to form the barrier layer 50; and finally, the first superconducting material layer 4 is photolithographically etched to form the lower electrode layer 40. Simultaneously, the lower electrode layer 40 is electrically connected to the shunt resistor 2. In this embodiment, the upper electrode layer 60, the barrier layer 50, and the lower electrode layer 40 collectively form a Josephson junction. Furthermore, the shape and layout of the upper electrode layer 60, the barrier layer 50, and the lower electrode layer 40 can be designed according to actual needs.

[0062] S4: forming a patterned second insulating material layer and a patterned third superconducting material layer in sequence on the surface of the structure obtained in step S3;

[0063] First, a second insulating material layer 7 is formed on the surface of the structure obtained in step S3. As an example, the thickness of the second insulating material layer 7 is greater than that of the first insulating material layer 3, ranging from 250nm to 280nm; the material of the second insulating material layer 7 includes SiO2 or SiN x But it is not limited to this, other materials with better insulation performance can also be used. Figure 6 As shown, the second insulating material layer 7 is patterned by photolithography-etching to form a second opening 70 , and the second opening 70 exposes the upper surface of the Josephson junction, that is, the upper surface of the upper electrode layer 60 .

[0064] Next, a third superconducting material layer 8 is formed on the surface of the above structure. In this embodiment, the third superconducting material layer 8 is a Nb layer. The thickness of the third superconducting material layer 8 is greater than that of the first superconducting material layer 4, ranging from 300nm to 330nm, preferably 300nm. Finally, the third superconducting material layer 8 is subjected to photolithography-etching to obtain the following: Figure 7 A patterned third superconducting material layer 8 is shown.

[0065] S5: depositing an insulating material on the surface of the structure obtained in step S4 to form a patterned third insulating material layer, and trimming the third insulating material layer by ion beam etching to remove the insulating material having the first thickness, thereby obtaining the third insulating material layer having a flat surface;

[0066] First, an insulating material is deposited on the surface of the structure obtained in step S4 to form a third insulating material layer 9, and the third insulating material layer 9 is patterned. As an example, the thickness of the third insulating material layer 9 is greater than that of the second insulating material layer 7, ranging from 350nm to 420nm, preferably 400nm; the material of the third insulating material layer 9 includes SiO2 or SiN x But it is not limited to this, other materials with better insulation performance can also be used. Figure 8 As shown, since the third insulating material layer 9 is thicker, it has greater undulations at the steps, which easily forms bulges at the convex corners.

[0067] Next, the third insulating material layer 9 is trimmed by ion beam etching to remove the insulating material having the first thickness, and then subjected to degumming, cleaning, and drying treatment to obtain the third insulating material layer 9 having a flat surface. Figure 9 As shown, as an example, the first thickness is between 100 nm and 150 nm, preferably 100 nm.

[0068] S6: depositing the insulating material with a first thickness on the surface of the structure obtained in step S5, and patterning the third insulating material layer.

[0069] As an example, an insulating material having a first thickness is deposited on the surface of the structure obtained in step S5 using plasma enhanced chemical vapor deposition (PECVD), ultimately obtaining a third insulating material layer 9 having a smooth surface, and patterning the third insulating material layer 9. In this embodiment, the first thickness is between 100 nm and 150 nm, preferably 100 nm; the thickness of the third insulating material layer 9 ultimately obtained is between 350 nm and 420 nm, preferably 400 nm.

[0070] Finally, if Figure 10As shown, a patterned fourth superconducting material layer 10 is formed on the surface of the above structure to facilitate the extraction of corresponding electrical signals, thereby grounding the superconducting integrated circuit device and shielding external noise. As an example, the thickness of the fourth superconducting material layer 10 is between 500nm and 540nm.

[0071] It should be noted that the materials of the insulating material layers used in the preparation method of the superconducting integrated circuit device of this embodiment, such as the first insulating material layer 3, the second insulating material layer 7 and the third insulating material layer 9, can be kept consistent, thereby achieving homogeneous growth of the insulating material layers. There is no obvious interface during homogeneous growth, and there is no impact on subsequent processes.

[0072] The method for preparing a superconducting integrated circuit device provided by the present invention, when forming a third insulating material layer, first deposits a certain thickness of insulating material on the surface of the third superconducting material layer to form the third insulating material layer. Since the third insulating material layer is relatively thick, it is easy to form bulges at convex corners; then, the third insulating material layer having a first thickness is removed by ion beam etching, thereby eliminating the bulges; finally, insulating material having a first thickness is re-deposited on the surface of the above structure, ultimately obtaining a third insulating material layer with a smooth surface. The method for preparing a superconducting integrated circuit device provided by the present invention solves the problem of bulges that are easy to generate when forming a thick insulating material layer, thereby effectively improving the etching residue problem of the inductor layer of the superconducting integrated device and avoiding the short circuit problem that is easy to generate when the metal connection within the layer; and the method for preparing a superconducting integrated circuit device provided by the present invention is simple to operate, greatly improving production efficiency.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a superconducting integrated circuit device, characterized in that: The steps include: S1: providing a substrate and forming a bypass resistor on the substrate; S2: forming a patterned first insulating material layer having a first opening on the surface of the structure obtained in step S1, wherein the first opening exposes the bypass resistor; S3: forming a three-layer thin film structure of a first superconducting material layer, a barrier material layer, and a second superconducting material layer in sequence on the surface of the structure obtained in step S2, and etching the three-layer thin film structure to form a Josephson junction; S4: forming a patterned second insulating material layer and a patterned third superconducting material layer in sequence on the surface of the structure obtained in step S3; S5: depositing an insulating material on the surface of the structure obtained in step S4 to form a patterned third insulating material layer, and trimming the third insulating material layer by ion beam etching to remove the insulating material having the first thickness, thereby obtaining the third insulating material layer having a flat surface; S6: depositing the insulating material with a first thickness on the surface of the structure obtained in step S5, and patterning the third insulating material layer.

2. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: After step S6, the method further includes: forming a patterned fourth superconducting material layer on the surface of the structure obtained in step S6.

3. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: In step S4, the second insulating material layer is etched to form a second opening, and the second opening exposes the upper surface of the Josephson junction.

4. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: The bypass resistor is a Mo layer, or a stack of a Pd layer and a Ti layer.

5. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: The first superconducting material layer includes at least one of a niobium nitride layer and a niobium layer; the second superconducting material layer includes at least one of a niobium nitride layer and a niobium layer; and the barrier material layer includes at least one of an aluminum oxide layer and an aluminum nitride layer.

6. The method for preparing a superconducting integrated circuit device according to claim 5, wherein: The first superconducting material layer is a niobium layer; the second superconducting material layer is a niobium layer; and the barrier material layer is a stack of an aluminum layer and an aluminum oxide layer or a stack of an aluminum layer and an aluminum nitride layer.

7. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: The material of the first insulating material layer includes SiO2 or SiN x .

8. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: The first thickness is between 100 nm and 150 nm.

9. The method for preparing a superconducting integrated circuit device according to claim 2, wherein: The thickness of the first superconducting material layer is between 150 nm and 170 nm; the thickness of the third superconducting material layer is between 300 nm and 330 nm; and the thickness of the fourth superconducting material layer is between 500 nm and 540 nm.

10. The method for preparing a superconducting integrated circuit device according to claim 1, wherein: The thickness of the first insulating material layer is between 100 nm and 120 nm; the thickness of the second insulating material layer is between 250 nm and 280 nm; and the thickness of the third insulating material layer is between 350 nm and 420 nm.

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