An accumulator, multiplier and operator circuit

Abstract

The application provides an accumulator, a multiplier and an operator circuit, relates to the technical field of electronics, and is used for reducing the area and power consumption of the accumulator. The accumulator comprises W compressor layers, wherein W is an integer greater than or equal to 1; wherein the W compressor layers comprise at least one first compressor layer, in an input array of each first compressor layer, a first array comprises a plurality of positive-phase bit positions, a second array comprises a plurality of negative-phase bit positions, each first compressor layer comprises first compression circuitry for compressing the first array and second compression circuitry for compressing the second array, that is, different-phase bit positions in the input array of each first compressor layer are compressed by different compression circuitry.

Description

TECHNICAL FIELD

[0001] The present application relates to the electronic technical field, in particular to an accumulator, a multiplier and an operator circuit. BACKGROUND

[0002] The accumulator is a commonly used computing circuit in digital circuit design, which can be used to implement addition (or accumulation) of multiple binary numbers, for example, to implement the addition of "y=x0[7:0]+x1[7:0]+x2[7:0]+..." shown in (a) in the following formula. Figure 1 The accumulator can also be applied in a multiplier to implement the accumulation of multiple binary numbers in multiplication, for example, to implement the accumulation of multiple binary numbers in "y=x0[7:0]x1[7:0]" shown in (b) in the following formula. Figure 1 B0 to B7 in the formula correspond to different digits (i.e. 2 0 to 2 7 ). Figure 1

[0003] In the prior art, the accumulator is implemented based on the compression method of Wallace tree, and multiple standard adders (including full adders and half adders) are used to compress the bit positions of each digit in multiple digits layer by layer, and two accumulation values are obtained after multiple layers of compression, and finally the two accumulation values are added to obtain the final result. For example, as shown in Figure 2 , for the accumulation calculation in an 8bitsx8bits multiplier, the multiple binary numbers to be accumulated can be compressed into two rows (each row represents an accumulation value) by four compressor layers, and each compressor layer includes multiple standard adders. Wallace tree is an existing method for efficient accumulation. The bit positions of different digits in the same layer can be compressed in parallel, and the delay of each layer is the delay of a standard full adder, so it has the characteristics of fast calculation speed.

[0004] However, in the accumulator implemented based on the above Wallace tree method, a large number of standard adders (mainly full adders) are used, and the standard adder requires that the input bit position and the output bit position are in phase when performing multi-bit position compression, so that the standard adder needs to include a functional circuit for performing phase unification, which will cause the accumulator to have the problems of large area and high power consumption. SUMMARY

[0005] The present application provides an accumulator, a multiplier and an operator circuit for reducing the implementation difficulty of the accumulator, thereby reducing the area and power consumption. In order to achieve the above purpose, the present application adopts the following technical solutions:

[0006] ​In a first aspect, an accumulator is provided, comprising W compressor layers, W being an integer greater than or equal to 1; the W compressor layers are configured to compress a plurality of binary numbers to obtain a plurality of accumulated values, a sum of the plurality of accumulated values being an accumulated sum of the plurality of binary numbers; wherein the W compressor layers comprise at least one first compressor layer, each first compressor layer being configured to compress an input array to obtain an output array, the input array comprising a first array and a second array, the first array comprising a plurality of positive phase bit positions, the second array comprising a plurality of negative phase bit positions, the output array comprising a first compressed array and a second compressed array; wherein each first compressor layer comprises: a first compression circuit configured to compress the first array to obtain the first compressed array; and a second compression circuit configured to compress the second array to obtain the second compressed array.

[0007] In the above technical solution, the W compressor layers comprise at least one first compressor layer, in the input array of each first compressor layer, the first array comprises a plurality of positive phase bit positions, and the second array comprises a plurality of negative phase bit positions, so that the first array can be considered as a Wallace tree comprising a plurality of positive phase bit positions, and the second array can be considered as a Wallace tree comprising a plurality of negative phase bit positions. That is, the input array of each first compressor layer comprises two Wallace trees, and the bit positions included in the two Wallace trees are opposite in phase. For the first array and the second array included in the input array of each first compressor layer, the first compression circuit is configured to compress the first array, and the second compression circuit is configured to compress the second array, so that the bit positions of different phases in the input array can be compressed by different compression circuits, so that it is not necessary to unify the bit positions in the input array of each first compressor layer to the same phase, and therefore it is not necessary to add a functional circuit for performing phase unification processing, so that the accumulator is simple in design relative to a conventional design, and can reduce area and power consumption.

[0008] In a possible implementation manner of the first aspect, the first compression circuit comprises one or more first compressors, each of the one or more first compressors being configured to compress three bit positions at the same digit position in the first array; and the second compression circuit comprises one or more second compressors, each of the one or more second compressors being configured to compress three bit positions at the same digit position in the second array. In the above possible implementation manner, the one or more first compressors in the first compression circuit and the one or more second compressors in the second compression circuit can be used in parallel to compress the bit positions at the corresponding digit positions, so as to improve the compression efficiency of each first compressor layer.

[0009] In a possible implementation form of the first aspect, each of the first compressors and the second compressors is a subtractive carry adder; the subtractive carry adder is configured to compress the three bits to obtain a carry output bit and a sum output bit, the phase of the carry output bit is the same as that of the three bits, and the phase of the sum output bit is opposite to that of the three bits. In the possible implementation form, a subtractive carry adder is provided, and the implementation scheme of the subtractive carry adder is relatively simple, for example, small area and low power consumption.

[0010] In a possible implementation form of the first aspect, the subtractive carry adder is configured to perform the following compression: if the three bits are all 0, the carry output bit is 0, and the sum output bit is 1; if the three bits are all 1, the carry output bit is 1, and the sum output bit is 0; if one bit of the three bits is 1, and the other two bits are 0, the carry output bit is 0, and the sum output bit is 0; and if two bits of the three bits are 1, and the other bit is 0, the carry output bit is 1, and the sum output bit is 1. In the possible implementation form, a simple and effective compression manner of a subtractive carry adder is provided.

[0011] In a possible implementation form of the first aspect, each of the first compressors and the second compressors is a subtractive carry adder; the subtractive carry adder is configured to compress the three bits to obtain a carry output bit and a sum output bit, the phase of the carry output bit is the same as that of the three bits, and the phase of the sum output bit is opposite to that of the three bits. In the possible implementation form, a subtractive carry adder is provided, and the implementation scheme of the subtractive carry adder is relatively simple, for example, small area and low power consumption.

[0012] In a possible implementation form of the first aspect, the subtractive carry adder is configured to perform the following compression: if the three bits are all 0, the carry output bit is 0, and the sum output bit is 1; if the three bits are all 1, the carry output bit is 1, and the sum output bit is 0; if one bit of the three bits is 1, and the other two bits are 0, the carry output bit is 0, and the sum output bit is 0; and if two bits of the three bits are 1, and the other bit is 0, the carry output bit is 1, and the sum output bit is 1. In the possible implementation form, a simple and effective compression manner of a subtractive carry adder is provided.

[0013] In a possible implementation of the first aspect, each of the first compressors and the second compressors is a double-inversion adder, configured to compress the three bits to obtain a carry output bit and a sum output bit, phases of the carry output bit and the sum output bit being opposite to a phase of the three bits. In the possible implementation, a double-inversion adder is provided, and the double-inversion adder has a relatively simple implementation scheme, for example, small area and low power consumption.

[0014] In a possible implementation of the first aspect, the double-inversion adder is configured to perform the following compression: if the three bits are all 0, the carry output bit is 1 and the sum output bit is 1; if the three bits are all 1, the carry output bit is 0 and the sum output bit is 0; if one bit of the three bits is 1 and the other two bits are 0, the carry output bit is 1 and the sum output bit is 0; if two bits of the three bits are 1 and the other bit is 0, the carry output bit is 0 and the sum output bit is 1. In the possible implementation, a simple and effective compression manner of a double-inversion adder is provided.

[0015] In a possible implementation of the first aspect, the accumulator further includes a summing circuit configured to receive the plurality of accumulated values and sum the plurality of accumulated values to obtain the accumulated sum.

[0016] In a possible implementation of the first aspect, the accumulator further includes one or more inverters configured to invert at least one of the sum output bit and the carry output bit output by one or more of the first compressors or the second compressors in the W compressor layers, or invert the three bits input to the one or more of the first compressors or the second compressors. In the possible implementation, the compression efficiency of the W compressor layers can be improved while ensuring the accuracy of the compression result.

[0017] In a second aspect, a multiplier is provided, including an encoder and an accumulator, the accumulator being the accumulator provided in the first aspect or any possible implementation of the first aspect.

[0018] In a third aspect, an operator circuit is provided, which, when applied to an accumulator, can serve as an adder in a compressor layer of the accumulator, and the adder is an inverting sum adder, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor; wherein the first transistor and the second transistor are coupled in parallel between a power supply end and a first node; the third transistor is coupled between the first node and a second node; the fourth transistor is coupled between the second node and a third node; the fifth transistor and the sixth transistor are coupled in parallel between the third node and a ground end; the seventh transistor is coupled between the power supply end and a fourth node; the eighth transistor is coupled between the second node and the fourth node; the ninth transistor is coupled between the second node and a fifth node; the tenth transistor and the eleventh transistor are coupled in series between the fourth node and a first output end; the twelfth transistor and the thirteenth transistor are coupled in series between the fifth node and the first output end; the fourteenth transistor is coupled between the fifth node and the ground end; the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are coupled in parallel between the power supply end and a sixth node; the eighteenth transistor is coupled between the first output end and the sixth node; the nineteenth transistor is coupled between the first output end and a seventh node; the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are coupled in parallel between the seventh node and the ground end; control ends of the third transistor, the fourth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, and the twentieth transistor are all used to receive a first input; control ends of the first transistor, the fifth transistor, the seventh transistor, the fourteenth transistor, the sixteenth transistor, and the twenty-first transistor are all used to receive a second input; control ends of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the seventeenth transistor, and the twenty-second transistor are all used to receive a third input; control ends of the eighteenth transistor and the nineteenth transistor are both coupled to the second node; the twenty-third transistor and the twenty-fourth transistor are coupled in series between the power supply end and the ground end, and a coupling point of the twenty-third transistor and the twenty-fourth transistor is a second output end; control ends of the twenty-third transistor and the twenty-fourth transistor are both coupled to the second node. In the above technical solution, an operator circuit is provided, which has a small number of transistors, occupies a small area, and is simple to implement, so that when the operator circuit is applied to an accumulator, the area of the accumulator can be reduced.

[0019] In a possible implementation manner of the third aspect, the first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the twenty-third transistor are PMOS transistors; the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-fourth transistor are NMOS transistors. In the possible implementation manner, the flip rate of the transistors in the operator circuit provided in the foregoing manner is small when the data is compressed, so that the power consumption of the accumulator can be reduced when the operator circuit is applied to the accumulator.

[0020] In a fourth aspect, an operator circuit is provided, which, when applied to an accumulator, can serve as an adder in a compressor layer of the accumulator, and the adder is a subtract-carry adder, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor; wherein the first transistor and the second transistor are coupled in parallel between a power supply end and a first node; the third transistor is coupled between the first node and a first output end; the fourth transistor is coupled between the first output end and a second node; the fifth transistor and the sixth transistor are coupled in parallel between the second node and a ground end; the seventh transistor is coupled between the power supply end and a third node; the eighth transistor is coupled between the third node and the first output end; the ninth transistor is coupled between the first output end and a fourth node; the tenth transistor and the eleventh transistor are coupled in series between the third node and a fifth node; the twelfth transistor and the thirteenth transistor are coupled in series between the fourth node and the fifth node; the fourteenth transistor is coupled between the fourth node and the ground end; the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are coupled in parallel between the power supply end and a sixth node; the eighteenth transistor is coupled between the fifth node and the sixth node; the nineteenth transistor is coupled between the fifth node and a seventh node; the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are coupled in parallel between the seventh node and the ground end; control terminals of the third transistor, the fourth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, and the twentieth transistor are all used to receive a first input; control terminals of the first transistor, the fifth transistor, the seventh transistor, the fourteenth transistor, the sixteenth transistor, and the twenty-first transistor are all used to receive a second input; control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the seventeenth transistor, and the twenty-second transistor are all used to receive a third input; control terminals of the eighteenth transistor and the nineteenth transistor are both coupled to the first output end; the twenty-third transistor and the twenty-fourth transistor are coupled in series between the power supply end and the ground end, and a coupling point of the twenty-third transistor and the twenty-fourth transistor is a second output end; control terminals of the twenty-third transistor and the twenty-fourth transistor are both coupled to the fifth node. In the above technical solution, an operator circuit is provided, which has a small number of transistors, occupies a small area, and is simple to implement, so that when the operator circuit is applied to an accumulator, the area of the accumulator can be reduced.

[0021] In a possible implementation form of the fourth aspect, the first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the twenty-third transistor are PMOS transistors; the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-fourth transistor are NMOS transistors. In the above possible implementation form, the flip rate of the transistors in the operator circuit is small when the operator circuit compresses data, so that the power consumption of the accumulator can be reduced when the operator circuit is applied to the accumulator.

[0022] In a fifth aspect, a processor is provided, including the accumulator provided in the first aspect or any possible implementation form of the first aspect, the multiplier provided in the second aspect, or the operator circuit provided in the third aspect to the fourth aspect or any possible implementation form of the third aspect to the fourth aspect.

[0023] In a sixth aspect, a chip is provided, including the accumulator provided in the first aspect or any possible implementation form of the first aspect, the multiplier provided in the second aspect, or the operator circuit provided in the third aspect to the fourth aspect or any possible implementation form of the third aspect to the fourth aspect.

[0024] It can be understood that any of the accumulator, the processor or the chip provided above includes the accumulator or the operator circuit provided above, and therefore, the beneficial effects achieved by the accumulator or the operator circuit provided above can be referred to, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A schematic diagram of accumulating a plurality of binary numbers provided by an embodiment of the present application;

[0026] Figure 2 A schematic diagram of accumulating a plurality of binary numbers provided by an embodiment of the present application;

[0027] Figure 3 A schematic diagram of accumulating a plurality of binary numbers provided by an embodiment of the present application;

[0028] Figure 4 A schematic diagram of accumulating a plurality of binary numbers provided by an embodiment of the present application;

[0029] Figure 5A structure diagram of an accumulator provided for an embodiment of the present application;

[0030] Figure 6 A structure diagram of an accumulator provided for an embodiment of the present application;

[0031] Figure 7 A structure diagram of an accumulator provided for an embodiment of the present application;

[0032] Figure 8 A structure diagram of an accumulator provided for an embodiment of the present application;

[0033] Figure 9 A structure diagram of an accumulator provided for an embodiment of the present application;

[0034] Figure 10 A structure diagram of an accumulator provided for an embodiment of the present application;

[0035] Figure 11 A structure diagram of an accumulator provided for an embodiment of the present application;

[0036] Figure 12 A structure diagram of an accumulator provided for an embodiment of the present application;

[0037] Figure 13 A structure diagram of an accumulator provided for an embodiment of the present application;

[0038] Figure 14 A structure diagram of an accumulator provided for an embodiment of the present application;

[0039] Figure 15 A structure diagram of an accumulator provided for an embodiment of the present application;

[0040] Figure 16 A structure diagram of an accumulator provided for an embodiment of the present application;

[0041] Figure 17 A structure diagram of an accumulator provided for an embodiment of the present application;

[0042] Figure 18 A structure diagram of an accumulator provided for an embodiment of the present application; DETAILED DESCRIPTION

[0043] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or roles. Those skilled in the art will understand that "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0044] Before introducing the embodiments of this application, the relevant technologies of accumulators based on Wallace trees in the prior art will be described first. Current accumulators based on Wallace trees typically include multiple compressor layers. When using this accumulator to accumulate multiple binary numbers, each bit in the input and output arrays of each compressor layer needs to be in positive phase. Simultaneously, for multiple positive bits in the same compressor layer, multiple standard adders are used for parallel compression. Every three bits are compressed by a standard adder, outputting a positive carry-out bit and a positive sum-out bit.

[0045] For example, such as Figure 3 As shown, when using this accumulator to perform an accumulation calculation on 27 six-bit binary numbers, the accumulator can include multiple compressor layers. Each standard adder in each compressor layer is used to perform an accumulation calculation on the three positive bits. Figure 3 The positive carry output bit is represented as C, and the positive summation output bit is represented as S. Figure 3 Only the first to third compressor layers are shown in the diagram, with B0 to B5 representing different digits (i.e., 2). 0 Up to 2 5 The digit can also be called the weight digit. It refers to the bit at different positions in binary, similar to the ones, tens, and hundreds digits in decimal.

[0046] The accumulator described above adopts a large number of standard adders, and the standard adder requires the input bit and the output bit to be in the same phase when performing multi-bit compression, so that the standard adder needs to include a functional circuit for performing phase unification. At present, the phase unification of the bit is usually implemented by using a larger number of metal-oxide-semiconductor (MOS) tubes, which causes the standard adder to have the problems of a large number of MOS tubes and a large number of MOS tube flips in the average unit bit calculation. The standard adder in the accumulator described above is basically a standard full adder. Taking the standard full adder as an example, each standard full adder includes as many as 28 MOS tubes, and occupies an area of 0.2736um 2 Thus, the area of the accumulator is large. In addition, the large number of MOS tubes in the standard full adder causes a large number of MOS tube flips in the average unit bit calculation, so that the power consumption of the accumulator is large. Therefore, the accumulator implemented based on the Wallace tree currently has the problems of a large area and high power consumption. Based on this, the embodiment of the present application provides an accumulator, which reduces the power consumption and area of the accumulator by compressing the bit positions of different phases in the same compressor layer respectively. The accumulator can be used in a communication device, and the specific description of the communication device and the accumulator can be referred to below.

[0047] In the accumulation calculation process provided by the embodiment of the present application, the phase of the bit (which can also be referred to as the signal corresponding to the bit) has two phase states of positive phase and negative phase, and the two phase states are relative, for example, the positive phase of a bit is G, and the negative phase of the bit is / G, that is, the negative signal is the logical negation of the positive signal.

[0048] Figure 4 The structure of a communication device provided by the embodiment of the present application is shown in the figure. The communication device can be a terminal or a server, or a chip, a chipset, a circuit board or a module built in the terminal or the server. Referring to Figure 3The communication device can include a memory 101, a processor 102, a communication interface 103, and a bus 104. The memory 101, the processor 102, and the communication interface 103 are connected to each other through the bus 104. The memory 101 can be used to store data, software programs, and modules, mainly including a program storage area and a data storage area, the program storage area can store an operating system, at least one application required by a function, etc., and the data storage area can store data created during use of the device, etc. The processor 102 is used to control and manage the actions of the communication device, such as by running or executing software programs and / or modules stored in the memory 101, and calling data stored in the memory 101, to perform various functions of the device and process data. The communication interface 103 is used to support communication of the communication device.

[0049] The processor 102 includes but is not limited to a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), or a digital signal processor (DSP), or a general-purpose processor, etc. In the embodiments of the present application, the processor 102 includes one or more accumulators, or includes one or more multipliers, for example, the processor 102 includes a multiplier array, which is a device for implementing multiplication operations in the processor 102.

[0050] The bus 104 can be a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0051] To further describe the technical solutions, Figure 5 A structure diagram of an accumulator is provided in the embodiments of the present application, which can be used to implement accumulation of a plurality of binary numbers. Referring to Figure 5 The accumulator includes: W compressor layers, used to compress a plurality of binary numbers to obtain a plurality of accumulation values, a sum of the plurality of accumulation values is an accumulation sum of the plurality of binary numbers, and W is an integer greater than or equal to 1.

[0052] The W compressor layers can obtain a plurality of rows (each row including one or more bit positions) after compressing the plurality of binary numbers, and each row represents an accumulated value, i.e., the plurality of rows represent the plurality of accumulated values. The plurality of accumulated values can be two accumulated values or more than two accumulated values, and embodiments of the present application do not make specific limitations thereto.

[0053] In addition, the W compressor layers can include one compressor layer or a plurality of compressor layers, for example, the W can be equal to 1, 4, or 6, and the specific value can be set by persons skilled in the art according to experience or actual needs, and embodiments of the present application do not make specific limitations thereto. Figure 5 For example, the W compressor layers include a plurality of compressor layers, and the plurality of compressor layers are denoted as L1 to LW.

[0054] In the present application, the W compressor layers include at least one first compressor layer, and each first compressor layer in the at least one first compressor layer is used to compress an input array to obtain an output array. The input array includes a first array and a second array, the first array includes a plurality of positive bit positions, the second array includes a plurality of inverted bit positions, and the output array includes a first compressed array and a second compressed array. Each first compressor layer includes: a first compression circuit 21, configured to compress the first array in the input array of the first compressor layer to obtain the first compressed array; and a second compression circuit 22, configured to compress the second array in the input array of the first compressor layer to obtain the second compressed array.

[0055] Each of the W compressor layers has an input array and an output array. The input array of the first compressor layer (i.e., L1) in the W compressor layers can be a matrix obtained by arranging the plurality of binary numbers in descending order of digits. The input matrix of each of the second to Wth compressor layers (i.e., L2 to LW) in the W compressor layers can be the output matrix of the previous compressor layer of the compressor layer or the matrix obtained by other transformations or preprocessing of the output matrix, i.e., the input matrix of the i-th compressor layer is the output matrix of the (i-1)-th compressor layer or the matrix obtained by other transformations or preprocessing of the output matrix, and the value of i is 2 to W in turn.

[0056] In addition, the at least one first compressor layer can include one or more first compressor layers, and the number of layers of the one or more first compressor layers can be denoted as N, N is a positive integer and less than or equal to W. When N is less than W, the at least one first compressor layer can be any one or more compressor layers in the W compressor layers. Figure 5For example, the at least one first compressor layer includes (W-1) first compressor layers, and the (W-1) first compressor layers are the second to Wth compressor layers (i.e., L2 to LW) in the W compressor layers. It should be noted that when N is less than W, the compressor layers other than the at least one first compressor layer in the W compressor layers can be implemented by using the prior art, and the embodiments of the present application do not make a specific limitation thereon.

[0057] In the embodiments of the present application, in the input array of each first compressor layer, the first array includes a plurality of bits in positive phase, and the second array includes a plurality of bits in negative phase, so that the first array can be considered as a Wallace tree including a plurality of bits in positive phase, and the second array can be considered as a Wallace tree including a plurality of bits in negative phase. That is, the input array of each first compressor layer includes two Wallace trees, and the bits included in the two Wallace trees are in opposite phases. For the first array and the second array included in the input array of each first compressor layer, the first compression circuit 21 is configured to compress the first array, and the second compression circuit 22 is configured to compress the second array, so that the bits in different phases in the input array can be compressed by different compression circuits, thereby eliminating the need to unify the bits in the input array of each first compressor layer to the same phase, so that the accumulator is simple in design compared with the conventional design, and the area and power consumption can be reduced.

[0058] Further, each compressor layer in the W compressor layers can include one or more compressors, and each compressor can be configured to compress three bits in the same digit in the input array of the compressor layer. For the first compression circuit 21 in each first compressor layer, the first compression circuit 21 can include one or more first compressors 211, and each first compressor 211 in the one or more first compressors 211 is configured to compress three bits in the same digit in the first array. For the second compression circuit 22 in each first compressor layer, the second compression circuit 22 can include one or more second compressors 221, and each second compressor 221 in the one or more second compressors 221 is configured to compress three bits in the same digit in the second array.

[0059] The first compressor 211 and the second compressor 221 described above can be any one of the following three adders, including a negative-sum adder, a negative-carry adder, and a double-negative adder, which will be introduced and described below.

[0060] The first kind, the negative-sum adder, is configured to compress three bits to obtain a sum output bit and a carry output bit, the phase of the sum output bit is opposite to the phase of the three bits, and the phase of the carry output bit is the same as the phase of the three bits.

[0061] As shown in FIG. 1, the first compressor 211 is configured to compress three bits IN0, IN1 and IN2 to output a carry bit C and a sum bit / S. The carry bit C has the same phase as the three bits IN0, IN1 and IN2, and the sum bit / S has the opposite phase as the three bits IN0, IN1 and IN2. Figure 6 As shown in FIG. 1, the first compressor 211 is configured to compress three bits IN0, IN1 and IN2 to output a carry bit C and a sum bit / S. The carry bit C has the same phase as the three bits IN0, IN1 and IN2, and the sum bit / S has the opposite phase as the three bits IN0, IN1 and IN2.

[0062] / S = NOT (IN0 XOR IN1 XOR IN2) (1-1)

[0063] C = (IN0 AND IN1) OR (IN1 AND IN2) OR (IN0 AND IN2) (1-2)

[0064] When the three bits have different values (e.g., 0 or 1), the first compressor 211 is configured to perform the following compression: if the three bits are all 0, the carry output bit is 0 and the sum output bit is 1; if the three bits are all 1, the carry output bit is 1 and the sum output bit is 0; if one of the three bits is 1 and the other two bits are 0, the carry output bit is 0 and the sum output bit is 0; if two of the three bits are 1 and the other bit is 0, the carry output bit is 1 and the sum output bit is 1. That is, the first compressor 211 can perform the compression according to the logic table shown in Table 1.

[0065] Table 1

[0066] IN0 IN1 IN2 C / S 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0

[0067] 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0

[0068] When the first compressor 211 is the inverting full adder, the first compressor 211 is configured to compress three bits in a non-inverted manner to output a carry bit in a non-inverted manner and a sum bit in an inverted manner. When the second compressor 221 is the inverting full adder, the second compressor 221 is configured to compress three bits in an inverted manner to output a carry bit in an inverted manner and a sum bit in a non-inverted manner.

[0069] In one possible embodiment, it is assumed that each of the W compressor layers includes a plurality of sign-reversed sum adders, and the input array of the first compressor layer (i.e., LI) includes only a plurality of positive bits, and the input array of each of the second to Wth compressor layers (i.e., L2 to LW) includes a plurality of positive bits (i.e., a first array) and a plurality of negative bits (i.e., a second array). The above description can also be understood as: the first compressor layer (i.e., LI) includes only one first compression circuit 21 including a plurality of first compressors 211; each of the second to Wth compressor layers (i.e., L2 to LW) includes one first compression circuit 21 including a plurality of first compressors 211 and one second compression circuit 22 including a plurality of second compressors 221.

[0070] As shown in FIG. 2, for example, when the accumulator is used to perform an accumulation calculation on a 27-bit binary number, the first compressor layer (i.e., LI) includes 54 first compressors 211, each of which is configured to compress three positive bits in the same bit position to output one positive carry output bit C and one negative sum output bit / S. Figure 7 As shown in FIG. 2, for example, when the accumulator is used to perform an accumulation calculation on a 27-bit binary number, the first compressor layer (i.e., LI) includes 54 first compressors 211, each of which is configured to compress three positive bits in the same bit position to output one positive carry output bit C and one negative sum output bit / S.

[0071] As shown in FIG. 2, for example, when the accumulator is used to perform an accumulation calculation on a 27-bit binary number, the first compressor layer (i.e., LI) includes 54 first compressors 211, each of which is configured to compress three positive bits in the same bit position to output one positive carry output bit C and one negative sum output bit / S.

[0072] The first compression circuit 21 in the third compressor layer (i.e. L3) includes 12 first compressors 211, and the second compression circuit 22 includes 12 second compressors 221. Each of the 12 first compressors 211 is configured to compress three positive-phase bit positions in the same digit in the first matrix to output a positive-phase carry output bit C and a negative-phase sum output bit / S. Each of the 12 second compressors 221 is configured to compress three negative-phase bit positions in the same digit in the second matrix to output a negative-phase carry output bit / C and a positive-phase sum output bit S. The input matrix of the fourth compressor layer (i.e. L4) includes the output bits output by the 12 first compressors 211 and the 12 second compressors 221. Among them, the first matrix in the input matrix includes the positive-phase carry output bits C output by the 12 first compressors 211 and the positive-phase sum output bits S output by the 12 second compressors 221, and the second matrix includes the negative-phase sum output bits / S output by the 12 first compressors 211 and the negative-phase carry output bits / C output by the 12 second compressors 221.

[0073] The first compression circuit 21 in the fourth compressor layer (i.e. L4) includes 6 first compressors 211, and the second compression circuit 22 includes 6 second compressors 221. Each of the 6 first compressors 211 is configured to compress three positive-phase bit positions in the same digit in the first matrix to output a positive-phase carry output bit C and a negative-phase sum output bit / S. Each of the 6 second compressors 221 is configured to compress three negative-phase bit positions in the same digit in the second matrix to output a negative-phase carry output bit / C and a positive-phase sum output bit S. The output matrix of the fourth compressor layer (i.e. L4) includes the positive-phase carry output bits C and the negative-phase sum output bits / S output by the 6 first compressors 211, the negative-phase carry output bits / C and the positive-phase sum output bits S output by the 6 second compressors 221, and the positive-phase bit positions in the first array that are not compressed and the negative-phase bit positions in the second array that are not compressed.

[0074] It should be noted that, Figure 7 It should be noted that,

[0075] The second type is an inverting carry adder, which is used to compress three bits to obtain a sum output bit and a carry output bit. The phase of the sum output bit is the same as the phase of the three bits, and the phase of the carry output bit is opposite to the phase of the three bits.

[0076] For example, such as Figure 8 As shown, assuming the three input bits of this inverting carry adder are IN0, IN1, and IN2, after compressing these three bits, the adder outputs a carry bit / C and a sum bit S. / C is out of phase with IN0, IN1, and IN2, while S is in phase with IN0, IN1, and IN2. In one example, this inverting carry adder can satisfy the logic functions shown in formulas (2-1) and (2-2), where NOT represents the inversion operation, XOR represents the NOR operation, AND represents the AND operation, and OR represents the OR operation.

[0077] S = IN0 XOR IN1 XOR IN2 (2-1)

[0078] / C=NOT((IN0 AND IN1)OR(IN1 AND IN2)OR(IN0 AND IN2))(2-2)

[0079] When the three bits are different values ​​(e.g., 0 or 1), the inverting carry adder performs the following compression: if all three bits are 0, the carry output bit is 1 and the sum output bit is 0; if all three bits are 1, the carry output bit is 0 and the sum output bit is 1; if one bit is 1 and the other two bits are 0, the carry output bit is 1 and the sum output bit is 1; if two bits are 1 and the other bit is 0, the carry output bit is 0 and the sum output bit is 0. In other words, the inverting carry adder can be compressed according to the logic table shown in Table 2 below.

[0080] Table 2

[0081] IN0 IN1 IN2 / C S 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1

[0082] 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1

[0083] When the first compressor 211 is the inverting carry adder, it is used to compress the three positive bits to obtain an inverted carry output bit and a positive sum output bit. When the second compressor 221 is the inverting carry adder, it is used to compress the three inverted bits to obtain a positive carry output bit and an inverted sum output bit.

[0084] In one possible embodiment, it is assumed that each of the W compressor layers includes multiple inverted carry adders, and the input array of the first compressor layer (i.e., L1) includes only multiple positive-phase bits, while the input arrays of the second to Wth compressors (i.e., L2 to LW) each include multiple positive-phase bits (i.e., a first array) and multiple inverted bits (i.e., a second array). This description can be understood as follows: the first compressor layer (i.e., L1) includes only one first compression circuit 21, which includes multiple first compressors 211; each of the second to Wth compressor layers (i.e., L2 to LW) includes one first compression circuit 21 and one second compression circuit 22, where the first compression circuit 21 includes multiple first compressors 211 and the second compression circuit 22 includes multiple second compressors 221.

[0085] For example, such as Figure 9 As shown, when the accumulator is used to perform an accumulation calculation on 27 6-bit binary numbers, the first compressor layer (L1) includes 54 first compressors 211. Each first compressor 211 is used to compress three positive-phase bits on the same bit position to output an inverted carry output bit / C and a positive-phase sum output bit S. The input matrix of the second compressor layer (L2) includes the output bits of the 54 first compressors 211. Specifically, the first matrix in the input matrix includes the inverted carry output bit / C of the 54 first compressors 211, and the second matrix includes the positive-phase sum output bit S of the 54 first compressors 211.

[0086] The first compression circuit 21 in the second compressor layer (L2) includes 18 first compressors 211, and the second compression circuit 22 includes 18 second compressors 221. Each of the 18 first compressors 211 compresses three positive-phase bits at the same position in the first matrix to output an inverted carry output bit / C and a positive sum output bit S. Each of the 18 second compressors 221 compresses three inverted bits at the same position in the second matrix to output a positive carry output bit C and an inverted sum output bit / S. The input matrix of the third compressor layer (L3) includes the output bits from the 18 first compressors 211 and the 18 second compressors 221. The first matrix in the input matrix includes 18 positive-phase summation output bits S from the first compressor 211 and 18 positive-phase carry output bits C from the second compressor 221, and the second matrix includes 18 negative-phase carry output bits / C from the first compressor 211 and 18 negative-phase summation output bits / S from the second compressor 221.

[0087] The first compression circuit 21 in the third compressor layer (i.e. L3) includes 12 first compressors 211, and the second compression circuit 22 includes 12 second compressors 221. Each of the 12 first compressors 211 is configured to compress three positive-phase bit positions in the same digit in the first matrix to output one negative-phase carry output bit / C and one positive-phase sum output bit S. Each of the 12 second compressors 221 is configured to compress three negative-phase bit positions in the same digit in the second matrix to output one positive-phase carry output bit C and one negative-phase sum output bit / S. The input matrix of the fourth compressor layer (i.e. L4) includes the output bits output by the 12 first compressors 211 and the 12 second compressors 221. Among them, the first matrix in the input matrix includes the positive-phase sum output bits S output by the 12 first compressors 211 and the positive-phase carry output bits C output by the 12 second compressors 221, and the second matrix includes the negative-phase carry output bits / C output by the 12 first compressors 211 and the negative-phase sum output bits / S output by the 12 second compressors 221.

[0088] The first compression circuit 21 in the fourth compressor layer (i.e. L4) includes 6 first compressors 211, and the second compression circuit 22 includes 6 second compressors 221. Each of the 6 first compressors 211 is configured to compress three positive-phase bit positions in the same digit in the first matrix to output one negative-phase carry output bit / C and one positive-phase sum output bit S. Each of the 6 second compressors 221 is configured to compress three negative-phase bit positions in the same digit in the second matrix to output one positive-phase carry output bit C and one negative-phase sum output bit / S. The output matrix of the fourth compressor layer (i.e. L4) includes the negative-phase carry output bits / C and the positive-phase sum output bits S output by the 6 first compressors 211, the negative-phase sum output bits / S and the positive-phase carry output bits C output by the 6 second compressors 221, and the positive-phase bit positions in the first array and the negative-phase bit positions in the second array that are not compressed.

[0089] It should be noted that, Figure 9 It should be noted that,

[0090] Furthermore, the examples of the first and second types described above illustrate that the input matrix of the first compressor layer (i.e., L1) only includes a number of positive-phase bits, and do not constitute a limitation on the embodiments of this application. In practical applications, the input matrix of the first compressor layer (i.e., L1) may also include only a number of negative-phase bits, or may include both positive-phase bits and negative-phase bits.

[0091] The third type is a double inverting adder, which is used to compress three bits to obtain a sum output bit and a carry output bit. The phase of the sum output bit and the phase of the carry output bit are opposite to the phase of the three bits.

[0092] For example, such as Figure 10 As shown, assuming the three input bits of this dual inverting adder are IN0, IN1, and IN2, after compressing these three bits, the dual inverting adder outputs a carry bit / C and a sum bit / S. The phases of / C and / S are opposite to the phases of IN0, IN1, and IN2. In one example, this dual inverting adder can satisfy the logic functions shown in formulas (3-1) and (3-2), where NOT represents the inversion operation, XOR represents the NOR operation, AND represents the AND operation, and OR represents the OR operation.

[0093] S=NOT(IN0 XOR IN1 XOR IN2)(3-1)

[0094] / C=NOT((IN0 AND IN1)OR(IN1 AND IN2)OR(IN0 AND IN2))(3-2)

[0095] When the three bits are different values ​​(e.g., 0 or 1), the double-inverting adder performs the following compression: if all three bits are 0, the carry-out bit is 1 and the sum-out bit is 1; if all three bits are 1, the carry-out bit is 0 and the sum-out bit is 0; if one bit is 1 and the other two bits are 0, the carry-out bit is 1 and the sum-out bit is 0; if two bits are 1 and the other bit is 0, the carry-out bit is 0 and the sum-out bit is 1. In other words, the double-inverting adder can be compressed according to the logic table shown in Table 3 below.

[0096] Table 3

[0097] IN0 IN1 IN2 / C S 0 0 0 1 1 1 1 1 0 0

[0098] 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 1 0 0 1

[0099] When the first compressor 211 is the dual-inverting adder, it is used to compress the three positive bits to obtain an inverted carry output bit and an inverted sum output bit. When the second compressor 221 is the dual-inverting adder, it is used to compress the three inverted bits to obtain a positive carry output bit and a positive sum output bit.

[0100] In one possible embodiment, it is assumed that each of the W compressor layers includes multiple double-inverting adders, and the input arrays of the first to the Wth compressors (i.e., L1 to LW) each include a first array and a second array. The above description can be understood as follows: each of the first to the Wth compressor layers (i.e., L1 to LW) includes a first compression circuit 21 and a second compression circuit 22, wherein the first compression circuit 21 includes multiple first compressors 211, and the second compression circuit 22 includes multiple second compressors 221.

[0101] For example, such as Figure 11 As shown, when the accumulator is used to perform an accumulation calculation on 18 6-bit binary numbers, if the first 9 binary numbers are positive bits (i.e., the first matrix) and the last 9 binary numbers are negative bits (i.e., the second matrix), then the first compression circuit 21 in the first compressor layer (i.e., L1) includes 18 first compressors 211, and the second compression circuit 22 includes 18 second compressors 221. Each of the 18 first compressors 211 is used to compress three positive bits at the same position in the first matrix to output a negative carry output bit / C and a negative sum output bit / S. Each of the 18 second compressors 221 is used to compress three negative bits at the same position in the second matrix to output a positive carry output bit C and a positive sum output bit S. The first matrix in the input matrix of the second compressor layer (i.e., L2) includes the positive carry output bits C and positive summation output bits S of the 18 outputs of the second compressor 221, and the second matrix includes the negative carry output bits / C and negative summation output bits / S of the 18 outputs of the first compressor 211.

[0102] The first compression circuit 21 in the second compressor layer (i.e., L2) includes 12 first compressors 211, and the second compression circuit 22 includes 12 second compressors 221. Each of the 12 first compressors 211 is configured to compress three positive-phase bit positions in the same digit in the first matrix to output one negative-phase carry output bit / C and one negative-phase sum output bit / S. Each of the 12 second compressors 221 is configured to compress three negative-phase bit positions in the same digit in the second matrix to output one positive-phase carry output bit C and one positive-phase sum output bit S. The output matrix of the second compressor layer (i.e., L2) includes the negative-phase sum output bits / S and the negative-phase carry output bits / C output by the 12 first compressors 211, and the positive-phase sum output bits S and the positive-phase carry output bits C output by the 12 second compressors 221.

[0103] It should be noted that, Figure 11 Only the first and second compressor layers (i.e., L1 and L2) in the accumulator are shown in FIG. 2, and the compression manner of the other compressor layers after the second compressor layer can be similar to that of the first and second compressor layers, or the bit positions of different phases in the output matrix of the second compressor layer can be converted into bit positions of the same phase through an inversion operation, and then compressed through the existing compression manner. Therefore, the details are not described herein.

[0104] Optionally, when the at least one first compressor layer in the W compressor layers includes a plurality of first compressor layers, the compression manner of the first compressor layers at different levels in the plurality of first compressor layers can be the same or different. For example, the plurality of first compressor layers includes at least two first compressor layers, and each first compressor and each second compressor in the at least two first compressor layers can adopt one of the three adders. Alternatively, each first compressor and each second compressor in a part of the at least two first compressor layers can adopt one of the three adders, and each first compressor and each second compressor in another part of the at least two first compressor layers can adopt one or two of the other two adders.

[0105] Furthermore, the accumulator may further include a summing circuit 23, used to receive the plurality of accumulated values ​​and sum the plurality of accumulated values ​​to obtain the accumulated sum. Specifically, after the plurality of binary numbers are compressed by the W compressor layers to obtain the plurality of accumulated values, the Wth compressor layer (i.e., LW) of the W compressor layers can send the plurality of accumulated values ​​to the summing circuit 23. When the summing circuit 23 receives the plurality of accumulated values, it sums the plurality of accumulated values ​​to obtain the accumulated sum of the plurality of binary numbers. Optionally, the plurality of accumulated values ​​are two accumulated values. In this case, the summing circuit 23 is an adder, which sums the two accumulated values ​​to obtain the accumulated sum of the plurality of binary numbers.

[0106] Furthermore, the accumulator may also include one or more inverters for inverting at least one of the summation output bit and carry output bit output by one or more first compressors or second compressors in the W compressor layers, or for inverting three bits input to the one or more first compressors or second compressors. In one possible embodiment, the one or more inverters are used to invert at least one of the summation output bit and carry output bit output by one or more first compressors or second compressors in the W compressor layers.

[0107] For example, such as Figure 12 As shown, taking the i-th compressor layer (i.e., 1≤i≤W) out of the W compressor layers as an example, assume that the input matrix of the i-th compressor layer consists of 3 rows and 6 columns of positive bit values. The i-th compressor layer includes 6 first compressors, and all 6 first compressors are inverting summators. These 6 first compressors are used to compress the input matrix to output two rows. The first row includes 6 inverted summator output bits / S, and the second row includes 6 positive carry output bits C. At this time, the one or more inverters can include 6 inverters, which can be used to invert the 6 inverted summator output bits / S of the first row to obtain 6 positive summator output bits S. After inversion, the two rows output by the i-th compressor layer are converted into two positive rows.

[0108] In another possible embodiment, the one or more inverters are used to invert three bits of one or more first or second compressors input to the W compressor layers. For example, as shown... Figure 13As shown, taking the i-th compressor layer (i.e. 1≤i≤W) in the W compressor layers as an example, it is assumed that the input matrix of the i-th compressor layer includes 6 rows and 3 columns of bit positions, the 1st to 3rd rows are positive-phase bit positions, the 4th to 6th rows are negative-phase bit positions, the i-th compressor layer includes 6 first compressors, and the 6 first compressors are all negative-phase sum adders. At this time, the one or more inverters can include 9 inverters, which can be used to invert the 9 bit positions in the 4th to 6th rows in the negative phase respectively to obtain 9 positive-phase bit positions (i.e. convert the bit positions in the 4th to 6th rows to the positive phase), that is, the 9 inverters can be used to invert the bit positions of the 3 first compressors in the input second row. After inversion, the 6 first compressors in the 1st compressor layer can be used to compress the three positive-phase bit positions on the same data respectively to output four rows, which include two rows of negative-phase sum output bits S and two rows of positive-phase carry output bits C.

[0109] It should be noted that the input matrix of the i-th compressor layer and the first compressors included as shown above are only exemplary and do not constitute a limitation on the embodiments of the present application. Figure 12 and Figure 13 The input matrix of the i-th compressor layer and the first compressors included as shown above are only exemplary and do not constitute a limitation on the embodiments of the present application. In the embodiments of the present application, by inverting at least one of the sum output bits and the carry output bits output by the one or more first compressors or second compressors or inverting the three bit positions input to the one or more first compressors or second compressors through the one or more inverters, the compression efficiency of the W compressor layers can be improved while ensuring the accuracy of the compression result, thereby improving the calculation efficiency of the accumulator.

[0110] Figure 14 A structural schematic diagram of a negative-phase sum compression operator circuit provided by an embodiment of the present application is shown. The negative-phase sum operator circuit can also be referred to as a negative-phase sum adder. The negative-phase sum adder includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24.

[0111] The first transistor M1 and the second transistor M2 are coupled in parallel between the power supply end and the first node ①; the third transistor M3 is coupled between the first node ① and the second node ②; the fourth transistor M4 is coupled between the second node ② and the third node ③; the fifth transistor M5 and the sixth transistor M6 are coupled in parallel between the third node ③ and the ground end; the seventh transistor M7 is coupled between the power supply end and the fourth node ④; the eighth transistor M8 is coupled between the second node ② and the fourth node ④; the ninth transistor M9 is coupled between the second node ② and the fifth node ⑤; the tenth transistor M10 and the eleventh transistor M11 are coupled in series between the fourth node ④ and the first output end / C; the twelfth transistor M12 and the thirteenth transistor M13 are coupled in series between the fifth node ⑤ and the first output end / C; the fourteenth transistor M14 is coupled between the fifth node ⑤ and the ground end; the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 are coupled in parallel between the power supply end and the sixth node ⑥; the eighteenth transistor M18 is coupled between the first output end / C and the sixth node ⑥; the nineteenth transistor M19 is coupled between the first output end / C and the seventh node ⑦; the twentieth transistor M20, the twenty-first transistor M21 and the twenty-second transistor M22 are coupled in parallel between the seventh node ⑦ and the ground end.

[0112] The control end of the third transistor M3, the fourth transistor M4, the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15 and the twentieth transistor M20 is used for receiving the first input IN0; the control end of the first transistor M1, the fifth transistor M5, the seventh transistor M7, the fourteenth transistor M14, the sixteenth transistor M16 and the twenty-first transistor M21 is used for receiving the second input IN2; the control end of the second transistor M2, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, the seventeenth transistor M17 and the twenty-second transistor M22 is used for receiving the third input IN3.

[0113] The control end of the eighteenth transistor M18 and the nineteenth transistor M19 is coupled to the second node ②; the twenty-third transistor M23 and the twenty-fourth transistor M24 are coupled in series between the power supply end and the ground end, and the coupling point of the twenty-third transistor M23 and the twenty-fourth transistor M24 is the second output end S; the control end of the twenty-third transistor M23 and the twenty-fourth transistor M24 is coupled to the second node ②.

[0114] In the embodiment of the present application, the first input IN0, the second input IN2 and the third input IN3 can be the three bits in the above-mentioned related description of the inverting summing adder in the accumulator embodiment, the first output terminal / S can be used to output the sum output bit of the inverting summing adder, and the second output terminal C can be used to output the carry output bit of the inverting summing adder.

[0115] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18 and the twenty-third transistor M23 are PMOS transistors; the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22 and the twenty-fourth transistor M24 are NMOS transistors. Correspondingly, the above-mentioned control terminal can be specifically a gate of the corresponding PMOS transistor or NMOS transistor.

[0116] It should be noted that the first transistor M1 to the twenty-fourth transistor M24 in the above-mentioned example can be MOS transistors, or can be replaced by bipolar transistors, Figure 14 the type of each transistor shown in the above-mentioned embodiment is only exemplary, and does not limit the embodiments of the present application. In addition, Figure 14 is only one circuit example, and any transistor added on the basis of the circuit, so that the roles of multiple transistors are equivalent to Figure 14 the role of one or more transistors in the above-mentioned circuit, is also regarded as the same kind of circuit.

[0117] Figure 15 A structure schematic diagram of an inverting carry compression operator circuit provided by the embodiment of the present application, which can also be called an inverting carry adder. The inverting carry adder comprises: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23 and a twenty-fourth transistor M24.

[0118] The first transistor M1 and the second transistor M2 are coupled in parallel between the power supply end and the first node ①; the third transistor M3 is coupled between the first node ① and the first output end / C; the fourth transistor M4 is coupled between the first output end / C and the second node ②; the fifth transistor M5 and the sixth transistor M6 are coupled in parallel between the second node ② and the ground end; the seventh transistor M7 is coupled between the power supply end and the third node ③; the eighth transistor M8 is coupled between the third node ③ and the first output end / C; the ninth transistor M9 is coupled between the first output end / C and the fourth node ④; the tenth transistor M10 and the eleventh transistor M11 are coupled in series between the third node ③ and the fifth node ⑤; the twelfth transistor M12 and the thirteenth transistor M13 are coupled in series between the fourth node ④ and the fifth node ⑤; the fourteenth transistor M14 is coupled between the fourth node ④ and the ground end; the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 are coupled in parallel between the power supply end and the sixth node ⑥; the eighteenth transistor M18 is coupled between the fifth node ⑤ and the sixth node ⑥; the nineteenth transistor M19 is coupled between the fifth node ⑤ and the seventh node ⑦; the twentieth transistor M20, the twenty-first transistor M21 and the twenty-second transistor M22 are coupled in parallel between the seventh node ⑦ and the ground end.

[0119] The control ends of the third transistor M3, the fourth transistor M4, the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15 and the twentieth transistor M20 are used for receiving the first input IN0; the control ends of the first transistor M1, the fifth transistor M5, the seventh transistor M7, the fourteenth transistor M14, the sixteenth transistor M16 and the twenty-first transistor M21 are used for receiving the second input IN2; the control ends of the second transistor M2, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, the seventeenth transistor M17 and the twenty-second transistor M22 are used for receiving the third input IN3.

[0120] The control ends of the eighteenth transistor M18 and the nineteenth transistor M19 are both coupled to the first output end / C; the twenty-third transistor M23 and the twenty-fourth transistor M24 are coupled in series between the power supply end and the ground end, and the coupling point of the twenty-third transistor M23 and the twenty-fourth transistor M24 is the second output end S; the control ends of the twenty-third transistor M23 and the twenty-fourth transistor M24 are both coupled to the fifth node ⑤.

[0121] In the embodiment of the present application, the first input IN0, the second input IN2 and the third input IN3 can be the three bits in the above-mentioned related description of the accumulator embodiment about the complementary carry-summation adder, the first output terminal / C can be used for outputting the summation output bit of the complementary carry-summation adder, and the second output terminal S can be used for outputting the carry output bit of the complementary carry-summation adder.

[0122] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18 and the twenty-third transistor M23 are PMOS transistors; the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22 and the twenty-fourth transistor M24 are NMOS transistors. Correspondingly, the above-mentioned control terminal can be specifically a gate of the corresponding PMOS transistor or NMOS transistor.

[0123] It should be noted that the first transistor M1 to the twenty-fourth transistor M24 in the above-mentioned example can be MOS transistors, or can be replaced by bipolar transistors, Figure 15 the type of each transistor shown in the above-mentioned example is only exemplary, and does not limit the embodiments of the present application. In addition, Figure 15 is only one circuit example, and any transistor added on the basis of the circuit, so that the roles of the multiple transistors are equivalent to Figure 15 the role of one or more transistors in the above-mentioned example, is also regarded as the same circuit.

[0124] Figure 16 A structure schematic diagram of a double-complementary compression operator circuit provided by the embodiment of the present application, the double-complementary compression operator circuit can also be called a double-complementary adder. The double-complementary adder comprises: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21 and a twenty-second transistor M22.

[0125] The first transistor M1 and the second transistor M2 are coupled in parallel between a power supply end and a first node ①; the third transistor M3 is coupled between the first node ① and a first output end / C; the fourth transistor M4 is coupled between the first output end / C and a second node ②; the fifth transistor M5 and the sixth transistor M6 are coupled in parallel between the second node ② and a ground end; the seventh transistor M7 is coupled between the power supply end and a third node ③; the eighth transistor M8 is coupled between the third node ③ and the first output end / C; the ninth transistor M9 is coupled between the first output end / C and a fourth node ④; the tenth transistor M10 is coupled between the fourth node ④ and the ground end; the eleventh transistor M11 and the twelfth transistor M12 are coupled in series between the third node ③ and a second output end / S; the thirteenth transistor M13 and the fourteenth transistor M14 are coupled in series between the second output end / S and the fourth node ④; the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 are coupled in parallel between the power supply end and a fifth node ⑤; the eighteenth transistor M18 is coupled between the fifth node ⑤ and the second output end / S; the nineteenth transistor M19 is coupled between the second output end / S and a sixth node ⑥; the twentieth transistor M20, the twenty-first transistor M21 and the twenty-second transistor M22 are coupled in parallel between the sixth node ⑥ and the ground end.

[0126] The control end of the third transistor M3, the fourth transistor M4, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15 and the twentieth transistor M20 is configured to receive a first input IN0; the control end of the first transistor M1, the fifth transistor M5, the seventh transistor M7, the tenth transistor M10, the sixteenth transistor M16 and the twenty-first transistor M21 is configured to receive a second input IN2; the control end of the second transistor M2, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the eleventh transistor M11, the fourteenth transistor M14, the seventeenth transistor M17 and the twenty-second transistor M22 is configured to receive a third input IN3. The control end of the eighteenth transistor M18 and the nineteenth transistor M19 is coupled to the first output end / C.

[0127] In the embodiment of the present application, the first input IN0, the second input IN2 and the third input IN3 described above can be the three bits in the description of the double-inversion adder in the accumulator embodiment, the first output end / C can be configured to output the sum output bit of the double-inversion adder, and the second output end / S can be configured to output the carry output bit of the double-inversion adder.

[0128] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are PMOS transistors; the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, the fourteenth transistor M14, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22 are NMOS transistors. Correspondingly, the control end mentioned above can refer to the gate of the corresponding PMOS transistor or NMOS transistor.

[0129] It should be noted that the first transistor M1 to the twenty-second transistor M22 exemplified above can be MOS transistors, or can be replaced by bipolar transistors, Figure 16 the types of the transistors shown in the above embodiments are only exemplary and do not limit the embodiments of the present application. In addition, Figure 16 is only one circuit example, and for any addition of transistors on the basis of this circuit, the roles of the multiple transistors are equivalent to Figure 16 the roles of one or more transistors in the above circuit, and it is also regarded as the same circuit.

[0130] Based on this, the embodiments of the present application also provide a multiplier, as shown in Figure 17 the multiplier can include: a plurality of groups of encoders 301 and an accumulator 302, the plurality of groups of encoders 301 can be used to encode a first value and a second value represented by binary numbers to obtain a plurality of partial product terms, and the accumulator 302 can be used to accumulate the plurality of partial product terms to obtain the product of the first value and the second value. Wherein, the accumulator 302 can be any one of the accumulators provided in the above embodiments, and the plurality of partial product terms can be used as the input array of the first compressor layer in the W compressor layers of the accumulator.

[0131] Optionally, the multiplier can further include a plurality of pre-encoders 303. The plurality of pre-encoders 303 can be used to pre-encode the first value to obtain a pre-encoding result; correspondingly, the plurality of groups of encoders 301 can be used to encode the pre-encoding result and the second value to obtain the plurality of partial product terms. For more specific description of the multiplier shown in Figure 17 , reference can be made to the international patent PCT / CN2019 / 119993.

[0132] The accumulator multiplier provided in the embodiments of the present application (hereinafter referred to as the inverse accumulation multiplier) is compared with the accumulator multiplier based on the standard adder (hereinafter referred to as the traditional accumulation multiplier) in the prior art, and the power consumption and area of the two are compared in the 7nm process as shown in the following table. Figure 18 As shown in the table, the embodiments of the present application are not limited to the specific parameter values. Figure 18 (a) of the table shows the power consumption of the corresponding accumulators when the inverse accumulation multiplier and the traditional accumulation multiplier are used to multiply two binary numbers of 8bits to 32bits. Figure 18 (b) of the table shows the area of the corresponding accumulators when the inverse accumulation multiplier and the traditional accumulation multiplier are used to multiply two binary numbers of 8bits to 32bits. Figure 18 It can be seen that the power consumption and area of the inverse accumulation multiplier are smaller than those of the traditional accumulation multiplier.

[0133] In the embodiments of the present application, the input array of each first compressor layer in the accumulator of the inverse accumulation multiplier includes a first array and a second array, the first array can be considered as a Wallace tree including a plurality of positive bit positions, and the second array can be considered as a Wallace tree including a plurality of negative bit positions. That is, the input array includes two Wallace trees including bit positions in opposite phases. For the first array and the second array, the first compression circuit 21 is used to compress the first array, and the second compression circuit 22 is used to compress the second array, so that the bit positions in different phases in the input array can be compressed by different compression circuits, so that the bit positions in the input array of each first compressor layer do not need to be unified to the same phase, so that the accumulator is simple in design, and the area and power consumption can be reduced. Therefore, the area and power consumption of the multiplier using the accumulator are also small.

[0134] In another embodiment of the present application, a processor is provided, including an accumulator, a multiplier or an operator circuit; wherein the accumulator is the accumulator provided above, the multiplier is the multiplier including the accumulator provided above, and the operator circuit includes any one or more of the operator circuits provided above.

[0135] In another embodiment of the present application, a chip is provided, including an accumulator, a multiplier or an operator circuit; wherein the accumulator is the accumulator provided above, the multiplier is the multiplier including the accumulator provided above, and the operator circuit includes any one or more of the operator circuits provided above.

[0136] In another embodiment of the present application, a communication device is also provided, which can be configured as shown in Figure 4 , i.e. the communication device can include a memory 101, a processor 102, a communication interface 103 and a bus 104. Among them, the processor 102 can include the accumulator provided above, or the multiplier including the accumulator provided above.

[0137] It should be noted that the above description of the accumulator and the operator circuit can be applied to the multiplier, the processor, the chip and the accumulator and the operator circuit included in the communication device shown in Figure 16 , and the embodiments of the present application will not be described here.

[0138] Finally, it should be noted that the above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An accumulator characterized in that, The W compressor layers, W being an integer greater than or equal to 1; The W compressor layers are configured to compress a plurality of binary numbers to obtain a plurality of accumulated values, and a sum of the plurality of accumulated values is an accumulated sum of the plurality of binary numbers. The W compressor layers include at least one first compressor layer, and each first compressor layer is configured to compress an input array to obtain an output array, the input array including a first array and a second array, the first array including a plurality of positive bits, the second array including a plurality of negative bits, and the output array including a first compressed array and a second compressed array. Each first compressor layer includes: a first compression circuit configured to compress the first array in a same digit by every three bits as a granularity to obtain the first compressed array; and a second compression circuit configured to compress the second array in the same digit by every three bits as the granularity to obtain the second compressed array.

2. The accumulator of claim 1, wherein, The first compression circuit includes one or more first compressors, and each first compressor is configured to compress three bits in a same digit of the first array. The second compression circuit includes one or more second compressors, and each second compressor is configured to compress three bits in the same digit of the second array.

3. The accumulator of claim 2, wherein, Each first compressor and each second compressor is a negative-sum adder. The negative-sum adder is configured to compress the three bits to obtain a carry output bit and a sum output bit, a phase of the carry output bit being the same as that of the three bits, and a phase of the sum output bit being opposite to that of the three bits.

4. The accumulator of claim 3, wherein, The negative-sum adder is configured to perform the following compression: if the three bits are all 0, the carry output bit is 0, and the sum output bit is 1; if the three bits are all 1, the carry output bit is 1, and the sum output bit is 0; if one bit of the three bits is 1, and the other two bits are 0, the carry output bit is 0, and the sum output bit is 0; and if two bits of the three bits are 1, and the other bit is 0, the carry output bit is 1, and the sum output bit is 1.

5. The accumulator of claim 2, wherein, Each first compressor and each second compressor is a negative-carry adder. The negative-carry adder is configured to compress the three bits to obtain a carry output bit and a sum output bit, a phase of the carry output bit being opposite to that of the three bits, and a phase of the sum output bit being the same as that of the three bits.

6. The accumulator of claim 5, wherein, The negative-carry adder is configured to perform the following compression: if the three bits are all 0, the carry output bit is 1, and the sum output bit is 0; if the three bits are all 1, the carry output bit is 0, and the sum output bit is 1; if one bit of the three bits is 1, and the other two bits are 0, the carry output bit is 1, and the sum output bit is 1; and if two bits of the three bits are 1, and the other bit is 0, the carry output bit is 0, and the sum output bit is 0. If two of the three bits are 1 and the other bit is 0, the carry-out bit is 0 and the sum-out bit is 0.

7. The accumulator of claim 2, wherein, Each of the first compressors and each of the second compressors is a double-inversion adder; The double-inversion adder is configured to compress the three bits to obtain a carry-out bit and a sum-out bit, wherein phases of the carry-out bit and the sum-out bit are opposite to a phase of the three bits.

8. The accumulator of claim 7, wherein, The double-inversion adder is configured to compress the three bits as follows: If all of the three bits are 0, the carry-out bit is 1 and the sum-out bit is 1; If all of the three bits are 1, the carry-out bit is 0 and the sum-out bit is 0; If one of the three bits is 1 and the other two bits are 0, the carry-out bit is 1 and the sum-out bit is 0; If two of the three bits are 1 and the other bit is 0, the carry-out bit is 0 and the sum-out bit is 1.

9. The accumulator according to any one of claims 1-8, characterized in that, The accumulator further comprises: a summing circuit configured to receive the plurality of accumulated values and sum the plurality of accumulated values to obtain the accumulated sum.

10. The accumulator of claim 3, wherein, The accumulator further comprises: one or more inverters configured to invert at least one of a sum-out bit and a carry-out bit output by one or more of the first compressors or the second compressors in the W layers of compressors, or to invert the three bits input to the one or more of the first compressors or the second compressors.

11. The accumulator of claim 2, wherein, The first compressor or the second compressor comprises an operator circuit, the operator circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor; wherein The first transistor and the second transistor are coupled in parallel between a power supply terminal and a first node; The third transistor is coupled between the first node and a second node; The fourth transistor is coupled between the second node and a third node; The fifth transistor and the sixth transistor are coupled in parallel between the third node and a ground terminal; The seventh transistor is coupled between the power supply terminal and a fourth node; The eighth transistor is coupled between the second node and the fourth node; The ninth transistor is coupled between the second node and a fifth node; The tenth transistor and the eleventh transistor are coupled in series between the fourth node and a first output terminal; The twelfth transistor and the thirteenth transistor are coupled in series between the fifth node and the first output terminal; The fourteenth transistor is coupled between the fifth node and the ground terminal; and The fifteenth transistor is coupled between the first output terminal and the ground terminal. The fifteenth transistor, the sixteenth transistor and the seventeenth transistor are coupled in parallel between the power supply end and a sixth node; The eighteenth transistor is coupled between the first output end and the sixth node; The nineteenth transistor is coupled between the first output end and a seventh node; The twentieth transistor, the twenty-first transistor and the twenty-second transistor are coupled in parallel between the seventh node and the ground end; Control terminals of the third transistor, the fourth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor and the twentieth transistor are configured to receive a first input; Control terminals of the first transistor, the fifth transistor, the seventh transistor, the fourteenth transistor, the sixteenth transistor and the twenty-first transistor are configured to receive a second input; Control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the seventeenth transistor and the twenty-second transistor are configured to receive a third input; Control terminals of the eighteenth transistor and the nineteenth transistor are coupled to the second node; The twenty-third transistor and the twenty-fourth transistor are coupled in series between the power supply end and the ground end, and a coupling point of the twenty-third transistor and the twenty-fourth transistor is a second output end; Control terminals of the twenty-third transistor and the twenty-fourth transistor are coupled to the second node.

12. The accumulator of claim 11, wherein, The first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the twenty-third transistor are PMOS transistors; The fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-fourth transistor are NMOS transistors.

13. The accumulator of claim 2, wherein, The first compressor or the second compressor comprises an operator circuit, and the operator circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a twenty-fourth transistor; wherein, The first transistor and the second transistor are coupled in parallel between a power supply end and a first node; The third transistor is coupled between the first node and a first output end; The fourth transistor is coupled between the first output end and a second node; and The first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the twenty-third transistor are PMOS transistors. The fifth transistor and the sixth transistor are coupled in parallel between the second node and a ground terminal; The seventh transistor is coupled between the power terminal and a third node; The eighth transistor is coupled between the third node and the first output terminal; The ninth transistor is coupled between the first output terminal and a fourth node; The tenth transistor and the eleventh transistor are coupled in series between the third node and a fifth node; The twelfth transistor and the thirteenth transistor are coupled in series between the fourth node and the fifth node; The fourteenth transistor is coupled between the fourth node and the ground terminal; The fifteenth transistor, the sixteenth transistor and the seventeenth transistor are coupled in parallel between the power terminal and a sixth node; The eighteenth transistor is coupled between the fifth node and the sixth node; The nineteenth transistor is coupled between the fifth node and a seventh node; The twentieth transistor, the twenty-first transistor and the twenty-second transistor are coupled in parallel between the seventh node and the ground terminal; Control terminals of the third transistor, the fourth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor and the twentieth transistor are configured to receive a first input; Control terminals of the first transistor, the fifth transistor, the seventh transistor, the fourteenth transistor, the sixteenth transistor and the twenty-first transistor are configured to receive a second input; Control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the seventeenth transistor and the twenty-second transistor are configured to receive a third input; Control terminals of the eighteenth transistor and the nineteenth transistor are coupled to the first output terminal; The twenty-third transistor and the twenty-fourth transistor are coupled in series between the power terminal and the ground terminal, and a coupling point of the twenty-third transistor and the twenty-fourth transistor is a second output terminal; Control terminals of the twenty-third transistor and the twenty-fourth transistor are coupled to the fifth node.

14. The accumulator of claim 13, wherein, The first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the twenty-third transistor are PMOS transistors; The fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-fourth transistor are NMOS transistors.

15. A multiplier, characterized by The multiplier comprises an encoder and an accumulator as claimed in any one of claims 1 to 14.

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