Rapid radio frequency packaging

Abstract

A device package including a chip carrier having a cavity and one or more microwave waveguides configured to route signals. There is a chip including one or more pads and located within the cavity of the chip carrier. Each pad is aligned with a corresponding connector pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one pad of the one or more pads is coupled to the connector pad of the corresponding microwave waveguide by way of an overlapping capacitive coupling between the at least one pad and the corresponding connector pad of the microwave waveguide with which the at least one pad is aligned.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to packaging chips, and more particularly to efficient packaging of superconducting devices. BACKGROUND

[0002] To enable a semiconductor chip to communicate with the outside world, it is typically packaged in a support housing that not only facilitates communication with external components, but also physically and thermally protects the chip. Conventional packaging techniques typically rely on a "permanent" connection between the package and the packaged chip. The typical connection between pads on the chip and the connector pads of the package can include permanent solder, wire bonds, thermal ultrasonic bonds, or other permanent bonding techniques, which make subsequent separation and replacement impractical. SUMMARY

[0003] According to an embodiment, a device package includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. There is a chip including one or more pads and located within the cavity of the chip carrier. Each pad is aligned with a corresponding connector pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one pad of the one or more pads is coupled to the connector pad of the corresponding microwave waveguide by virtue of an overlapping capacitive coupling between the at least one pad and the corresponding connector pad of the microwave waveguide with which the at least one pad is aligned.

[0004] In one embodiment, the chip is a quantum chip.

[0005] In one embodiment, the chip carrier is a printed circuit board (PCB).

[0006] In one embodiment, there is a block configured to press the chip into the cavity of the chip carrier. The chip can be a quantum chip, and the block can be a thermalization block operable to thermalize the quantum chip.

[0007] In one embodiment, the block includes one or more springs operable to press the chip onto the cavity of the chip carrier.

[0008] In one embodiment, the microwave waveguides are superconducting and include a superconductor or are coated with a superconductor, such as copper. For example, the microwave waveguides can include niobium or copper coated with a superconductor, such as tin.

[0009] In one embodiment, the superconducting microwave waveguides of the chip carrier are routed in three dimensions onto a connector plane, the connector plane including a ball grid array (BGA).

[0010] In one embodiment, the alignment between the chip and the cavity of the chip carrier is within 0.2 times the width of the connector pad.

[0011] In one embodiment, the chip carrier includes a plurality of additional cavities. At least one additional cavity of the plurality of additional cavities includes a given chip having one or more pads located within the at least one additional cavity. Each pad of the given chip is aligned with a corresponding connector pad of a microwave waveguide of the chip carrier. At least one pad of the one or more pads of the given chip is coupled to its aligned corresponding connector pad of the chip carrier by an overlapping capacitive coupling.

[0012] In one embodiment, the chip is a quantum chip and the given chip is not a quantum chip.

[0013] According to one embodiment, a chip packaging system includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. An interpose chip includes one or more pads and is located within the cavity of the chip carrier. One or more chips are bonded to the interpose chip. Each pad of the interpose chip is aligned with a corresponding connector of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one pad of the one or more pads is coupled to the corresponding connector pad of the corresponding microwave waveguide by means of an overlapping capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.

[0014] In one embodiment, the chip is a quantum chip and the chip carrier is a printed circuit board (PCB).

[0015] In one embodiment, there is a block configured to press the interpose chip into the cavity of the chip carrier.

[0016] In one embodiment, the block includes one or more springs for pressing the interpose chip onto the cavity of the chip carrier.

[0017] According to one embodiment, a method of packaging a chip includes providing a chip carrier having a cavity and one or more microwave waveguides to route signals. A chip including one or more pads is directed into the cavity of the chip carrier. Each pad of the chip is aligned with a corresponding connector pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one pad of the one or more pads is coupled to the corresponding connector of the corresponding microwave waveguide by means of an overlapping capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.

[0018] In one embodiment, the chip is pressed into the cavity of the chip carrier by a thermalizing block.

[0019] In one embodiment, the pressing includes one or more springs of the thermalizing block that press the chip onto the cavity of the chip carrier.

[0020] In one embodiment, the chip carrier includes a plurality of additional cavities. At least one additional cavity of the plurality of additional cavities includes a given chip having one or more pads located within the at least one additional cavity. Each pad of the given chip is aligned with a corresponding connector pad of the microwave waveguide of the chip carrier. At least one pad of the one or more pads of the given chip is coupled to its aligned corresponding connector pad of the chip carrier by an overlapping capacitive coupling.

[0021] In one embodiment, a function of a chip is determined. Upon determining that the chip is defective, the chip is removed and replaced with a new chip.

[0022] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Additionally or alternatively, other embodiments can be used. Details that can be obvious or unnecessary can be omitted to save space or for a more effective presentation. Some embodiments can be practiced with additional or different components or steps, and / or without all of the components or steps shown. When the same numeral appears in different drawings, it designates the same or similar components or steps.

[0024] FIG. 1A A perspective view of a packaged chip consistent with the illustrative embodiments is provided.

[0025] FIG. 1B A top view of a printed circuit board having a cutout consistent with the illustrative embodiments is provided. FIG. 1A

[0026] FIG. 1C FIG. 1D A top view and a bottom view of a chip having a waveguide transmitter, respectively, according to an example implementation are shown.

[0027] FIG. 2A A cutaway view of a package consistent with the illustrative embodiments is provided.

[0028] FIG. 2B A chip carrier cutout configured to accept a chip according to the illustrative embodiments is shown.

[0029] FIG. 3 ​​A packaged multi-chip configuration is shown in accordance with an exemplary embodiment.

[0030] FIG. 4 A cross-section of a chip coupled to a printed circuit board by wire bonding in accordance with an illustrative embodiment is provided.

[0031] FIG. 5 A cross-section view of a chip coupled to a printed circuit board by capacitive coupling in accordance with an illustrative embodiment.

[0032] FIG. 6 A cross-section view of a chip coupled to a printed circuit board with a spring-loaded thermalization structure in accordance with an illustrative embodiment.

[0033] FIG. 7 A cross-section view of a structure with a chip coupled to a printed circuit board with a carrier chip in accordance with an illustrative embodiment.

[0034] FIG. 8A to FIG. 8C Example simulation results for coupling capacitance between a chip's pads and a connector pad on a printed circuit board for a fixed vertical distance between coplanar waveguides of 100 nm are provided. DETAILED DESCRIPTION

[0035] SUMMARY

[0036] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the relevant teachings. However, it will be apparent to one skilled in the art that the present teachings can be practiced without these specific details. In other instances, well-known methods, procedures, components, and / or circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

[0037] In one aspect, spatially relative terms, such as "front," "back," "top," "bottom," "under," "below," "lower," "over," "upper," "side," "left," "right," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device described is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first," "second," "third," "fourth," and / or the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive

[0038] As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to a first surface of a chip.

[0039] As used herein, the term "vertical" describes an orientation arranged perpendicular to a first surface of a chip, chip carrier, or semiconductor body.

[0040] As used herein, the terms "coupled" and / or "electrically coupled" do not necessarily imply that the elements must be directly coupled together - intervening elements can be provided between "coupled" or "electrically coupled" elements. Conversely, if elements are referred to as being "directly connected" or "directly coupled" to another element, then there are no intervening elements. The term "electrically connected" refers to a low ohmic electrical connection between elements that are electrically connected together.

[0041] Although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] The exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures) of the present application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the regions illustrated in the figures are schematic and their shapes do not necessarily illustrate the actual shape of a region of a device and are not limiting of the scope of the present application.

[0043] It should be understood that other embodiments might be utilized without departing from the scope of the present application as defined by the claims. Structural or logical changes can be made without departing from the scope of the present application. The description of the embodiments is not limiting. In particular, elements of the embodiments described below can be combined with elements of different embodiments.

[0044] The present disclosure relates generally to fast and easily replaceable packaging of chips. By way of example only and not by way of limitation, concepts are discussed herein in the context of quantum technology and quantum chips, although it is to be understood that the teachings can also be applied to different types of chips. With respect to quantum technology, electromagnetic energy associated with a qubit can be stored in, for example, a so-called Josephson junction and capacitive and inductive elements used to form the qubit. In other examples, there can be spin qubits coupled to resonators or topological qubits, microfabricated ion traps, etc. The teachings herein also support other types of microwave components that can be adjusted or easily replaced, including but not limited to circulators, isolators, amplifiers, filters, active control electronics (such as rapid single flux quantum (RSFQ)), etc.

[0045] In one example, to read out the qubit state, a microwave signal is applied to the microwave readout cavity, which is coupled to the qubit at the cavity frequency. The transmitted (or reflected) microwave signal passes through multiple thermal isolation stages and low noise amplifiers, which are used to block or reduce noise and improve the signal-to-noise ratio. The amplitude and / or phase of the returned / output microwave signal carries information about the qubit state, e.g., whether the qubit has been phase shifted to the ground or excited state. The microwave signal carrying quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons). Different circuits and techniques can be used to measure the weak signal. For example, low noise quantum limited amplifiers (QLAs), such as Josephson amplifiers and traveling wave parametric amplifiers (TWPAs), can be used as preamplifiers at the output of a quantum system to boost the quantum signal while adding a minimum amount of noise specified by quantum mechanics in order to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components using Josephson amplifiers or Josephson mixers, such as Josephson circulators, Josephson isolators, and Josephson mixers, can be used in scalable quantum processors.

[0046] The ability to include more qubits is significant to the potential to enable a quantum computer. Applicant has recognized that in order to increase the computing power and reliability of a quantum computer, improvements can be made in different dimensions. First, is the qubit count itself. The more qubits in a quantum processor, the more states, in principle, can be manipulated and stored. Second is the low error rate, which involves precisely manipulating qubit states and performing sequential operations that provide consistent results rather than just unreliable data. Third, qubit technology is still a developing field, and providing qubits with a predetermined frequency with high precision is a challenge. For example, in some scenarios, consistent manufacturing of a qubit with a 5.20 GHz center frequency can not be achieved repeatably. Thus, it is desirable to have a modular system with multiple quantum chips, and to be able to easily replace qubits that do not have the desired center frequency or simply are defective.

[0047] Thus, in order to improve the fault tolerance of a quantum computer system, a large number of physical qubits should be used to store logical qubits. In this way, the local information is delocalized, such that the quantum computer is less susceptible to local errors and the performance of measurements in the eigenbasis of the qubits, similar to parity checks for classical computers, thereby advancing to more fault-tolerant qubits.

[0048] In order for a semiconductor chip, such as a quantum chip, to communicate with the outside world, it is typically coupled to or packaged in a support shell that not only facilitates communication, but also physically and thermally protects the quantum chip. Existing support shells can suffer from different challenges. For example, conventional bonding is a time-consuming and resource-intensive process that can not provide sufficient impedance matching in the transition between a chip carrier, such as a printed circuit board (PCB), to the chip. Further, conventional bonding can reduce the ability to provide a cavity around the chip for efficient guiding of the chip onto the PCB or provide sufficient access to the relevant chip surface for processing or inspection.

[0049] Conventional packaging techniques can involve vertical through-silicon vias (TSVs), which introduce manufacturing challenges and can affect coherence during the manufacturing process. The packaging can even strain the chip during cooling. For example, point forces on the chip, such as from pogo pins, can cause the chip to crack. Differences in the coefficient of expansion between the chip and the packaging can strain the chip (e.g., lateral strain). Still further, in conventional quantum chip packaging, the overlap of lossy / normal materials with different modes of the qubit can cause loss, collectively referred to herein as packaging-induced decoherence.

[0050] The concepts discussed here offer various improvements to packaged chips, such as quantum chips, as will be described in more detail below. For example, the effort and time required to couple a chip to a PCB are greatly reduced by the degree of freedom in the physical bonding between the chip's pads and the corresponding connector pads (such as a PCB) on the chip carrier. The ease and flexibility of removing the chip from the PCB allows for easy, individual replacement of the chip with different chips that meet desired criteria. This flexibility can be particularly useful in, for example, compliance experiments and materials evaluation. Similarly, chips can be easily replaced with those having more desirable qubit frequencies because no physical bonds are removed and reintroduced during the replacement process. Since there are no physical bonding wires connecting the chip and the PCB, the chip carrier and the corresponding connector pads can be easily reused. Since the chip is not mechanically fixed to the chip carrier as in conventional packaging, strain during cooling is mitigated. Furthermore, in some embodiments, the teachings herein readily facilitate multi-chip modular devices.

[0051] The techniques described in this article can be implemented in several ways. Exemplary implementations are provided below with reference to the accompanying figures.

[0052] Example encapsulation architecture

[0053] FIG. 1A to 1D Together, they provide an overview of different aspects of the packaging concept of the invention, consistent with the illustrative embodiments. More specifically, FIG. 1A A perspective view of packaged chip 100A is provided. In various scenarios, the packaged chip may operate at room temperature or cryogenic temperatures. Coaxial cable 102 may be coupled to various test and measurement devices (e.g., operating at room temperature) to determine whether one or more chips connected to the chip carrier should be replaced by the simple removal and insertion of the chip described herein. In various embodiments, the conductors on the chip carrier may be microstrip and / or coplanar waveguides (CPWs). In one embodiment, the chip carrier is a PCB.

[0054] FIG. 1B Provided FIG. 1A A top view 100B of a PCB is provided, which has a cutout operable to receive a chip 100C. The chip 100C can be directly placed (e.g., inserted) onto a connector pad of the PCB (e.g., a coplanar waveguide (CPW) line in the PCB). In this respect, FIG. 1C and FIG. 1D Top and bottom views of a chip with waveguide transmitter 130 are shown respectively. An equivalent waveguide transmitter (e.g., 130) facing the chip is present on PCB 100B. For example, the center wire in waveguide transmitter 130 is a signal line, and the two outer wires are grounded. Each waveguide transmitter acts as a pad connected via capacitive coupling.

[0055] Reference is now made to FIG. 2A which provides a cross-sectional view of package 200A consistent with the illustrative embodiments. FIG. 2A including chip 220 communicatively coupled with PCB 228 by capacitive coupling between pads on chip 220 and corresponding connector pads on PCB 228. The actual connector pads and pads of chip are not shown in FIG. 2A but are discussed in more detail later, including in the context of FIG. 2B For example, by capacitive coupling, signals from chip 220 are transmitted through the connector pads on PCB 228 and travel through the CPWs that lead to the launch pads of PCB 228. Two fasteners 242 and 244 are used to press the chip into the PCB recess and to align the chip, PCB, and thermalization block (discussed in more detail in the context of FIG. 5 These launch pads on chip 220 are aligned with corresponding connector pads on PCB 228, respectively, and are able to communicate by sending microwave signals by way of capacitive coupling. In this regard, FIG. 2B shows a chip carrier (e.g., PCB) having a cutout 200C configured to receive chip 200B. For example, chip 200B can be placed (e.g., flip-chip) onto PCB cutout 200C, where the pads on chip 130 (e.g., sometimes referred to herein as waveguides or waveguide launchers) are aligned with corresponding connector pads on the PCB in cutout 200C.

[0056] Accordingly, a chip (which can be a quantum chip) can be placed (e.g., flip-chipped) directly onto a cutout of a chip carrier (e.g., PCB) without the need for a physical connection between the pads of the chip and connector pads on the chip carrier. For example, the architecture described herein does not require permanent solder, wire, thermal sonic, or other permanent bonding between the chip and the PCB. Rather, chip 200B is flip-chipped and placed onto the cavity of the chip carrier such that the pads on the chip are directly aligned with and face the connector pads on the chip carrier (e.g., PCB). The actual transmission of signals between the pads of the chip and their corresponding connectors on the chip carrier is by way of capacitive coupling (i.e., large overlapping capacitance between the pads on the chip and the corresponding connectors on the PCB). The chip and the PCB are held together in a non-invasive and non-permanent and easily removable manner to package the chip, as discussed in more detail below.

[0057] Thus, capacitive coupling between the pads of the chip (e.g., waveguide transmitter) and the corresponding connector pads of the PCB facilitates communication between the chip and the PCB. The CPW of the PCB can be used to route signals between different chips and / or devices. In one embodiment, superconducting wires and / or vias can be used in the PCB (e.g., tinned copper) to route signals in three dimensions and / or connect the signals to a connector plane (e.g., ball grid array).

[0058] In one embodiment, the chip 200B is aligned laterally to better than about 0.2*w, where w is the width of the connector (e.g., capacitor) pads. For example, the alignment is better than 50 um. Applicant has determined that such a tolerance provides sufficient overlap between the pads of the chip and the connector pads on the chip carrier (e.g., PCB with cutouts to receive the chip) to achieve the desired overlap capacitance for reliable capacitive coupling. Such alignment is provided by making precise cutouts in the PCB 200C that guide the chip 200B. The chip 200B is pressed against the PCB to minimize the distance "d" (see FIG. 2B) between the pads on the chip and their corresponding connectors on the PCB. In different embodiments, the minimization of the distance d can be achieved with a spring-based mechanism or with a thermal structure (e.g., copper block) that clamps the chip 200B and the PCB between two parts with fasteners (e.g., screws, clamps, etc.). These concepts are discussed in more detail later. FIG. 5 ) most of the time. In one embodiment, the chip 200B is aligned laterally to better than about 0.2*w, where w is the width of the connector (e.g., capacitor) pads. For example, the alignment is better than 50 um. Applicant has determined that such a tolerance provides sufficient overlap between the pads of the chip and the connector pads on the chip carrier (e.g., PCB with cutouts to receive the chip) to achieve the desired overlap capacitance for reliable capacitive coupling. Such alignment is provided by making precise cutouts in the PCB 200C that guide the chip 200B. The chip 200B is pressed against the PCB to minimize the distance "d" (see FIG. 2B) between the pads on the chip and their corresponding connectors on the PCB. In different embodiments, the minimization of the distance d can be achieved with a spring-based mechanism or with a thermal structure (e.g., copper block) that clamps the chip 200B and the PCB between two parts with fasteners (e.g., screws, clamps, etc.). These concepts are discussed in more detail later.

[0059] While the chip carrier configured to receive a single chip is shown by way of example in FIG. 1A and 2B , it should be understood that the teachings herein are not so limited. In this regard, reference is now made to FIG. 3 , which shows a multi-chip configuration 300 of a package consistent with the example embodiments. In various embodiments, the multi-chip configuration 300 can include an array of similar (e.g., qubit) chips 302 or a combination of different types of chips (e.g., control logic, amplifiers, readout circuitry, power supplies, quantum chips, etc.) that are communicatively connected to a multi-chip PCB 350 through capacitive coupling between pads on the chips 302-324 and their corresponding connector pads on the PCB 350. Two or more of the chips 302-324 can communicate with each other through capacitive coupling between pads on the chips and connector pads on the PCB 350. If any of the chips 302-324 does not function adequately, it can be easily replaced with another chip by way of quick removal of the old chip and insertion of the new chip. This flexibility is provided by virtue of the chips 302-324 not being permanently connected to the PCB 350 but rather being capacitively coupled. In this way, the functionality of the multi-chip configuration 300 can be facilitated and easily maintained over time.

[0060] To better understand the features of the teachings herein, it can be helpful to provide a comparison to known packaging techniques. To this end, FIG. 4 A cross-section of a chip coupled to a PCB 410 by wire bonds 402 is provided. Structure 400 includes a thermalization structure 414, sometimes referred to as a (e.g., copper) pushrod block, operable to hold a chip 406 above a cavity 416. The quantum chip 406 itself is physically connected to the PCB 410 by permanent wire bonds (e.g., 402). There is typically a shield 404 operable to encase this quantum chip 406. The shield 404 is held to the top surface of the PCB 410 by a clamp 412 that mechanically clamps or screws the shield 404 to the PCB 410 and the thermalization structure 414. There can be a shield 408 on the PCB. The PCB can include RF connectors 418 operable to communicate with other components by RF signals. Because the wire bonds (e.g., 402) are a relatively permanent connection, the quantum chip 406 cannot be easily replaced.

[0061] By contrast, reference is now made to FIG. 5 which is a cross-section of a chip 506 coupled to a chip carrier (e.g., PCB) 510 by capacitive coupling, consistent with illustrative embodiments. Structure 500 includes a thermalization structure 514 operable to hold a chip (e.g., quantum chip and / or control chip) 506 below a cavity 516. The thermalization structure 514 can include copper. In some embodiments, there is a shield 508 operable to complete the encasement of the chip 506 and protect the chip surface from stray fields or external influences. The shield can be mechanically secured to the bottom surface of the chip carrier (e.g., PCB) 510 by a clamp 512 that mechanically clamps or screws both the shield 508 and the thermalization structure 514 to the PCB 510. The clamping provided by the clamp 512 ensures that the thermal contact between the thermalization structure 514 and the chip 506 is adequate. With a copper block or already by large ground contacts at all edges of the chip (e.g., no waveguide anywhere), good thermal and electrical contact to ground is achieved. In one embodiment, there is a shield 502 on the PCB 510 operable to protect the chip circuitry from electromagnetic (EM) interference that provides a defined cavity.

[0062] The PCB 510 can include one or more RF connectors (e.g., 518 and 530) operable to communicate with other components through RF signals. Significantly, the connection between the pads on the chip 506 and the connector pads of the PCB 510 is not by way of a permanent connection (e.g., permanent solder, wire, thermal ultrasonic or other permanent bonding). Rather, the one or more connections between the chip 506 and the chip carrier 310 are by way of capacitive coupling between the pads on the chip 506 and the connector pads on the PCB 510 having a distance d. In one example, the overlap between the pads of the chip 506 and the chip carrier is about 500um. With a CPW transmitter (sometimes referred to herein as a pad of the chip) width of 100um, a coupling capacitance of 500fF has been observed with less than 5dB of signal attenuation. By virtue of this non-permanent connection, the chip 506 can be easily removed and replaced from the chip carrier 510. It will be appreciated that while the distance "d" is shown as a visible gap in the exploded view, this gap occurs despite the chip 506 being pressed against the PCB 510 by the thermalizing structure 514 and the clamp 512. In particular, as indicated previously, the distance "d" can be minimized by increasing the contact pressure between the chip 506 and the PCB 510. This in turn results in a reduced distance "d" and a corresponding increase in the coupling capacitance between the pads of the chip 506 and the PCB 510. In some implementations, the coupling capacitance can be varied by controlling the distance "d" based on the mechanical pressure applied between the chip and the chip carrier (e.g., via a screw clamp, spring, etc.).

[0063] Accordingly, the waveguide is brought to the edge of the chip and is configured as a waveguide transmitter, sometimes referred to herein as a pad of the chip. The dimension of the lateral dimension (w) of the pad of the chip is configured such that the impedance remains the same but the dimension of w is grown, for example, from 10um to 200um. There are corresponding waveguides exposed on the side of the chip carrier (e.g., PCB) 510 within the overlapping region. In one embodiment, the length "l" is about 1um. Accordingly, placing the chip on the chip carrier, the two ends of these waveguides (e.g., the pad of the chip and the connector on the chip carrier) form a plate capacitor with a length of l and a width of w. Applicants have determined that if "l" and "w" are large enough (typically l=500um, w=100-200um), the capacitive coupling is large enough such that transmission from the chip to the PCB is sufficient even with a separation "d" between the surface of the chip and the surface of the PCB, each with their corresponding waveguides. In this regard, FIG. 8A to FIG. 8C Exemplary simulation results are provided for the coupling capacitance between the pad of the chip and the connector on the PCB (i.e., their corresponding CPWs) for a fixed vertical distance of 100nm between the CPWs. FIG. 8C It is shown that the capacitance is linear with the length of the overlap l.

[0064] FIG. 6 is a cross-sectional view of a chip 506 coupled to a PCB 510 with a spring-loaded thermalization structure 514 consistent with illustrative embodiments. FIG. 6 Many of the components of FIG. 5 are substantially similar to those of and, therefore, are not repeated herein for the sake of brevity. The main difference is that there is one or more spring contacts 620 between the thermalization structure 514 and the chip 506, which are sometimes referred to herein as being spring-loaded. The spring loading can help to have a defined constant force on the chip, compensating for geometry changes due to cooling. Thus, the chip 606 is pressed to the connector pads of the chip carrier by the spring contacts pressing down on its back side. The actual coupling between the pads of the chip 606 and the connector pads on the PCB is by means of capacitive coupling as discussed herein.

[0065] FIG. 7 is a cross-sectional view 700 of a structure with a chip 706 coupled to a chip carrier (e.g., PCB) 510 with a carrier chip 608, according to illustrative embodiments. FIG. 7 Many of the components of FIG. 5 and 6 are substantially similar to those of FIG. 6 and, therefore, are not repeated herein for the sake of brevity. FIG. 7 One significant difference between FIG. 7 and is that the chip 608 (e.g., qubit) is not directly connected to the chip carrier (e.g., PCB) 510. Rather, the chip 606 is connected to the interposer chip 608 (sometimes referred to herein as a control chip) by a ball grid array (BGA), where the interposer chip 608 is coupled to the chip carrier 510 by capacitive coupling.

[0066] The chip 606 is shown within a cavity 716 of a shield 708. This quantum chip 706 can be connected via a plurality of superconducting interconnects (e.g., inner bumps) or similar to the control chip 608. Advantageously, such sandwiched chips can be easily replaced and do not need to be wire-bonded to the PCB.

[0067] The architecture discussed herein is useful in different fields, including but not limited to microwave packaging (e.g., for quantum engineering, quantum chips, superconducting quantum chips), quantum technology (e.g., quantum processors, packaging of quantum systems, packaging of superconducting qubits, etc.), cryogenic technology (e.g., thermalization, signal transfer, cryogenic microwave measurements, etc.), and the like.

[0068] CONCLUSION

[0069] The description of the different embodiments of the present teachings have been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0070] While the foregoing has described what are considered to be the best mode and / or other examples, it is recognized that various modifications can be made within the scope of the application, and the subject matter is not to be limited to what is described in the specification. The claims are intended to cover any and all applications, modifications and variations occurring within the true scope of the present teachings.

[0071] The components, steps, features, objects, benefits and advantages that have been discussed herein are merely illustrative. None of them, nor the discussion of the disclosed embodiments, are intended to limit, in any way, the scope of the claims. Although various advantages, benefits and features of the application have been set forth, it will be appreciated that not all advantages, benefits, and features are necessarily exhibited in all embodiments of the application. The description of the embodiments is intended to be read in connection with the various claims

[0072] Many other embodiments are contemplated. These include embodiments that have fewer, additional and / or different components, steps, features, objects, benefits and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0073] While the foregoing has described what are considered to be the best mode and / or other examples, it is recognized that various modifications can be made within the scope of the application, and the subject matter is not to be limited to what is described in the specification. The claims are intended to cover any and all applications, modifications and variations occurring within the true scope of the present teachings.

[0074] It should be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions by those skilled in the respective querying and research fields, except where expressly stated otherwise. Relationaiy terms such as first and second, and the like can be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a" does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0075] The abstract of the disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims. In addition, in the above Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are explicitly recited in each claim. Rather, inventive subject matter consists of all features that are one of individualized in each claim and also of all combinations of features in the specification without the particular, explicit recitation of such a combination in a claim. Thus, the following claims, by themselves, are hereby incorporated into the detailed description.

Claims

1. A device package, comprising: A chip carrier having a notch and one or more microwave waveguides configured to route signals; as well as A chip, comprising qubits and one or more pads, is received within the notch of the chip carrier and has cavities on its top and bottom surfaces, wherein: Each of the one or more pads is aligned with a corresponding connector pad of a microwave waveguide in one or more microwave waveguides of the chip carrier. as well as The chip-side waveguide connected to at least one of the one or more pads is coupled to the corresponding microwave waveguide by means of the overlapping capacitive coupling between the at least one pad and the corresponding connector pad of the microwave waveguide to which it is aligned.

2. The device package according to claim 1, wherein the waveguide on the chip side and the microwave waveguide are coplanar waveguides.

3. The device package according to claim 1, wherein the chip carrier is a printed circuit board (PCB).

4. The device package of claim 1, further comprising a block configured to press the chip into the notch of the chip carrier.

5. The device package according to claim 4, wherein: The block is a thermalizing block, which is operable to thermalize the chip.

6. The device package of claim 4, wherein the block includes one or more springs that operate to press the chip onto the notch in the chip carrier.

7. The device package of claim 1, wherein the microwave waveguide is superconducting and comprises niobium or copper coated with a superconductor.

8. The device package of claim 1, wherein the microwave waveguide of the chip carrier is routed in three dimensions to a connector plane, the connector plane comprising a ball grid array (BGA).

9. The device package of claim 1, wherein the alignment between the chip and the notch of the chip carrier is within 0.2 times the width of the connector pad.

10. The device package of claim 1, wherein: The chip carrier includes multiple additional cutouts; At least one of the plurality of additional cuts includes a given chip with one or more pads located within the at least one additional cut; Each pad of the given chip is aligned with the corresponding connector pad of the microwave waveguide of the chip carrier. as well as At least one of the pads of the given chip is coupled to the corresponding connector pad of the chip carrier to which it is aligned via overlapping capacitive coupling.

11. The device package of claim 10, wherein: The given chip is not a quantum chip.

12. A chip packaging system, comprising: A chip carrier having a notch and one or more microwave waveguides configured to route signals; An insert chip is provided, the insert chip comprising one or more pads and being received within the cutout of the chip carrier; as well as One or more chips, said one or more chips being coupled to said insert chip and having qubits, wherein: Each pad of the inserted chip is aligned with a corresponding connector pad of a microwave waveguide in one or more microwave waveguides of the chip carrier; and The waveguide on the insert chip side, which is connected to at least one of the one or more pads, is coupled to the corresponding microwave waveguide by means of the overlapping capacitive coupling between the at least one pad and the corresponding connector pad of the microwave waveguide to which it is aligned. The one or more chips that are joined together have cavities on the top and bottom surfaces of the inserted chip.

13. The chip packaging system according to claim 12, characterized in that: The waveguide on the chip insertion side and the microwave waveguide are coplanar waveguides; and The chip carrier is a printed circuit board (PCB).

14. The chip packaging system of claim 12, further comprising a block configured to press the insert chip into the notch of the chip carrier.

15. The chip packaging system according to claim 14, wherein, The block includes one or more springs that operate to press the inserted chip onto the notch in the chip carrier.

16. A method for packaging a chip, comprising: A chip carrier providing one or more microwave waveguides with notches and routing signals; A chip including qubits and one or more pads is guided into the notch of the chip carrier, the chip having cavities on its top and bottom surfaces; Align each pad of the chip with the corresponding connector pad of the microwave waveguide in one or more microwave waveguides of the chip carrier. as well as The chip-side waveguide connected to at least one of the one or more pads is coupled to the corresponding microwave waveguide by means of overlapping capacitive coupling between at least one of the pads and the corresponding connector pad of the microwave waveguide to which it is aligned.

17. The method of claim 16, further comprising pressing the chip into the cutout of the chip carrier using a thermal block.

18. The method of claim 17, wherein the pressing comprises one or more springs of the thermal block pressing the chip onto the notch of the chip carrier.

19. The method according to any one of claims 16 to 18, wherein: The chip carrier includes multiple additional cutouts; At least one of the plurality of additional cuts includes a given chip with one or more pads located within the at least one additional cut; Each pad of the given chip is aligned with the corresponding connector pad of the microwave waveguide of the chip carrier. as well as At least one of the pads of the given chip is coupled to the corresponding connector pad of the chip carrier via overlapping capacitive coupling.

20. The method according to any one of claims 16 to 18, further comprising: Determine the function of the chip; as well as When it is determined that the chip is defective: Remove the chip; as well as Replace the chip with a new one.

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