Thermal Resistance Testing Method for Small Package and Method for Obtaining Its Case Temperature
By carrying the back of the small package on the cold water table, the thermocouple contacts the base island, and setting a thermal conductive material between the back and the cold water table, the problem of inaccurate thermal resistance testing of small and medium-sized packages in the prior art is solved, and a single heat dissipation path and accurate thermal resistance value acquisition that complies with JEDEC standards is achieved.
Patent Information
- Application Number
- CN202111106751.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-22
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2041-09-22
AI Technical Summary
The thermal resistance testing methods of the prior art small and medium-sized packaging cannot accurately obtain the shell temperature, causing the thermal resistance value to deviate from the theoretical value and do not meet the single heat dissipation path requirements of the JEDEC test standards.
By carrying the back of the small package on the cold water table, the thermocouple contacts the base island, using a PCB board as the adapter structure, and a thermally conductive material is set between the back and the cold water table to ensure a single heat dissipation path while obtaining the accurate shell temperature.
A single heat dissipation path that complies with JEDEC testing standards is realized, and the shell temperature is obtained is accurate, thereby obtaining accurate thermal resistance values.
Smart Images
Figure CN115932517B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, and in particular to a method for testing the thermal resistance of a small package and a method for obtaining the shell temperature thereof. Background Art
[0002] The thermal characteristics of semiconductor devices are one of the important contents in reliability design. In order to ensure the reliability of the device during use, the structural design of the device must take into account the heat dissipation characteristics of the device, and the quantitative calculation of these designs must be based on the thermal resistance parameters of the device. Therefore, the thermal resistance of semiconductor devices is an important parameter that reflects the thermal characteristics of the device.
[0003] The resistance encountered by heat on the heat conduction path is thermal resistance. It is defined as the ratio of the temperature difference on the heat conduction path to the power consumption. The thermal resistance from the junction to the shell of the device is the thermal resistance between the heat source junction of the chip and the package shell. The junction temperature T of the device when it is working can be obtained by the thermal resistance tester. J According to the test method specified in the JEDEC test standard, when conducting the junction-to-case thermal resistance test, the device package case temperature (i.e., case temperature T C ) is controlled at a fixed temperature through a temperature control platform, so the junction-to-case thermal resistance of the device can be obtained.
[0004] Small packages have small pin areas and tight layouts, while the terminal areas of the connecting wires of the thermal resistance tester are large, so it is easy for the pins and connecting wires to short-circuit when they are directly connected. In related technologies, a PCB board is generally used as a transfer structure to first connect the small package to the PCB board, and then the PCB board is placed on a cold water table for testing. The actual test results show that the thermal resistance value obtained by the above thermal resistance test method deviates greatly from the theoretical thermal resistance value.
[0005] To solve the above problems, the industry has begun to install cooling fans or heat sinks around small packages to improve the heat dissipation performance of small packages. Although there is a certain improvement effect, it does not meet the single heat dissipation path requirement specified in the JEDEC test standard.
[0006] In order to meet the requirement of a single heat dissipation path, a heat sink is installed between the PCB and the cold water table. However, the measured thermal resistance value is highly sensitive to the uniformity of the contact degree of each area of the PCB, the heat sink and the cold water table. However, it is difficult to control the uniformity of the contact degree of each area of the PCB, the heat sink and the cold water table. Summary of the invention
[0007] The object of the present invention is to provide a method for testing the thermal resistance of a small package and a method for obtaining the shell temperature thereof, so as to obtain accurate shell temperature and thermal resistance values.
[0008] To achieve the above object, a first aspect of the present invention provides a method for obtaining the case temperature in the thermal resistance test of a small package, including:
[0009] Provide a small package and a PCB board. The small package includes a chip and a lead frame carrying the chip. The lead frame includes a base island and pins. The base island is exposed on the back of the small package, and the pins are at least exposed on the side of the small package. The PCB board includes a first set of electrical connection terminals and a second set of electrical connection terminals electrically connected together. The front of the small package faces the front of the PCB board, and the pins are connected to the first set of electrical connection terminals.
[0010] The back of the small package faces the cold water table of the testing machine. Place the small package on the cold water table and make the thermocouple located on the cold water table contact the base island. Connect the second set of electrical connection terminals to the testing machine.
[0011] The testing machine provides a predetermined power to the small package through the PCB board, and obtains the case temperature of the small package through the thermocouple.
[0012] Optionally, the first set of electrical connection terminals is located on the front of the PCB board. The PCB board has a groove, and the opening of the groove is located on the front of the PCB board. The groove is adapted to accommodate at least part of the height of the small package.
[0013] Optionally, when the small package is placed in the groove, the ratio of the height difference between the side of the pin close to the bottom wall of the groove and the first set of electrical connection terminals to the thickness of the small package ranges from 0.15 to 0.3.
[0014] Optionally, when the small package is placed on the cold water table, the thermocouple contacts the center of the base island.
[0015] Optionally, the testing machine includes an adiabatic pressing block. After the small package is placed on the cold water table, the adiabatic pressing block is arranged on the back of the PCB board.
[0016] Optionally, the second set of electrical connection terminals is located on the back of the PCB board.
[0017] Optionally, a thermal conductive material is arranged between the back of the small package and the cold water table.
[0018] Optionally, the small package includes at least one of DFN 3*3 and DFN 5*6.
[0019] The second aspect of the present invention provides a method for testing the thermal resistance of a small package, including: obtaining the case temperature according to the method for obtaining the case temperature in the thermal resistance test of the small package described in any one of the above, and obtaining the junction temperature of the small package through the parasitic diode in the chip.
[0020] Optionally, obtaining the junction temperature of the small package through the parasitic diode in the chip includes: obtaining the forward voltage drop of the parasitic diode through the test machine platform, and obtaining the junction temperature of the small package according to the K coefficient between the forward voltage drop of the parasitic diode and the temperature.
[0021] Optionally, before performing the thermal resistance test, the following is also performed: calibrating the K coefficient between the forward voltage drop of the parasitic diode and the temperature.
[0022] After analysis by the inventor, the reason why the thermal resistance values obtained by various thermal resistance test methods in the related art deviate greatly from the theoretical thermal resistance values is that: the thermocouple contacts the PCB board carried on the cold water table, so the measured case temperature is actually the temperature of the PCB board, rather than the case temperature of the small package.
[0023] Based on the above analysis, the present invention places the back surface of the small package on the cold water table, so that the thermocouple located on the cold water table contacts the base island of the small package.
[0024] Compared with the prior art, the beneficial effect of the present invention is that: it not only conforms to a single heat dissipation path, but also the obtained case temperature is accurate, so the obtained thermal resistance value is also accurate. Description of the Drawings
[0025] Figure 1 is a flowchart of the method for obtaining the case temperature in the thermal resistance test of the small package according to the first embodiment of the present invention;
[0026] Figure 2 is Figure 1 the bottom view of the small package corresponding to the process in
[0027] Figure 3 is Figure 1 the cross-sectional structure schematic diagram of the small package corresponding to the process in
[0028] Figure 4 is Figure 1 the top view of the PCB board corresponding to the process in
[0029] Figure 5 is Figure 2 and Figure 3 the small package in Figure 4 are connected together with the PCB board in
[0030] Figure 6 isFigure 2 And Figure 3 The cross-sectional structure schematic diagram of the connection between the small package in Figure 4 and the PCB board in
[0031] Figure 7 is Figure 2 And Figure 3 The cross-sectional structure schematic diagram of the small package in Figure 4 and the PCB board in
[0032] Figure 8 It is the cross-sectional structure schematic diagram of the connection between the small package and the PCB board in the method for obtaining the case temperature in the thermal resistance test of the small package according to the second embodiment of the present invention;
[0033] Figure 9 It is the flowchart of the thermal resistance test method of the small package according to the third embodiment of the present invention.
[0034] For the convenience of understanding the present invention, all the reference numerals appearing in the present invention are listed below:
[0035] Small package 11 Chip 110
[0036] Lead frame 111 Base island 111a
[0037] Pin 111b Encapsulant 112
[0038] The front side 11a of the small package The back side 11b of the small package
[0039] The side 11c of the small package PCB board 12
[0040] The front side 12a of the PCB board The back side 12b of the PCB board
[0041] The first set of electrical connection terminals 121 Cold water table 13
[0042] Thermocouple 14 Thermal conductive material 15
[0043] Adiabatic pressing block 16 Groove 120 Detailed implementation manners
[0044] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0045] Figure 1 It is the flowchart of the method for obtaining the case temperature in the thermal resistance test of the small package according to the first embodiment of the present invention; Figure 2 is Figure 1 The bottom view of the small package corresponding to the process in Figure 3 is Figure 1A schematic diagram of the cross-sectional structure of a small package corresponding to the process in FIG. Figure 4 yes Figure 1 The top view of the PCB board corresponding to the process in; Figure 5 yes Figure 2 and Figure 3 Small package and Figure 4 A top view of the PCB boards connected together; Figure 6 yes Figure 2 and Figure 3 Small package and Figure 4 A schematic diagram of a cross-sectional structure in which the PCB boards are connected together; Figure 7 yes Figure 2 and Figure 3 Small package and Figure 4 Schematic diagram of the cross-sectional structure of the PCB board placed on the cold water table.
[0046] First, refer to Figure 1 Step S1 in Figures 2 to 6 As shown, a small package 11 and a PCB board 12 are provided. The small package 11 includes a chip 110 and a lead frame 111 carrying the chip 110. The lead frame 111 includes a base island 111a and pins 111b. The base island 111a is exposed on the back side 11b of the small package 11, and the pins 111b are exposed on at least the side 11c of the small package 11; the PCB board 12 includes a first group of electrical connection terminals 121 and a second group of electrical connection terminals (not shown) electrically connected together; the front side 11a of the small package 11 faces the front side 12a of the PCB board 12, and the pins 111b are connected to the first group of electrical connection terminals 121.
[0047] The small package 11 refers to a chip package structure that cannot be directly connected to the connection line of the thermal resistance test machine due to its small area and dense layout, and needs to adopt a PCB board transfer. Figure 2 As shown, the small package 11 is DFN 3*3. In other embodiments, the small package 11 may also be DFN 5*6 or the like.
[0048] In this embodiment, the chip 110 of the small package 11 can be a vertical channel MOS transistor, including a source, a drain and a gate. A parasitic diode, i.e., a PN junction, is formed between the source and the drain. Figure 3 As shown, the drain is electrically connected to the base island 111a. The source and the gate can be connected to the pin 111b through a wire. A molding compound 112 can be filled between the chip 110 and the lead frame 111.
[0049] The front side 11 a and the back side 11 b of the small package body 11 are opposite to each other. In this embodiment, the front side 11 a exposes the molding compound 112 .
[0050] In this embodiment, referring to Figure 3 as shown, pin 111b is exposed not only on the side surface 11c of the small package 11, but also on the back surface 11b.
[0051] Referring to Figure 2 as shown, in DFN 3*3, four pins 111b are connected to the base island 111a. In other words, in DFN 3*3, four pins 111b are connected to the drain; in addition, one pin 111b is connected to the gate, and three pins 111b are connected to the source.
[0052] In this embodiment, referring to Figure 4 and Figure 5 as shown, the first set of electrical connection terminals 121 has eight, which are respectively used to electrically connect eight pins 111b. Referring to Figure 5 and Figure 6 as shown, the first set of electrical connection terminals 121 is located on the front surface 12a of the PCB board 12, and the second set of electrical connection terminals is located on the back surface 12b of the PCB board 12. In other embodiments, the second set of electrical connection terminals may also be located on the front surface 12a of the PCB board 12.
[0053] The connection between the pin 111b and the first set of electrical connection terminals 121 can be achieved by soldering.
[0054] Next, referring to Figure 1 the steps S2 in Figure 7 and as shown, the back surface 11b of the small package 11 faces the cold water table 13 of the testing machine, place the small package 11 on the cold water table 13 and make the thermocouple 14 located on the cold water table 13 contact the base island 111a; connect the second set of electrical connection terminals to the testing machine.
[0055] After the back surface 11b of the small package 11 is placed on the cold water table 13, since the surface of the cold water table 13 is metal and has electrical conductivity, in order to prevent short circuits between the pins 111b exposed on the back surface 11b of the small package 11, at least the pins 111b connected to the source and gate of the vertical trench MOS transistor need to be electrically insulated. For example, use high-temperature insulating tape to stick on each pin 111b.
[0056] The testing machine has an integrated circuit, and the integrated circuit has a reserved interface, and the second set of electrical connection terminals can be connected to the reserved interface.
[0057] In this embodiment, in order to improve the heat dissipation effect of the small package 11 to the cold water table 13, a heat-conducting material 15, such as thermal grease, can be provided between the back surface 11b of the small package 11 and the cold water table 13. In addition, the testing machine further includes an adiabatic pressing block 16, and the adiabatic pressing block 16 can be provided on the back surface 12b of the PCB board 12.
[0058] After that, referring toFigure 1 Step S3 in Figure 7 As shown in Figure 7 , the test machine provides a predetermined power to the small package 11 through the PCB board 12, and obtains the case temperature T of the small package 11 through the thermocouple 14 C .
[0059] As described above, the integrated circuit of the test machine can be electrically connected to the source, drain, and respective pins 111b corresponding to the gate of the vertical-channel MOS transistor after passing through the second set of electrical connection terminals and the first set of electrical connection terminals 121.
[0060] It can be seen that the back surface 11b of the small package 11 is carried on the cold water table 13. The base island 111a has a good heat dissipation effect on the chip 110 relative to the plastic package 112. Therefore, the above test meets the requirements of a single heat dissipation path specified by the JEDEC test standard. In addition, the thermocouple 14 contacts the base island 111a of the small package 11, so the obtained case temperature T C is accurate.
[0061] Preferably, the thermocouple 14 contacts the center of the base island 111a of the small package 11. Relative to contacting the edge of the base island 111a, the heat dissipation path from the center of the base island 111a to the chip 110 is the shortest, which can ensure a single heat dissipation path.
[0062] Specifically, the alignment method between the center of the base island 111a and the thermocouple 14 can be achieved through the following two methods:
[0063] a) Mark the center of the base island 111a on the back surface 12b of the PCB board 12. With the PCB board 12 vertically downward, during the process of bringing the back surface 11b of the small package 11 close to the cold water table 13, the center of the base island 111a is aligned with the thermocouple 14.
[0064] After the small package 11 is connected to the PCB board 12, since the light transmittance of the chip 110 in the small package 11 is different from that of the plastic package 112, therefore, when the structure of the small package 11 and the PCB board 12 connected together faces the light, the chip 110 can be accurately identified, and the center of the chip 110 can be judged. The center of the chip 110 is the center of the base island 111a.
[0065] b) Measure the distance from the reference position to the thermocouple 14; use a robotic arm to drive the structure of the small package 11 and the PCB board 12 connected together by the above distance from the reference position.
[0066] Figure 8 is a schematic cross-sectional structure diagram of the connection between the small package and the PCB board in the method for obtaining the case temperature in the thermal resistance test of the small package according to the second embodiment of the present invention.
[0067] Refer to Figure 8As shown, the difference between the method for obtaining the case temperature in the thermal resistance test of the small package of this embodiment and the method for obtaining the case temperature in the thermal resistance test of the small package of Embodiment 1 is only that: in step S1, the PCB board 12 has a groove 120, and the opening of the groove 120 is located on the front surface 12a of the PCB board 12, and the groove 120 is adapted to accommodate a part of the height of the small package 11.
[0068] The above-mentioned groove 120 can reduce the height difference between the pins 111b and the first set of electrical connection terminals 121, thereby reducing the difficulty of the soldering process for connecting the two.
[0069] When the small package 11 is placed in the groove 120, the ratio range of the height difference between the side of the pin 111b close to the bottom wall of the groove 120 and the first set of electrical connection terminals 121 to the thickness of the small package 11 is preferably: 0.15 to 0.3. The side of the pin 111b close to the bottom wall of the groove 120 means that at least a part of the area where the first set of electrical connection terminals 121 can be connected to the pin 111b to achieve electrical connection between the two is sufficient, and it is not necessary to connect the entire side surface of the pin 111b. In the above range, on the one hand, the soldering process will not cause short circuits, and on the other hand, the first set of electrical connection terminals 121 will not contact the cold water table 13, and the first set of electrical connection terminals 121 will not be short-circuited to each other.
[0070] It should be noted that the numerical range in this embodiment includes the endpoint values.
[0071] Except for the above differences, the other steps of the method for obtaining the case temperature in the thermal resistance test of the small package of Embodiment 2 can refer to the corresponding steps of the method for obtaining the case temperature in the thermal resistance test of the small package of Embodiment 1.
[0072] Figure 9 It is the flowchart of the method for testing the thermal resistance of the small package of the third embodiment of the present invention.
[0073] Refer to Figure 9 As shown, the method for testing the thermal resistance of the small package includes: obtaining the case temperature according to the method for obtaining the case temperature in the thermal resistance test of the small package of any one of the above embodiments, and obtaining the junction temperature T of the small package 11 through the parasitic diode in the chip 110 J .
[0074] Specifically, step S3' obtains not only the case temperature T C , but also the junction temperature T J . According to Rjc = (T J - T C ) / (V * I), the thermal resistance value Rjc can be obtained.
[0075] Since there is an approximately linear function relationship between the forward voltage drop of the parasitic diode of the vertical channel type MOS transistor and the temperature. Therefore, obtaining the junction temperature TJ It may include: obtaining the forward voltage drop of the parasitic diode through a test machine, and obtaining the junction temperature T of the small package 11 according to the linear coefficient between the forward voltage drop of the parasitic diode and the temperature, abbreviated as the K coefficient. J When the vertical-channel MOS transistor is an NMOS, the anode of the parasitic diode is connected to the source of the NMOS transistor, and the cathode is connected to the drain.
[0076] In this embodiment, before performing the thermal resistance test, the following may also be performed: calibrating the K coefficient between the forward voltage drop of the parasitic diode and the temperature. The calibration process may include:
[0077] After the small package 11 is externally connected to the test machine and placed in an oil bath, the oil bath is heated to a certain temperature and then starts to cool naturally. The calculation of the K coefficient is based on the points collected during the cooling process (because the cooling process is very slow and the temperature change during natural cooling is very stable). By applying a small current to the parasitic diode, the forward voltage drop at the first temperature is obtained, and then a small current is applied to the parasitic diode again at the second temperature to obtain the forward voltage drop at the second temperature. Based on the two coordinate points, the K coefficient can be calculated. The above K coefficient is the calibrated K coefficient.
[0078] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for obtaining the case temperature in the thermal resistance test of a small package, characterized in that, Comprising: Providing a small package and a PCB board, the small package includes a chip and a lead frame carrying the chip, a molding compound is filled between the chip and the lead frame, the lead frame includes a base island and pins, the base island is exposed on the back of the small package, and the pins are at least exposed on the side of the small package; the PCB board includes a first set of electrical connection terminals and a second set of electrical connection terminals electrically connected together; the front of the small package faces the front of the PCB board, the pins are connected to the first set of electrical connection terminals, the PCB board has a groove, the opening of the groove is located on the front of the PCB board, and the groove is adapted to accommodate at least part of the height of the small package; The back of the small package faces the cold water table of the testing machine, place the back of the small package on the cold water table and make the thermocouple located on the cold water table contact the base island; Connect the second set of electrical connection terminals to the testing machine; The testing machine provides a predetermined power to the small package through the PCB board, and obtains the case temperature of the small package through the thermocouple.
2. The method for obtaining the case temperature in the thermal resistance test of the small package according to claim 1, characterized in that, The first set of electrical connection terminals is located on the front of the PCB board.
3. The method for obtaining the case temperature in the thermal resistance test of the small package according to claim 1, characterized in that, When the small package is placed on the cold water table, the thermocouple contacts the center of the base island.
4. The method for obtaining the case temperature in the thermal resistance test of the small package according to claim 1, wherein The testing machine includes an adiabatic pressing block; after the small package is placed on the cold water table, the adiabatic pressing block is arranged on the back of the PCB board.
5. The method for obtaining the case temperature in the thermal resistance test of the small package according to claim 4, wherein The second set of electrical connection terminals is located on the back of the PCB board.
6. The method for obtaining the case temperature in the thermal resistance test of the small package according to claim 1, characterized in that, A thermal conductive material is arranged between the back of the small package and the cold water table.
7. The method for obtaining the case temperature in the thermal resistance test of the small package according to claim 1, characterized in that The small package includes at least one of DFN 3*3 and DFN 5*6.
8. A method for testing the thermal resistance of a small package, characterized in that, Comprising: Obtaining the case temperature by the method for obtaining the case temperature in the thermal resistance test of the small package according to any one of claims 1 to 7, and obtaining the junction temperature of the small package through the parasitic diode in the chip.
9. The method for testing the thermal resistance of the small package according to claim 8, characterized in that Obtaining the junction temperature of the small package through the parasitic diode in the chip includes: obtaining the forward voltage drop of the parasitic diode through the testing machine, and obtaining the junction temperature of the small package according to the K coefficient between the forward voltage drop of the parasitic diode and the temperature.
10. The method for testing the thermal resistance of the small package according to claim 9, characterized in that, Before performing the thermal resistance test, it is also performed: calibrating the K coefficient between the forward voltage drop of the parasitic diode and the temperature.