A coarse-fine adjustment control logic circuit for a digital low dropout regulator
The digital logic control circuit for DLDOs addresses slow response times and complex fine-tuning by integrating a dynamic comparator and clock conversion circuit, enhancing sampling rate and response performance while reducing power consumption.
Patent Information
- Application Number
- CN202211532659.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-01
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2042-12-01
AI Technical Summary
Traditional digital LDO regulators have problems such as long response time, poor process mobility and high working voltage, and the existing coarse and fine adjustment schemes have complex structures and fine adjustment saturation problems.
The sampling clock is changed through the digital logic control circuit and the sampling clock conversion logic circuit through the digital logic control circuit and the sampling clock conversion logic circuit, and the sampling clock is changed to achieve rapid response and simplified circuit structure.
Improves the sampling rate and response performance of digital LDO regulators, reduces power consumption, shortens response time, and improves the convergence speed of DLDO.
Smart Images
Figure CN115933790B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a coarse-fine adjustment control logic circuit for a digital low-dropout regulator. Background Art
[0002] For traditional low-dropout (LDO) regulators, due to their advantages such as small output ripple, simple circuit structure, and small chip area occupation, they are widely used in various electronic devices, especially portable electronic devices. However, due to the characteristics of their analog circuits, they have the disadvantage of poor process migration, which is a very serious problem that has always troubled everyone. At the same time, traditional LDO regulators also have the problem of relatively high required operating voltage. Therefore, in recent years, digital LDOs have been gradually recognized due to their good process migration and low required operating voltage.
[0003] The structure of a traditional digital LDO regulator usually includes a voltage comparator, a serial input parallel output bidirectional shift register, a PMOSFET array, a feedback resistor network, and an output capacitor; when the output feedback voltage is less than the reference voltage, the voltage comparator outputs "0", otherwise it is "1"; the bidirectional shift register controls the number of transistors conducting in the PMOSFET array according to the output value of the voltage comparator to adjust the output voltage, so as to achieve the purpose of output voltage regulation. When the output voltage value is large, more PMOS transistors need to be conducted, resulting in a longer response time for the DLDO (digital low-dropout regulator) and a longer time required for recovery. Existing coarse-fine adjustment schemes approximate with a large step size first and then fine-tune with a small step size, but the structure is complex and there is a potential problem of saturation in fine-tuning. Summary of the Invention
[0004] Object of the Invention: The object of the present invention is to provide a coarse-fine adjustment control logic circuit for a digital low-dropout regulator that can improve the sampling rate and response performance of traditional digital low-dropout regulators.
[0005] Technical Solution: The coarse-fine adjustment control logic circuit of the present invention includes a dynamic comparator, a bidirectional shift register, a PMOS power transistor array, a PMOS auxiliary feedforward, a load capacitor and a load current source, a digital logic control circuit, and a sampling clock conversion control circuit;
[0006] The output end of the bidirectional shift register is connected to the input end of the PMOS power transistor array, and the output end of the PMOS power transistor array is connected to the output end of the PMOS auxiliary feedforward;
[0007] The input end of the load capacitor and the load current source is grounded, and the output end is connected to the PMOS power transistor array and serves as the terminal output end of the entire circuit;
[0008] The dynamic comparator includes a first input terminal, a second input terminal, and an output terminal. The output terminal is respectively connected to the input terminal of the bidirectional shift register, the input terminal of the PMOS auxiliary feedforward, and the input terminal of the digital logic control circuit;
[0009] The digital logic control circuit includes a first register, a second register, a first AND gate circuit, a second AND gate circuit with inversion, and a first OR gate circuit; the input terminal of the first register is connected to the output terminal of the dynamic comparator, and the output terminal is connected to the input terminal of the first AND gate circuit and the input terminal of the second AND gate circuit with inversion; the input terminal of the second register is connected to the input terminal of the first AND gate circuit and the input terminal of the second AND gate circuit with inversion; the output terminal of the dynamic comparator is connected to the third input terminal of the first AND gate circuit, and at the same time, the output terminal of the dynamic comparator after inversion is connected to the third input terminal of the second AND gate circuit; the output terminal of the first AND gate circuit and the output terminal of the second AND gate circuit with inversion are respectively connected to the first input terminal and the second input terminal of the first OR gate circuit;
[0010] The sampling clock conversion control circuit includes a first delay unit, a second delay unit, a NOT gate circuit, a second OR gate circuit, and a third AND gate circuit; the clock signal is respectively connected to the input terminal of the first delay unit and the second input terminal of the third AND gate circuit; the output terminal of the first delay unit is respectively connected to the input terminal of the second delay unit and the input terminal of the NOT gate circuit, and the output terminal of the second delay unit is connected to the first input terminal of the second OR gate circuit; the output terminal of the NOT gate circuit is connected to the second input terminal of the second OR gate circuit, the output terminal of the digital control logic circuit is connected to the third input terminal of the second OR gate circuit, the output terminal of the second OR gate circuit is connected to the first input terminal of the third AND gate circuit, and the output terminal of the third AND gate circuit is connected to the sampling clock signal input terminal of the bidirectional shift register.
[0011] Furthermore, the dynamic comparator is a clock-controlled two-input dynamic comparator, including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; wherein, the gate of the second transistor is the positive input terminal of the dynamic comparator and is connected to the terminal output terminal;
[0012] The drain of the ninth transistor is connected to the drains of the fifth transistor and the seventh transistor, and this node is respectively connected to the gates of the sixth transistor and the fourth transistor;
[0013] The drain of the tenth transistor is connected to the drains of the eighth transistor and the sixth transistor, and this node is respectively connected to the gates of the fifth transistor and the third transistor; and this node is the output terminal of the dynamic comparator;
[0014] The source of the seventh transistor is connected to the drain of the third transistor; the source of the eighth transistor is connected to the drain of the fourth transistor;
[0015] The source of the third transistor is connected to the drain of the first transistor; the source of the fourth transistor is connected to the drain of the second transistor;
[0016] The source of the first transistor is connected to the source of the second transistor, and this node is grounded;
[0017] The gate of the first transistor is the negative input terminal of the two-input dynamic comparator and is connected to the reference voltage V REF ; the sources of the ninth transistor, the fifth transistor, the sixth transistor, and the tenth transistor are respectively connected to the operating voltage V of the dynamic comparator DD ;
[0018] The sampling clock signal is respectively connected to the connection node of the gate of the seventh transistor and the gate of the ninth transistor, and the connection node of the gate of the eighth transistor and the gate of the tenth transistor.
[0019] Furthermore, the fifth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are P-type MOS transistors, and the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are N-type MOS transistors.
[0020] Furthermore, the PMOS auxiliary feedforward includes several P-type MOS transistors. The gate of each P-type MOS transistor is connected to the output terminal of the dynamic comparator, and the drain is connected to the drain of the P-type MOS transistor in the PMOS power transistor array.
[0021] Furthermore, the bidirectional shift register is composed of several cascaded shift register units. Each stage of the shift register unit includes a D flip-flop and a two-to-one data selector;
[0022] The input terminal of the D flip-flop in each stage of the shift register unit is connected to the output terminal of the two-to-one data selector. The clock terminal of the D flip-flop is respectively connected to the clock signal and the output terminal of the dynamic comparator;
[0023] The first input terminal of the two-to-one data selector of the first-stage shift register unit is connected to the first fixed-value signal, and the second input terminal of the two-to-one data selector of the last-stage shift register unit is connected to the second fixed-value signal; the first input terminal of the second-stage to the last-stage shift register units is connected to the output terminal of the D flip-flop of the previous-stage shift register unit, and the second input terminal of the first-stage to the penultimate-stage shift register units is connected to the output terminal of the D flip-flop of the next-stage shift register unit;
[0024] The output terminal of the D flip-flop in each stage of the shift register unit is connected to the corresponding PMOS power transistor in the PMOS power transistor array.
[0025] Further, the PMOS power transistor array includes a number of P-type MOS transistors. The gates of each P-type MOS transistor are respectively connected to the output terminals of the corresponding D flip-flops of the bidirectional shift register, and the drains of each P-type MOS transistor are connected to the drains of the corresponding P-type MOS transistors in the PMOS auxiliary feedforward.
[0026] Compared with the prior art, the remarkable effects of the present invention are as follows:
[0027] 1. By adding a digital logic control circuit and a sampling clock conversion logic circuit to change the sampling clock, the circuit structure is simple and the power consumption is reduced.
[0028] 2. By adding a digital logic control circuit and a sampling clock conversion logic circuit to change the sampling clock, a relatively large step size is adjusted at one time, and the response time is shortened.
[0029] 3. By adding a digital logic control circuit and a sampling clock conversion logic circuit to change the sampling clock, the convergence speed of the DLDO is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 is the coarse and fine adjustment control logic circuit of the present invention;
[0031] Figure 2 is a schematic diagram of the structure of the digital logic control circuit of the present invention;
[0032] Figure 3 is a schematic diagram of the structure of the sampling clock conversion circuit of the present invention;
[0033] Figure 4 is a schematic diagram of the structure of the dynamic comparator of the present invention;
[0034] Figure 5 is a schematic diagram of the structure of the bidirectional shift register of the present invention;
[0035] Figure 6 is the clock signal diagram before and after conversion of the present invention;
[0036] Figure 7 is the clock signal diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0037] The present invention will be further described in detail below with reference to the accompanying drawings of the specification and specific embodiments.
[0038] Such as Figure 1As shown in the figure, the thickness adjustment control logic circuit of the present invention includes a dynamic comparator 5, a bidirectional shift register 10, a PMOS power transistor array 15, a PMOS auxiliary feedforward 20, a load capacitor and a load current source 25, a digital logic control circuit 85, and a sampling clock conversion control circuit 90; the dynamic comparator 5 includes a first input terminal, a second input terminal, and an output terminal.
[0039] The output terminal of the bidirectional shift register 10 is connected to the input terminal of the PMOS power transistor array 15, and the output terminal of the PMOS power transistor array 15 is connected to the output terminal of the PMOS auxiliary feedforward 20; the input terminal of the load capacitor and the load current source 25 is grounded, and the output terminals are respectively connected to the PMOS power transistor array 15 as the output terminals of the system; the output terminal of the dynamic comparator 5 is respectively connected to the input terminal of the bidirectional shift register 10, the input terminal of the PMOS auxiliary feedforward 20, and the input terminal of the digital logic control circuit 85; the PMOS power transistor array 15 includes a plurality of P-type MOS transistors, the gate of each P-type MOS transistor is respectively connected to the output terminal of the corresponding D flip-flop of the bidirectional shift register 10, and the drain of each P-type MOS transistor is connected to the drain of the corresponding P-type MOS transistor in the PMOS auxiliary feedforward 20; the PMOS auxiliary feedforward 20 includes a plurality of P-type MOS transistors, the gate of the P-type MOS transistor is connected to the output terminal of the dynamic comparator 5, and the drain is connected to the drain of the P-type MOS transistor in the PMOS power transistor array 15.
[0040] As Figure 2 shown in the figure, the digital logic control circuit 85 includes a first register 30, a second register 35, a first AND gate circuit 40, a second AND gate circuit 45 with inversion, and a first OR gate circuit 50; the first AND gate circuit 40 includes first, second, and third input terminals and an output terminal; the second AND gate circuit 45 includes first, second, and third input terminals and an output terminal; the first OR gate circuit 50 includes first and second input terminals and an output terminal. The input terminal of the first register 30 is connected to the output terminal of the dynamic comparator 5, and the output terminal is connected to the input terminal of the first AND gate circuit 40 and the input terminal of the second AND gate circuit 45. The output terminal of the second register 35 is connected to the input terminal of the first AND gate circuit 40 and the input terminal of the second AND gate circuit 45; the dynamic comparator 5 is also connected to the third input terminal of the first AND gate circuit 40, and the inverted output of the dynamic comparator 5 is connected to the third input terminal of the second AND gate circuit 45. The output terminals of the first AND gate circuit 40 and the second AND gate circuit 45 with inversion are respectively connected to the first input terminal and the second input terminal of the first OR gate circuit 50;
[0041] As Figure 3As shown in the figure, the sampling clock conversion control circuit 90 includes a first delay unit 60, a second delay unit 65, a NOT gate circuit 70, a second OR gate circuit 75, and a third AND gate circuit 80. The NOT gate circuit 70 includes an input terminal and an output terminal. The second OR gate circuit 75 includes first, second, and third input terminals and an output terminal. The third AND gate circuit 80 includes first and second input terminals and an output terminal. The clock signal is connected to the input terminal of the first delay unit 60 and also to the second input terminal of the third AND gate circuit 80. The output terminal of the first delay unit 60 is respectively connected to the input terminal of the second delay unit 65 and the input terminal of the NOT gate circuit 70. The output terminal of the second delay 65 is connected to the first input terminal of the second OR gate circuit 75. The output terminal of the NOT gate circuit 70 is connected to the second input terminal of the second OR gate circuit 75. The output terminal of the digital control logic circuit 85 is connected to the third input terminal of the second OR gate circuit 75. The output terminal of the second OR gate circuit 75 is connected to the first input terminal of the third AND gate circuit 80. The output of the third AND gate circuit 80 is connected to the sampling clock input terminal of the bidirectional shift register 10.
[0042] As Figure 4 shown in the figure, there is a clock-controlled two-input dynamic comparator 5. The dynamic comparator 5 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, and a tenth transistor Q10. Among them, the gate of the second transistor Q2 is connected to the positive input terminal and the terminal output VOUT of the two-input dynamic comparator 5. The drain of the ninth transistor Q9 is respectively connected to the drains of the fifth transistor Q5 and the seventh transistor Q7, and this node is respectively connected to the gates of the sixth transistor Q6 and the fourth transistor Q4. The drain of the tenth transistor Q10 is respectively connected to the drains of the eighth transistor Q8 and the sixth transistor Q6, and this node is respectively connected to the gates of the fifth transistor Q5 and the third transistor Q3, which is the output terminal F of the dynamic comparator, and is connected to the input terminals of the bidirectional shift register 10 and the PMOS auxiliary feedforward 20. The source of the seventh transistor Q7 is connected to the drain of the third transistor Q3. The source of the eighth transistor Q8 is connected to the drain of the fourth transistor Q4. The source of the third transistor Q3 is connected to the drain of the first transistor Q1. The source of the fourth transistor Q4 is connected to the drain of the second transistor Q2. The source of the first transistor Q1 is connected to the source of the second transistor Q2, and this node is grounded. The gate of the first transistor Q1 is connected to the negative input terminal of the two-input dynamic comparator 5 and is connected to the reference voltage VREF. The sources of the ninth transistor Q9, the fifth transistor Q5, the sixth transistor Q6, and the tenth transistor Q10 are connected to the operating voltage VDD of the two-input dynamic comparator 5. The sampling clock signal clk is respectively connected to the connection node between the gate of the seventh transistor Q7 and the gate of the ninth transistor Q9 and the connection node between the gate of the eighth transistor Q8 and the gate of the tenth transistor Q10.
[0043] As Figure 5 , the bidirectional shift register 10 is composed of a plurality of serially connected shift register units. Each stage of the shift register unit includes a D flip-flop and a two-to-one data selector. The input end of the D flip-flop in each stage of the shift register unit is connected to the output end of the two-to-one data selector. The clock end of the D flip-flop in each stage of the shift register unit is connected to the sampling clock signal. The clock end of each stage of the shift register unit is connected to the output end of the two-input dynamic comparator 5. The first input end of the two-to-one data selector of the first stage of the shift register unit is connected to the first fixed value signal. The second input end of the two-to-one data selector of the last stage of the shift register unit is connected to the second fixed value signal. The first input end of the shift register units from the second stage to the last stage is connected to the output end of the D flip-flop of the previous stage of the shift register unit. The second input end of the shift register units from the first stage to the penultimate stage is connected to the output end of the D flip-flop of the next stage of the shift register unit. The output end of the D flip-flop of each stage of the shift register unit is connected to the corresponding PMOS power transistor in the PMOS power transistor array 15.
[0044] As Figure 4 shown, the ninth transistor Q9, the fifth transistor Q5, the sixth transistor Q6, and the tenth transistor Q10 are P-type MOS transistors, and the seventh transistor Q7, the eighth transistor Q8, the third transistor Q3, the fourth transistor Q4, the first transistor Q1, and the second transistor Q2 are N-type MOS transistors.
[0045] The principles of the digital logic control circuit 85 and the sampling clock conversion circuit 90 are as follows:
[0046] Fs is the clock sampling frequency, which provides the clock signal clk for the dynamic comparator 5 and the bidirectional shift register 10. When the clock signal clk arrives, the dynamic comparator 5 and the bidirectional shift register 10 start to work. When the clock signal clk arrives, the output V OUT of the voltage regulator and the reference voltage V REF are compared to monitor the difference between them. When the output V OUT is greater than the reference voltage V REF , the dynamic comparator 5 outputs 1; when the output V OUT is less than the reference voltage V REFWhen the dynamic comparator 5 outputs 0. When the dynamic comparator 5 outputs the first 1, the signal 1 is stored in the first register 30. When it outputs the second 1, the second signal 1 is stored in the second register 35. When it outputs the third 1, the third signal 1 and the previous two signal 1s are simultaneously input into the first AND gate circuit 40, and the first AND gate circuit 40 outputs the signal 1. When the dynamic comparator 5 outputs the first 0, the first signal 0 is stored in the first register 30. When it outputs the second 0, the second signal 0 is stored in the second register 35. When it outputs the third 0, the third signal 0 and the previous two signal 0s are inverted and then simultaneously input into the second AND gate circuit 45, and the second AND gate circuit 45 outputs the signal 1; the signals of the first AND gate circuit 40 and the second AND gate circuit 45 are simultaneously input into the first OR gate circuit 50, and the first OR gate circuit 50 outputs 0 or 1; therefore, when the dynamic comparator 5 continuously outputs 1 three times in a row or is continuously 0, it is determined that the output of the digital logic control circuit is 1; at this time, the output of the digital logic control circuit after taking the inverse is input to the second input terminal of the second OR gate circuit 75 of the sampling clock control logic circuit. Figure 7 In Figure 7 , the clock signal clk passes through the first delay unit 60 and the NOT gate circuit 70 to obtain a signal, and this signal is input into the first input terminal of the second OR gate circuit 75; the clock signal clk passes through the first delay unit 60 and the second delay unit 65 to obtain the clk_dd signal, and this clk_dd signal is input into the first input terminal of the second OR gate circuit 75; the output signal of the digital logic control circuit after taking the inverse is input into the third input terminal of the second OR gate circuit 75. At this time, the second OR gate circuit 75 outputs Figure 7 the signal in Figure 7 . This signal is input into the first input terminal of the third AND gate circuit 80; the clk signal is input into the second input terminal of the third AND gate circuit 80. The third AND gate circuit 80 outputs Figure 6 the F S signal in Figure 6 through the logic clk&(p + clk_d + clk_dd). In this way, when it is detected that the comparator output is continuously 1 three times in a row or continuously 0, it is determined that the output of the digital logic control circuit is P = 1. When the output of the digital logic control circuit is 1, the sampling clock conversion circuit changes the single rising edge of each cycle of the clock of the bidirectional shift register 10 to a double rising edge to control F S to achieve coarse adjustment; when P = 0, the sampling clock conversion circuit still maintains the original F S to achieve fine adjustment.
[0047] After one clock cycle, the output of the dynamic comparator 5 is fed to the bidirectional shift register 10. Through the characteristic of serial input and parallel output, the output of the bidirectional shift register 10 becomes several, so as to control the number of PMOS power transistors in the PMOS power transistor array 15 to be turned on.
[0048] In the above specific embodiments, the purpose, technical solution and beneficial effects of the present invention have been further described in detail. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A coarse and fine adjustment control logic circuit for a digital low dropout regulator, characterized in that, It includes a dynamic comparator (5), a bidirectional shift register (10), a PMOS power transistor array (15), a PMOS auxiliary feedforward (20), a load capacitor and a load current source (25), a digital logic control circuit (85), and a sampling clock conversion control circuit (90); The output end of the bidirectional shift register (10) is connected to the input end of the PMOS power transistor array (15), and the output end of the PMOS power transistor array (15) is connected to the output end of the PMOS auxiliary feedforward (20); The input ends of the load capacitor and the load current source (25) are grounded, and the output ends are connected to the PMOS power transistor array (15) and serve as the terminal output end (V OUT ) of the entire circuit; The dynamic comparator (5) includes a first input end, a second input end, and an output end. The output end is respectively connected to the input end of the bidirectional shift register (10), the input end of the PMOS auxiliary feedforward (20), and the input end of the digital logic control circuit (85); The digital logic control circuit (85) includes a first register (30), a second register (35), a first AND gate circuit (40), a second AND gate circuit (45) with inversion, and a first OR gate circuit (50); The input end of the first register (30) is connected to the output end of the dynamic comparator (5), and the output end is connected to the input end of the first AND gate circuit (40) and the input end of the second AND gate circuit (45) with inversion; The input end of the second register (35) is connected to the input end of the first AND gate circuit (40) and the input end of the second AND gate circuit (45) with inversion; The output end of the dynamic comparator (5) is connected to the third input end of the first AND gate circuit (40), and at the same time, the output end of the dynamic comparator (5) after inversion is connected to the third input end of the second AND gate circuit (45); The output end of the first AND gate circuit (40) and the output end of the second AND gate circuit (45) with inversion are respectively connected to the first input end and the second input end of the first OR gate circuit (50); The sampling clock conversion control circuit (90) includes a first delay unit (60), a second delay unit (65), a NOT gate circuit (70), a second OR gate circuit (75), and a third AND gate circuit (80); The clock signal is respectively connected to the input end of the first delay unit (60) and the second input end of the third AND gate circuit (80); The output end of the first delay unit (60) is respectively connected to the input end of the second delay unit (65) and the input end of the NOT gate circuit (70), and the output end of the second delay unit (65) is connected to the first input end of the second OR gate circuit (75); The output end of the NOT gate circuit (70) is connected to the second input end of the second OR gate circuit (75), the output end of the digital control logic circuit (85) is connected to the third input end of the second OR gate circuit (75), the output end of the second OR gate circuit (75) is connected to the first input end of the third AND gate circuit (80), and the output end of the third AND gate circuit (80) is connected to the sampling clock signal input end of the bidirectional shift register (10).
2. The fine and coarse adjustment control logic circuit for a digital low dropout regulator according to claim 1, wherein The dynamic comparator (5) is a clock-controlled two-input dynamic comparator, including a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), a sixth transistor (Q6), a seventh transistor (Q7), an eighth transistor (Q8), a ninth transistor (Q9), and a tenth transistor (Q10); wherein, the gate of the second transistor (Q2) is the positive input terminal of the dynamic comparator (5) and is connected to the terminal output terminal (V OUT ); The drain of the ninth transistor (Q9) is connected to the drains of the fifth transistor (Q5) and the seventh transistor (Q7), and this node is respectively connected to the gates of the sixth transistor (Q6) and the fourth transistor (Q4); The drain of the tenth transistor (Q10) is connected to the drains of the eighth transistor (Q8) and the sixth transistor (Q6), and this node is respectively connected to the gates of the fifth transistor (Q5) and the third transistor (Q3); and this node is the output terminal (F) of the dynamic comparator. The source of the seventh transistor (Q7) is connected to the drain of the third transistor (Q3); the source of the eighth transistor (Q8) is connected to the drain of the fourth transistor (Q4). The source of the third transistor (Q3) is connected to the drain of the first transistor (Q1); the source of the fourth transistor (Q4) is connected to the drain of the second transistor (Q2). The sources of the first transistor (Q1) and the second transistor (Q2) are connected, and this node is grounded. The gate of the first transistor (Q1) is the negative input terminal of a two-input dynamic comparator and is connected to the reference voltage V REF ; The sources of the ninth transistor (Q9), the fifth transistor (Q5), the sixth transistor (Q6), and the tenth transistor (Q10) are respectively connected to the operating voltage V of the dynamic comparator DD ; The sampling clock signal is connected to the connection node between the gates of the seventh transistor (Q7) and the ninth transistor (Q9), and the connection node between the gates of the eighth transistor (Q8) and the tenth transistor (Q10).
3. The fine and coarse adjustment control logic circuit for a digital low dropout regulator according to claim 2, wherein The fifth transistor (Q5), the sixth transistor (Q6), the ninth transistor (Q9), and the tenth transistor (Q10) are P-type MOS transistors, and the first transistor (Q1), the second transistor (Q2), the third transistor (Q3), the fourth transistor (Q4), the seventh transistor (Q7), and the eighth transistor (Q8) are N-type MOS transistors.
4. The coarse and fine adjustment control logic circuit for a digital low dropout regulator according to claim 1, wherein The PMOS auxiliary feedforward (20) includes several P-type MOS transistors, and the gates of each P-type MOS transistor are all connected to the output terminal of the dynamic comparator (5), and the drains are all connected to the drains of the P-type MOS transistors in the PMOS power transistor array (15).
5. The fine and coarse adjustment control logic circuit for a digital low dropout regulator according to claim 1, wherein The bidirectional shift register (10) is composed of several serially connected shift register units, and each stage of the shift register unit includes a D flip-flop and a multiplexer. The input terminal of the D flip-flop in each stage of the shift register unit is connected to the output terminal of the multiplexer, and the clock terminals of the D flip-flop are respectively connected to the clock signal and the output terminal of the dynamic comparator (5). The first input terminal of the multiplexer of the first-stage shift register unit is connected to the first fixed-value signal, and the second input terminal of the multiplexer of the last-stage shift register unit is connected to the second fixed-value signal; the first input terminals of the second-stage to the last-stage shift register units are connected to the output terminals of the D flip-flops of the previous-stage shift register units, and the second input terminals of the first-stage to the second-last-stage shift register units are connected to the output terminals of the D flip-flops of the next-stage shift register units. The output terminal of the D flip-flop in each stage of the shift register unit is connected to the corresponding PMOS power transistor in the PMOS power transistor array (15).
6. The fine and coarse adjustment control logic circuit for a digital low dropout regulator according to claim 1, characterized in that, The PMOS power transistor array (15) includes several P-type MOS transistors, the gates of each P-type MOS transistor are respectively connected to the output terminals of the corresponding D flip-flops of the bidirectional shift register (10), and the drains of each P-type MOS transistor are connected to the drains of the corresponding P-type MOS transistors in the PMOS auxiliary feedforward (20).
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