Control system and control method for controlling a storage device
By detecting and latching the status signals of abnormal read and write operations, and then disabling and restarting the storage device, the problem of data security of the storage device is solved, and the effectiveness of information protection is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WIWYNN CORP
- Filing Date
- 2021-10-09
- Publication Date
- 2026-06-26
AI Technical Summary
Existing storage devices are not secure enough to prevent abnormal read/write operations, increasing the risk of information leakage.
The system and methods detect abnormal read/write operations, generate and latch a first state signal, disable the storage device that is experiencing abnormal read/write operations, and restart the disabled storage device via a restart input module.
It improves the security of data in storage devices and prevents information leakage caused by abnormal read and write operations.
Smart Images
Figure CN115934591B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a control system and a control method, and more particularly to a control system and a control method for a storage device. Background Technology
[0002] In this era of information overload, important data stored on storage devices often becomes a target for malicious actors (such as hackers). As these malicious actors become increasingly sophisticated, the development of new data protection mechanisms is essential to enhance information security and improve the protection of data stored on storage devices. Summary of the Invention
[0003] The present invention provides a control system and control method for a storage device, which can improve the security of data stored in the storage device.
[0004] An embodiment of the present invention provides a control system for controlling at least one storage device. The control system includes a host, a first controller, a judgment circuit, a second controller, and a restart input module. The host generates an exception signal in response to an abnormal read / write operation being performed on the at least one storage device. The first controller is coupled to the host. The first controller provides a first setting signal in response to the exception signal. The judgment circuit is coupled to the first controller. The judgment circuit generates and latches a first state signal having a first logic value in response to the first setting signal. The judgment circuit provides a first control signal in response to the first state signal having the first logic value. The second controller is coupled to the judgment circuit and the at least one storage device. The second controller disables the at least one storage device from which the abnormal read / write operation was performed in response to the first control signal. The restart input module is coupled to the judgment circuit. The restart input module changes the first logic value of the first state signal latched in the judgment circuit to a second logic value, causing the judgment circuit to provide a second control signal in response to the first state signal having the second logic value. The second controller restarts the at least one storage device from which the abnormal read / write operation was performed in response to the second control signal.
[0005] An embodiment of the present invention provides a control method for controlling at least one storage device. The control method includes: detecting that the at least one storage device has undergone an abnormal read / write operation and generating an abnormal signal accordingly; providing a first setting signal in response to the abnormal signal via a first controller; generating and latching a first state signal having a first logic value via a judgment circuit in response to the first setting signal; providing a first control signal in response to the first state signal having the first logic value; disabling the at least one storage device undergoing the abnormal read / write operation via a second controller in response to the first control signal; operating a restart input module to change the first logic value of the first state signal latched in the judgment circuit to a second logic value; causing the judgment circuit to provide a second control signal in response to the first state signal having the second logic value; and restarting the at least one storage device undergoing the abnormal read / write operation via the second controller in response to the second control signal.
[0006] Based on the above, when an abnormal read / write operation is detected on the storage device, the control system and control method generate a first state signal with a first logic value and latch the first state signal, thereby deactivating the storage device from which the abnormal read / write operation was performed. The restart input module is then operated to change the first logic value of the first state signal latched in the judgment circuit to a second logic value, thereby restarting the storage device from which the abnormal read / write operation was performed. In other words, when an abnormal read / write operation is detected on the storage device, the control system and control method deactivate the storage device from which the abnormal read / write operation was performed based on the latched first logic value until the restart input module is operated. In this way, the security of the data stored in the storage device can be improved.
[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of a control system according to an embodiment of the present invention.
[0009] Figure 2 This is a flowchart illustrating a control method according to an embodiment of the present invention.
[0010] Figure 3 This is a schematic diagram of a control system according to an embodiment of the present invention.
[0011] Figure 4 This is a schematic diagram of a control system according to an embodiment of the present invention.
[0012] Figure 5 This is a schematic diagram of a control system according to an embodiment of the present invention. Detailed Implementation
[0013] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered identical or similar when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.
[0014] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a control system according to an embodiment of the present invention. In one embodiment, the control system 100 is used to control the storage device 200. The storage devices SD1 to SD4 may be non-volatile storage devices. The control system 100 includes a host 110, a first controller 120, a determination circuit 130, a second controller 140, and a restart input module 150. The host 110 generates an exception signal SAB in response to at least one of the storage devices SD1 to SD4 being subjected to an abnormal read / write operation. The first controller 120 is coupled to the host 110. The first controller 120 provides a first setting signal ST1 in response to the exception signal SAB. The determination circuit 130 is coupled to the first controller 120. The determination circuit 130 generates a first status signal SS1 having a first logic value in response to the first setting signal ST1. The determination circuit 130 also latches the first status signal SS1. That is, when it is determined that at least one of the storage devices SD1 to SD4 has been subjected to an abnormal read / write operation, the determination circuit 130 latches the first status signal SS1 having the first logic value. In addition, the determination circuit 130 also responds to the first state signal SS1 having a first logic value to provide a first control signal SC1.
[0015] The second controller 140 is coupled to the judgment circuit 130 and the storage devices SD1 to SD4. The second controller 140 responds to the first control signal SC1 to disable the storage device among the storage devices SD1 to SD4 that has been subjected to abnormal read / write operations.
[0016] In one embodiment, a restart input module 150 is coupled to a determination circuit 130. The restart input module 150 is operated to change the first logic value of a first state signal SS1 latched in the determination circuit 130 to a second logic value. The determination circuit 130 responds to the first state signal SS1 having the second logic value to provide a second control signal SC2. In one embodiment, the restart input module 150 may be one of a physical button, a physical push button, and a physical switch. The second controller 140 responds to the second control signal SC2 to restart the storage devices SD1-SD4 that have undergone abnormal read / write operations.
[0017] In one embodiment, when an abnormal read / write operation is detected on at least one of the storage devices SD1 to SD4, the control system 100 generates a first status signal SS1 with a first logic value and latches the first status signal SS1, thereby deactivating the storage device on which the abnormal read / write operation was performed. The restart input module 150 is operated (e.g., pressed or clicked) to change the first logic value of the first status signal SS1 latched in the judgment circuit to a second logic value, thereby restarting the deactivated storage device. In other words, when an abnormal read / write operation is detected on a storage device, the control system 100 continuously deactivates the storage device on which the abnormal read / write operation was performed based on the first logic value of the latched first status signal SS1 until an operator physically operates the restart input module 150 on-site. In this way, the security of the data stored on the storage devices SD1 to SD4 can be improved.
[0018] In one embodiment, the first controller 120, the judgment circuit 130, the second controller 140, and the storage devices SD1 to SD4 can be integrated into a single server. In one embodiment, the restart input module 150 can be located on the server or in the server rack. In one embodiment, the host 110 can be a background monitoring device or a monitoring device located on the server.
[0019] For ease of explanation, this embodiment uses four storage devices SD1 to SD4 as an example. The number of storage devices in this invention can be one or more, and is not limited to this embodiment.
[0020] In some embodiments, when at least one of the storage devices SD1 to SD4 is detected to have performed an abnormal read / write operation, all storage devices SD1 to SD4 are continuously disabled based on a latched first logic value.
[0021] To further illustrate the implementation of the host 110's detection of abnormal read / write operations, consider the following example: A trap file is loaded into storage devices SD1 to SD4. The trap file can be stored in a specific folder. When the trap file stored on storage device SD1 is used (e.g., copied, modified, moved, or deleted), the host 110 determines that abnormal read / write operations have been performed on storage device SD1.
[0022] For example, the data transfer rate of storage devices SD1 to SD4 is limited within a specific time interval. When the data transfer rate of storage device SD2 exceeds the traffic threshold within the specific time interval, host 110 determines that storage device SD1 has been subjected to abnormal read / write operations. Similarly, when the data transfer rate of storage device SD2 exceeds the traffic threshold within the specific time interval, host 110 determines that storage device SD2 has been subjected to abnormal read / write operations. Furthermore, if storage device SD2 is subjected to unexpected formatting, host 110 determines that storage device SD2 has been subjected to abnormal read / write operations.
[0023] For example, a password may be set. When data on storage devices SD1 to SD4 is about to be used, the control system 100 will prompt the user to enter a password. The host 110 will determine whether an abnormal read / write operation has occurred based on the number of consecutive incorrect password entries. When the number of consecutive incorrect password entries exceeds a threshold, the host 110 will determine that an abnormal read / write operation has been performed on storage devices SD1 to SD4 based on the number of consecutive incorrect password entries.
[0024] Please also refer to Figure 1 as well as Figure 2 , Figure 2 This is a flowchart illustrating a control method according to an embodiment of the present invention. In step S101, storage devices SD1 to SD4 are detected. In step S102, it is determined whether storage devices SD1 to SD4 have been subjected to an abnormal read / write operation. In step S102, if none of the storage devices SD1 to SD4 have been found to have been subjected to an abnormal read / write operation, the control method returns to step S101. That is, if no abnormal read / write operation occurs, the control method executes steps S101 and S102 in a loop. On the other hand, when at least one of the storage devices SD1 to SD4 is found to have been subjected to an abnormal read / write operation, an exception signal SAB is generated. Furthermore, the control method proceeds to step S103.
[0025] In step S103, a first state signal SS1 with a first logic value is generated. Furthermore, the first state signal SS1 is latched. In step S104, the logic value of the first state signal SS1 is determined. When the logic value of the first state signal SS1 is the first logic value, the control method proceeds to step S105 to disable the storage devices SD1 to SD4 that have undergone abnormal read / write operations.
[0026] In step S106, it is determined whether the restart input module 150 has been operated. When the restart input module 150 has not been operated, the control method returns to step S104. That is, when the logic value of the first state signal SS1 is the first logic value and the restart input module 150 has not been operated, the control method executes steps S104 to S106 in a loop. On the other hand, when the restart input module 150 is operated, the first logic value of the latched first state signal SS1 is changed to the second logic value in step S107. Then, the control method returns to step S104.
[0027] In step S104, when the logic value of the first status signal SS1 is the second logic value, the storage device subjected to the abnormal read / write operation is enabled in step S108. The control method returns to step S101.
[0028] In one embodiment, steps S101 and S102 can be executed by the host 110. In one embodiment, step S103 can be executed by the coordinated operation of the first controller 120 and the judgment circuit 130. In one embodiment, steps S104 to S108 can be executed by the coordinated operation of the judgment circuit 130 and the second controller 140. The implementation details of the host 110, the first controller 120, the judgment circuit 130, and the second controller 140 can be provided by [the relevant documentation / organization]. Figure 1 Sufficient teaching has been obtained from the embodiments, and therefore will not be repeated here.
[0029] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a control system according to an embodiment of the present invention. In one embodiment, the control system 200 includes a host 210, a first controller 220, a judgment circuit 230, a second controller 240, and a restart input module 250. The host 210 generates an exception signal SAB in response to at least one of the storage devices SD1 to SD4 being subjected to an abnormal read / write operation.
[0030] When the abnormal signal SAB is not generated, the first controller 220 provides a first setting signal ST1 with a first logic value and a second setting signal ST2 with a second logic value. The first logic value is a low logic value (i.e., logic 0). The second logic value is a high logic value (i.e., logic 1). On the other hand, when the abnormal signal SAB is generated, the first controller 220 responds to the abnormal signal SAB by providing the first setting signal ST1 with the second logic value and the second setting signal ST2 with the first logic value.
[0031] In one embodiment, the restart input module 250 generates an operation signal SO with a first logic value when it is not operated. When the restart input module 250 is operated, it generates an operation signal SO with a second logic value. The determination circuit 230 provides a first status signal SS1 with a first logic value and a second status signal SS2 with a second logic value in response to the first setting signal ST1 and the operation signal SO with the first logic value. Alternatively, the determination circuit 230 provides a first status signal SS1 with a second logic value and a second status signal SS2 with a second logic value in response to the operation signal SO with the second logic value. The first controller 220 provides a second setting signal ST2 with a second logic value in response to the second status signal SS2 with the first logic value. In one embodiment, when the restart input module 250 is operated, the first controller 220 is triggered in response to the second status signal SS2 with the first logic value, thereby resetting the second logic value of the first setting signal ST1 back to the first logic value and resetting the first logic value of the second setting signal ST2 back to the second logic value. In some embodiments, the first controller 220 is triggered in response to the falling edge of the second state signal SS2 to reset the logic value of the first setting signal ST1 and the logic value of the second setting signal ST2.
[0032] Further, the determination circuit 230 includes a latch LT and a logic circuit 231. The latch LT latches a first state signal SS1. The logic circuit 231 responds to the first state signal SS1 latched in the latch LT and a second setting signal ST2 to provide a first control signal SC1. In one embodiment, the logic circuit 231 includes a switching circuit SW, a flip-flop FF, and an AND gate AG. The first input of the switching circuit SW is coupled to the first controller 220. The first input of the switching circuit SW receives the first setting signal ST1. The second input of the switching circuit SW is coupled to a reference low voltage (e.g., ground). The control terminal of the switching circuit SW receives an operation signal SO. The setting terminal S of the flip-flop FF receives the operation signal SO. The reset terminal R of the flip-flop FF is coupled to the output terminal of the switching circuit SW. The output terminal Q of the flip-flop FF is coupled to the latch LT. The inverted output terminal QB of the flip-flop FF is coupled to the first controller 220. The flip-flop FF may be implemented by an RS flip-flop.
[0033] In one embodiment, the switching circuit SW responds to the operation signal SO having a first logic value to switch the reset terminal R of the flip-flop to the first controller 220. The switching circuit SW responds to the operation signal SO having a second logic value to switch the reset terminal R of the flip-flop to the reference low voltage. Therefore, the truth table provided by the first setting signal ST1, the operation signal SO, and the flip-flop FF is shown in Table 1.
[0034] Table 1:
[0035]
[0036]
[0037] Table 1 shows four possible states in one embodiment. In state 1, no abnormal read / write operation is performed on storage devices SD1 to SD4. The logic value of the first setting signal ST1 is logic 0. The restart input module 250 is not operated. The logic value of the operation signal SO is logic 0. That is, the logic value of the first setting signal ST1 is the same as the logic value of the operation signal SO. Therefore, the logic value of the reset terminal R and the logic value of the setting terminal S are both logic 0. The logic value of the first state signal SS1 will remain the previous logic value. The logic value of the second state signal SS2 will remain the previous logic value.
[0038] In state 2, storage devices SD1 to SD4 are not subjected to any abnormal read / write operations. The logic value of the first setting signal ST1 is logic 0. The restart input module 250 is operated. The logic value of the operation signal SO is logic 1. The logic value of the first setting signal ST1 is different from the logic value of the operation signal SO. Therefore, the logic value of the reset terminal R is logic 0. The logic value of the setting terminal S is logic 1. The logic value of the first status signal SS1 is logic 1. The logic value of the second status signal SS2 is logic 0. Based on the above, when storage devices SD1 to SD4 are not subjected to any abnormal read / write operations, the operation of the restart input module 250 does not affect the logic values of the first status signal SS1 and the second status signal SS2. Storage devices SD1 to SD4 can operate normally.
[0039] In state 3, at least one of the storage devices SD1 to SD4 is subjected to an abnormal read / write operation. The logic value of the first setting signal ST1 is logic 1. The restart input module 250 is not operated. The logic value of the operation signal SO is logic 0. The logic value of the first setting signal ST1 is different from the logic value of the operation signal SO. Therefore, the logic value of the reset terminal R is logic 1. The logic value of the setting terminal S is logic 0. The logic value of the first status signal SS1 is logic 0. The logic value of the second status signal SS2 is logic 1. Therefore, the storage device subjected to the abnormal read / write operation is deactivated. That is, when the first setting signal ST1 with a second logic value (i.e., logic 1) is provided, the flip-flop FF responds to the first setting signal ST1 and the operation signal SO with a first logic value (i.e., logic 0). Therefore, the output terminal Q of the flip-flop FF provides the first status signal SS1 with a first logic value (i.e., logic 0), and causes the inverting output terminal of the flip-flop FF to provide the second status signal SS2 with a second logic value (i.e., logic 1).
[0040] In state 4, at least one of the storage devices SD1 to SD4 is subjected to an abnormal read / write operation. The logic value of the first setting signal ST1 is logic 1. The restart input module 250 is operated. The logic value of the operation signal SO is logic 1. The logic value of the first setting signal ST1 is the same as the logic value of the operation signal SO. Therefore, the logic value of the reset terminal R is logic 0. The logic value of the setting terminal S is logic 1. The logic value of the first status signal SS1 is logic 1. The logic value of the second status signal SS2 is logic 0. Therefore, the storage device subjected to the abnormal read / write operation is enabled. Furthermore, the logic value of the first setting signal ST1 is reset back to logic 0. That is, the flip-flop FF responds to the operation signal SO with a second logic value (i.e., logic 1) and a reference low voltage to provide the first status signal SS1 with a second logic value (i.e., logic 1) at the output of the flip-flop FF, and to provide the second status signal SS2 with a first logic value (i.e., logic 0) at the inverted output of the flip-flop FF.
[0041] In one embodiment, the first input of the AND gate AG is coupled to the first controller 220 to receive a second setting signal ST2. The second input of the AND gate AG is coupled to the latch LT to receive a first status signal SS1. The output of the AND gate AG is coupled to the first controller 220. The truth table provided by the second setting signal ST2, the first status signal SS1, and the AND gate AG is shown in Table 2.
[0042] Table 2:
[0043] state ST2 SS1 The output of AND gate AG State A 1 1 1 (Second control signal SC2) State B 0 1 0 (First control signal SC1) State C 0 0 0 (First control signal SC1) State D 1 0 0 (First control signal SC1)
[0044] State A is the normal state. That is, the initial logic value of the first state signal SS1 is logic 1. The initial logic value of the second setting signal ST2 is logic 1. In other words, the initial logic value of the first state signal SS1 is the same as the initial logic value of the second setting signal ST2. Therefore, the AND gate AG performs a logical AND operation on the first state signal SS1 and the second setting signal ST2 to provide a second control signal SC2 with a second logic value. At this time, the logic value of the second control signal SC2 is the same as the initial logic value of both the first state signal SS1 and the second setting signal ST2. In other words, the judgment circuit 230 responds to the second setting signal ST2 with a second logic value and the first state signal SS1 with a second logic value to provide the second control signal SC2. Therefore, the second controller 240 responds to the second control signal SC2 to drive the storage devices SD1 to SD4.
[0045] In state B, at least one of the storage devices SD1 to SD4 is subjected to an abnormal read / write operation. The logic value of the second setting signal ST2 is changed to logic 0. Next, the logic value of the first state signal SS1 is changed to logic 0 in state C. Therefore, in states B and C, the AND gate AG performs a logical AND operation on the first state signal SS1 and the second setting signal ST2 to provide a first control signal SC1. That is, the judgment circuit 230 responds to at least one of the second setting signal ST2 having a first logic value and the first state signal SS1 having a first logic value to provide a first control signal SC1 having a first logic value. The second controller 240 responds to the first control signal SC1 to disable the storage device subjected to the abnormal read / write operation.
[0046] In states B and C, when the restart input module 250 is operated, the logic value of the first state signal SS1 is changed to logic 1. The logic value of the second setting signal ST2 is also changed to logic 1. The judgment circuit 230 provides the second control signal SC2. Therefore, the second controller 240 responds to the second control signal SC2 to enable the disabled storage device (i.e., the storage device that was previously subjected to an abnormal read / write operation).
[0047] In state D, the first controller 220 may be maliciously modified, causing the logic value of the second setting signal ST2 to be changed to logic 1. However, the logic 0 of the first state signal SS1 is latched. Therefore, the AND gate AG still provides the first control signal SC1. It is worth mentioning that, based on the configuration of the judgment circuit 230, operating the restart input module 250 is the only way to change the logic 0 of the latched first state signal SS1 to logic 1. In this way, malicious actors cannot remotely control the memory device that has been subjected to abnormal read / write operations.
[0048] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a control system according to an embodiment of the present invention. In one embodiment, the control system 300 includes a host 310, a first controller 320, a judgment circuit 330, a second controller 340, a restart input module 350, and a power supply unit 360. In one embodiment, the implementation details of the host 310, the first controller 320, the judgment circuit 330, and the restart input module 350 can be found later. Figure 3Sufficient teaching has been obtained from the embodiments, and therefore will not be repeated here. In one embodiment, the power supply unit 360 is coupled to the decision circuit 330 and the second controller 340. The power supply unit 360 responds to the first control signal SC1 to stop the second controller 340 from receiving power PWR. Therefore, the second controller 340 cannot use the power PWR to drive the storage devices SD1 to SD4. On the other hand, the power supply unit 360 responds to the second control signal SC2 to allow the second controller 340 to receive power PWR. Therefore, the second controller 340 can use the power PWR to drive the storage devices SD1 to SD4. The power supply unit 360 is implemented, for example, by a switching circuit.
[0049] In some embodiments, the second controller 340 may be driven based on the power supply PWR. Therefore, when the first control signal SC1 is provided, the storage devices SD1 to SD4 and the second controller 340 are all deactivated.
[0050] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a control system according to an embodiment of the present invention. In one embodiment, the control system 400 includes a host 410, a first controller 420, judgment circuits 430_1 and 430_2, a second controller 440_1 and 440_2, a restart input module 450_1 and 450_2, and power supply units 460_1 and 460_2. The judgment circuit 430_1, the second controller 440_1, the restart input module 450_1, and the power supply unit 460_1 are configured as a first control group to control storage devices SD1 and SD2. The judgment circuit 430_2, the second controller 440_2, the restart input module 450_2, and the power supply unit 460_2 are configured as a second control group to control storage devices SD3 and SD4.
[0051] The implementation methods for the first control group and / or the second control group can be described by... Figure 3 as well as Figure 4 Sufficient teaching has been obtained from the embodiments described above. Therefore, it will not be repeated here.
[0052] The control system of the present invention may include multiple control groups, and is not limited to the first control group and the second control group of the embodiments of the present invention. The number of storage devices corresponding to the control groups of the embodiments of the present invention may be one or more, and is not limited to this embodiment.
[0053] In one embodiment, for example, when storage devices SD1 and SD2 are subjected to the abnormal read / write operation, the control system 400 may only disable storage devices SD1 and SD2. Storage devices SD3 and SD4 may continue to operate.
[0054] Based on actual usage requirements, the control system 400 can expand the number of control groups without adding the host 410 and the first controller 420. Therefore, the control system 400 can be used to control more storage devices.
[0055] In some embodiments, at least one of the first control group and the second control group may be provided by, for example Figure 3 The judgment circuit 230, the second controller 240, and the restart input module 250 are used to achieve this.
[0056] In summary, when an abnormal read / write operation is detected on the storage device, the control system and control method generate a first state signal with a first logic value and latch the first state signal, thereby deactivating the storage device from which the abnormal read / write operation was performed. The storage device can only be reactivated when the restart input module is activated. In this way, the security of the data stored on the storage device can be improved.
[0057] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A control system for controlling at least one storage device, comprising: A host is configured to generate an exception signal in response to an abnormal read / write operation being performed on the at least one storage device; A first controller, coupled to the host, is configured to respond to the abnormal signal to provide a first setting signal; A determination circuit, coupled to the first controller, is configured to respond to the first setting signal to generate a first state signal having a first logic value and latch the first state signal, wherein the determination circuit responds to the first state signal having the first logic value to provide a first control signal; A second controller, coupled to the judgment circuit and the at least one storage device, is configured to respond to the first control signal to disable the at least one storage device from which the abnormal read / write operation is performed; as well as A restart input module, coupled to the judgment circuit, is configured to change the first logic value of the first state signal latched in the judgment circuit to a second logic value, so that the judgment circuit responds to the first state signal having the second logic value to provide a second control signal. The second controller responds to the second control signal to restart the at least one storage device that was subjected to the abnormal read / write operation.
2. The control system as described in claim 1, wherein the restart input module is one of a physical button, a physical button, and a physical switch.
3. The control system of claim 1, wherein the first controller responds to the abnormal signal to provide a second setting signal having the first logic value, wherein the determination circuit includes: A latch, configured to latch the first state signal; as well as A logic circuit configured to provide the first control signal in response to the first state signal and the second setting signal.
4. The control system as described in claim 3, wherein: This logic circuit contains an AND gate. The first logic value is a low logic value. The second logic value is a high logic value, and The logic circuit responds to at least one of the first state signal having the first logic value and the second setting signal having the first logic value to provide the first control signal having the first logic value.
5. The control system as described in claim 3, wherein: The restart input module generates an operation signal with the first logic value when it is not operated. When the restart input module is operated, it generates an operation signal with the second logic value, and The determination circuit responds to the first setting signal and the operation signal having the first logic value to provide the first state signal having the first logic value.
6. The control system as described in claim 5, wherein: The determination circuit responds to the operation signal having the second logic value by providing the first state signal having the second logic value and providing a second state signal having the first logic value. The first controller responds to the second status signal having the first logic value to provide the second setting signal having the second logic value.
7. The control system of claim 6, wherein the determining circuit further comprises: A switching circuit, wherein a first input terminal of the switching circuit is coupled to the first controller, a second input terminal of the switching circuit is coupled to a reference low voltage, and a control terminal of the switching circuit receives the operation signal; as well as A trigger, wherein a set terminal of the trigger receives the operation signal, a reset terminal of the trigger is coupled to an output terminal of the switching circuit, an output terminal of the trigger is coupled to the latch, and an inverted output terminal of the trigger is coupled to the first controller.
8. The control system as claimed in claim 7, wherein: The switching circuit responds to the operation signal having the first logic value to switch the reset terminal of the flip-flop to the first controller. The first setting signal has the second logic value, and When the first setting signal is provided, the flip-flop responds to the first setting signal and the operation signal having the first logic value to make the output of the flip-flop provide the first state signal having the first logic value, and makes the inverted output of the flip-flop provide the second state signal having the second logic value.
9. The control system as claimed in claim 7, wherein: The switching circuit responds to the operation signal having the second logic value to switch the reset terminal of the flip-flop to the reference low voltage. The flip-flop responds to the operation signal having the second logic value and the reference low voltage to cause the output of the flip-flop to provide the first state signal having the second logic value, and causes the inverted output of the flip-flop to provide the second state signal having the first logic value. The first controller responds to the second status signal having the first logic value to provide the second setting signal having the second logic value.
10. The control system of claim 9, wherein the determination circuit responds to the second setting signal having the second logic value and the first state signal having the second logic value to provide the second control signal.
11. The control system of claim 1, further comprising: A power supply unit, coupled to the determination circuit and the second controller, is configured to stop receiving a power supply in response to the first control signal and to receive the power supply in response to the second control signal.
12. A control method for controlling at least one storage device, comprising: An abnormal read / write operation is detected in at least one storage device, and an abnormal signal is generated accordingly. A first setting signal is provided by a first controller in response to the abnormal signal; A judgment circuit responds to the first setting signal to generate a first state signal having a first logic value and latches the first state signal. In response to the first state signal having the first logic value, a first control signal is provided; A second controller responds to the first control signal to disable the at least one storage device from which the abnormal read / write operation was performed; An operation is performed on a restart input module to change the first logic value of the first state signal latched in the judgment circuit to a second logic value; The determination circuit responds to the first state signal having the second logic value to provide a second control signal; as well as The second controller responds to the second control signal to restart the at least one storage device that was subjected to the abnormal read / write operation.
13. The control method as described in claim 12, wherein the restart input module is one of a physical button, a physical button, and a physical switch.
14. The control method as described in claim 12, further comprising: The first controller responds to the abnormal signal by providing a second setting signal having the first logic value.
15. The control method of claim 14, wherein the determination circuit includes a latch and a logic circuit, wherein the step of providing the first control signal in response to the first state signal having the first logic value includes: The first state signal is latched by the latch; as well as The logic circuit responds to the first state signal and the second setting signal having the first logic value to provide the first control signal.
16. The control method of claim 15, wherein the logic circuit includes an AND gate, the first logic value is a low logic value, and the second logic value is a high logic value, wherein the step of providing the first control signal by means of the logic circuit in response to the first state signal and the second setting signal having the first logic value includes: The logic circuit responds to the first state signal having the first logic value and the second setting signal having the first logic value to provide the first control signal having the first logic value.
17. The control method of claim 15, wherein the restart input module generates an operation signal having the first logic value when not operated, wherein the restart input module generates the operation signal having the second logic value when operated, wherein the step of generating the first state signal having the first logic value by the determination circuit responding to the first setting signal includes: The determination circuit responds to the first setting signal and the operation signal having the first logic value to provide the first state signal having the first logic value.
18. The control method of claim 17, wherein the step of causing the determination circuit to respond to the first state signal having the second logic value to provide the second control signal comprises: The determination circuit responds to the operation signal having the second logic value to provide the first state signal having the second logic value and to provide a second state signal having the first logic value.
19. The control method of claim 18, wherein the step of causing the determination circuit to respond to the first state signal having the second logic value to provide the second control signal further comprises: The first controller responds to the second status signal having the first logic value to provide the second setting signal having the second logic value; as well as The determination circuit responds to the second setting signal having the second logic value and the first status signal having the second logic value to provide the second control signal.
20. The control method of claim 12, further comprising: In response to the first control signal, the second controller is made to stop receiving a power supply; as well as In response to the second control signal, the second controller receives the power.