Power consumption analysis method, device, electronic device, storage medium

Abstract

A power consumption analysis method, device, electronic device, and storage medium. The power consumption analysis method includes: obtaining the input stimulus corresponding to the function module to be tested when it is in the target test state; determining the state element corresponding to the input port of the function module to be tested in the gate-level netlist file of the integrated circuit; establishing a mapping relationship between the input port of the function module to be tested and the state element; based on the mapping relationship and the gate-level netlist file, performing simulation power consumption analysis on the integrated circuit, wherein the input stimulus is input to the state element during the simulation power consumption analysis process. The power consumption analysis method can perform detailed power consumption analysis at the function module level, obtain the dynamic power consumption of the function module of interest, and allow power consumption analysis of a single function module, so that these function modules can be subsequently optimized in a targeted manner.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a power consumption analysis method, a power consumption analysis device, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] In the design of integrated circuits (ICs), whether it is the design of high-performance central processing units (CPUs) or graphics processing units (GPUs), or the low-power design of the Internet of Things, etc., it is necessary to consider the battery life under low-power design and the thermal limitations of the circuit in high-power consumption operating modes. During the design phase of an integrated circuit, it is necessary to test the extreme operating states of the integrated circuit design under different test conditions to accurately evaluate the performance of the integrated circuit design. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a power consumption analysis method for the design of an integrated circuit, where the integrated circuit includes a functional module to be tested, and the power consumption analysis method includes: obtaining an input excitation corresponding to the functional module to be tested in a target test state; determining a state element corresponding to an input port of the functional module to be tested in a gate-level netlist file of the integrated circuit; establishing a mapping relationship between the input port of the functional module to be tested and the state element; and performing a simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, where during the simulation power consumption analysis, the input excitation is input to the state element.

[0004] For example, in the power consumption analysis method provided by at least one embodiment of the present disclosure, obtaining the input excitation corresponding to the functional module to be tested in the target test state includes: determining at least one simulation excitation; performing a simulation test on the functional module to be tested according to the at least one simulation excitation; and using the simulation excitation input when the functional module to be tested is in the target test state as the input excitation during the simulation test.

[0005] For example, in the power consumption analysis method provided by at least one embodiment of the present disclosure, determining at least one simulation excitation includes: constructing at least one set of random input data according to the target test state of the functional module to be tested, and using the at least one set of random input data as the at least one simulation excitation; or determining the at least one simulation excitation according to the module input-output behavior standard defined during the architecture design phase corresponding to the integrated circuit.

[0006] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, simulating and testing the to-be-tested functional module according to the at least one simulation stimulus includes: sequentially inputting the at least one simulation stimulus into the input port of the to-be-tested functional module to obtain the output waveform of the to-be-tested functional module; judging whether the to-be-tested functional module is in the target test state according to the output waveform; in response to the to-be-tested functional module being in the target test state, using the currently input simulation stimulus as the input stimulus, and in response to the to-be-tested functional module not being in the target test state, continuing to input the next simulation stimulus for the simulation test until the input stimulus is obtained.

[0007] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, performing power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file includes: based on the mapping relationship, inputting the input stimulus into the state element in the gate-level netlist file to simulate the circuit state in which the input stimulus is input into the gate-level circuit structure corresponding to the to-be-tested functional module through the state element; performing power consumption analysis on the integrated circuit according to the circuit state.

[0008] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, performing power consumption analysis on the integrated circuit according to the circuit state includes: obtaining the output result generated by the gate-level circuit structure when receiving the input stimulus; performing power consumption analysis on the gate-level circuit structure corresponding to the to-be-tested functional module according to the output result.

[0009] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, based on the mapping relationship, inputting the input stimulus into the state element in the gate-level netlist file to simulate the circuit state in which the input stimulus is input into the gate-level circuit structure corresponding to the to-be-tested functional module through the state element includes: setting the circuit part other than the gate-level circuit structure in the gate-level netlist file of the integrated circuit to a non-operating state and inputting the input stimulus into the state element; or only inputting the input stimulus into the state element and allowing the input stimulus to propagate only through the gate-level circuit structure.

[0010] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, the target test state includes the state of the highest power consumption or the state of the lowest leakage current.

[0011] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, the mapping relationship indicates that the input port of the to-be-tested functional module is mapped to the output port of the state element in the netlist file.

[0012] For example, at least one embodiment of the present disclosure provides a power consumption analysis method, which further includes: optimizing the to-be-tested functional module according to the result of the power consumption analysis.

[0013] For example, in a power consumption analysis method provided by at least one embodiment of the present disclosure, the to-be-tested functional module belongs to a first integrated circuit design, and the description form of the first integrated circuit design includes a register transfer level description file form or a gate-level netlist form; the description form or hierarchical structure of the first integrated circuit design is different from the gate-level netlist file of the integrated circuit.

[0014] At least one embodiment of the present disclosure provides a power consumption analysis device for the design of an integrated circuit. The integrated circuit includes a to-be-tested functional module. The power consumption analysis device includes: an acquisition unit configured to acquire an input stimulus corresponding to the to-be-tested functional module in a target test state; a determination unit configured to determine a state element corresponding to the input port of the to-be-tested functional module in the gate-level netlist file of the integrated circuit; a mapping unit configured to establish a mapping relationship between the input port of the to-be-tested functional module and the state element; and an analysis unit configured to perform a simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, wherein during the simulation power consumption analysis, the input stimulus is input to the state element.

[0015] For example, in a power consumption analysis device provided by at least one embodiment of the present disclosure, when the acquisition unit executes to acquire an input stimulus corresponding to the to-be-tested functional module in a target test state, it includes performing the following operations: determining at least one simulation stimulus; performing a simulation test on the to-be-tested functional module according to the at least one simulation stimulus; and during the simulation test, using the simulation stimulus input when the to-be-tested functional module is in the target test state as the input stimulus.

[0016] For example, in a power consumption analysis device provided by at least one embodiment of the present disclosure, when the acquisition unit executes to perform a simulation test on the to-be-tested functional module according to the at least one simulation stimulus, it includes performing the following operations: sequentially inputting the at least one simulation stimulus to the input port of the to-be-tested functional module to obtain an output waveform of the to-be-tested functional module; judging whether the to-be-tested functional module is in the target test state according to the output waveform; in response to the to-be-tested functional module being in the target test state, using the currently input simulation stimulus as the input stimulus, and in response to the to-be-tested functional module not being in the target test state, continuing to input the next simulation stimulus for the simulation test until the input stimulus is obtained.

[0017] For example, in a power consumption analysis device provided by at least one embodiment of the present disclosure, when the analysis unit performs simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, the following operations are included: Based on the mapping relationship, input the input stimulus into the state elements in the gate-level netlist file to simulate the circuit state when the input stimulus is input into the gate-level circuit structure corresponding to the function module to be tested through the state elements; perform power consumption analysis on the integrated circuit according to the circuit state.

[0018] For example, in a power consumption analysis device provided by at least one embodiment of the present disclosure, when the analysis unit performs power consumption analysis on the integrated circuit according to the circuit state, the following operations are included: Obtain the output result generated by the gate-level circuit structure when receiving the input stimulus; perform power consumption analysis on the gate-level circuit structure corresponding to the function module to be tested according to the output result.

[0019] For example, in a power consumption analysis device provided by at least one embodiment of the present disclosure, when the analysis unit performs the operation of inputting the input stimulus into the state elements in the gate-level netlist file based on the mapping relationship to simulate the circuit state when the input stimulus is input into the gate-level circuit structure corresponding to the function module to be tested through the state elements, the following operations are included: Set the circuit part other than the gate-level circuit structure in the gate-level netlist file of the integrated circuit to the non-operating state, and input the input stimulus into the state elements; or only input the input stimulus into the state elements and let the input stimulus propagate only through the gate-level circuit structure.

[0020] At least one embodiment of the present disclosure provides an electronic device, including: a memory that stores computer-executable instructions non-transiently; a processor configured to run the computer-executable instructions, wherein when the computer-executable instructions are run by the processor, the power consumption analysis method according to any embodiment of the present disclosure is implemented.

[0021] At least one embodiment of the present disclosure provides a non-transient computer-readable storage medium, wherein the non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the power consumption analysis method according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0023] Figure 1Schematic flowchart of a power consumption analysis method provided by at least one embodiment of the present disclosure;

[0024] Figure 2 Schematic diagram of simulation test of a functional module to be tested provided by at least one embodiment of the present disclosure;

[0025] Figure 3 Schematic diagram of mapping relationship between a functional module to be tested and a gate-level circuit structure provided by at least one embodiment of the present disclosure;

[0026] Figure 4 Schematic block diagram of a power consumption analysis device provided by at least one embodiment of the present disclosure;

[0027] Figure 5 Schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0028] Figure 6 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0029] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted in the present disclosure.

[0032] With the increasing demand for computing power, the scale of integrated circuits is getting larger and larger, making the requirements for power consumption analysis of integrated circuits higher and higher.

[0033] Integrated circuits can be divided into multiple functional modules according to their functions, and each functional module can be composed of some circuit logics that perform specific functions. For example, a functional module can be an arithmetic component for performing arithmetic tasks. For example, the functional module can be a multiplier, an accumulator, etc. For example, a functional module can be a module that performs data transmission functions. For example, the functional module can also be a functional module that completes register read / write and request forwarding functions, a functional module that completes task distribution functions, etc. For example, an integrated circuit realizes functions such as control, arithmetic, and storage by combining these functional modules.

[0034] For example, multiple functional modules can be designed and developed in parallel and finally jointly undergo synthesis, placement and routing, etc. For example, if a functional module appears only once in a circuit, for this functional module, the instance and the functional module have the same meaning, both referring to this functional module; if a functional module appears multiple times in an integrated circuit and is named differently, these functional modules with different names are called different instances. For example, an integrated circuit includes two functional modules 1, and the two functional modules 1 have different names and can be called instance 1 and instance 2 respectively.

[0035] In multiple design stages of the integrated circuit design process, the circuit will be simulated and verified, including pre-simulation, post-synthesis simulation, and post-simulation, etc. For example, pre-simulation includes Register Transfer Level (RTL) simulation. RTL simulation is based on RTL files for simulation, testing and simulating the logic function to verify whether the function meets the design requirements. For example, post-synthesis simulation backannotates the standard delay file to the synthesis simulation model to estimate the impact of gate delay on the circuit. For example, post-simulation includes simulating the netlist after placement and routing, and this simulation is closer to the actual operation of circuit devices.

[0036] In the process of simulating and verifying an integrated circuit, programs or modules are usually written to construct a generator for simulation stimuli, input the simulation stimuli into the top-level input port of the integrated circuit, simulate and verify the functional correctness of the hardware model, and perform system-level logic function simulation on the integrated circuit. For example, for a set of simulated input stimuli, it can be used to verify the scenario simulated by this set of input stimuli. In the design of an integrated circuit, it is necessary to simulate and test the circuit working states of the integrated circuit under various scenarios to ensure that the integrated circuit can work properly under various scenarios.

[0037] For large-scale integrated circuits, the power consumption of some key functional modules (such as functional modules that perform arithmetic tasks, such as multipliers, etc.) is crucial for the overall performance of the integrated circuit. The true power consumption of the integrated circuit can only be tested and obtained after layout and wiring are completed. For example, the waveform file can be obtained through post-layout and wiring simulation of the circuit, and the power consumption can be analyzed based on this waveform file. Although the post-simulation waveform is very close to the actual circuit situation, the post-simulation period is very long, and a large amount of hardware resources and time are required. Especially in ultra-large-scale integrated circuits, such as CPU (Central Processing Unit) or GPU (Graphics Processing Unit) chips, it is very difficult for designers to perform simulation verification of the entire circuit under various modes. In contrast, the time spent on pre-simulation is much less. Therefore, the post-simulation waveform can be obtained using the pre-simulation waveform, enabling power consumption analysis to be synchronized with the automatic layout and wiring in the project, greatly improving the speed of power consumption analysis and playing a key role in power consumption analysis and optimization.

[0038] However, the current power consumption analysis solution can only perform overall and system-level power consumption analysis on integrated circuits. After the input stimulus enters the integrated circuit through the external input port, it needs to go through multiple levels of data transmission (such as registers or other functional modules, etc.) to reach the input port of the key functional module, so it is impossible to specifically perform power consumption analysis on only the key functional module, and thus it is also impossible to specifically optimize the power consumption of these key functional modules.

[0039] In addition, for multiple functional modules in an integrated circuit, each functional module is very likely to work in different scenarios. For example, for multiple multipliers in an integrated circuit, some multipliers work in scenario 1, and some multipliers work in scenario 2. Scenario 1 and scenario 2 are not related to each other. For large-scale integrated circuits, it is very difficult to construct a scenario in which all multipliers are in the highest power consumption state or other test states, so it is also impossible to test the power consumption of the integrated circuit when all multipliers are in the highest power consumption state or other test states.

[0040] At least one embodiment of the present disclosure provides a power consumption analysis method, a power consumption analysis device, an electronic device, and a non-transitory computer-readable storage medium. The power consumption analysis method includes: obtaining the input stimulus corresponding to the to-be-tested functional module in the target test state; determining the state element corresponding to the input port of the to-be-tested functional module in the gate-level netlist file of the integrated circuit; establishing a mapping relationship between the input port of the to-be-tested functional module and the state element; and performing simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, wherein during the simulation power consumption analysis process, the input stimulus is input to the state element.

[0041] This power consumption analysis method can perform a detailed power consumption analysis at the functional module level, obtain the dynamic power consumption of the functional modules of interest, allow power consumption analysis of a single functional module or parallel power consumption analysis of multiple functional modules, determine the impact of the power consumption of the key functional modules in the integrated circuit on the entire integrated circuit, and thus subsequent targeted optimization of these functional modules can be carried out.

[0042] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0043] Figure 1 It is a schematic flowchart of a power consumption analysis method provided by at least one embodiment of the present disclosure.

[0044] For example, this power consumption analysis method is applied to the design of an integrated circuit. For example, the integrated circuit includes multiple functional modules, and the definition of the functional modules is as described above and will not be elaborated here.

[0045] For example, the functional module to be tested is a key functional module among multiple functional modules. For example, the functional module to be tested can be a functional module that performs arithmetic tasks or a functional module that performs data transmission functions. The present disclosure does not make specific limitations on this.

[0046] For example, the functional module to be tested can be an instance in the integrated circuit, and the concept of the instance is as described above. When the integrated circuit includes multiple instances corresponding to the same functional module, each instance can be used as the functional module to be tested and power consumption analysis can be performed independently.

[0047] For example, the functional module to be tested can also be some of the multiple functional modules, such as two or more functional modules as a whole being the functional module to be tested. For example, multiple functional modules can be developed in parallel by different development teams, and each development team is responsible for some of the functional modules. When performing power consumption testing, the partial functional modules responsible by each team can be used as the functional modules to be tested in the present invention, and power consumption analysis and optimization can be performed on the functional modules to be tested responsible by each development team respectively.

[0048] In the present disclosure, the functional module to be tested is the circuit logic for which power consumption analysis and optimization are desired. The content, division method, scope in the integrated circuit, functions, etc. of the functional module to be tested can be selected by those skilled in the art according to needs, and the present disclosure does not make specific limitations on this.

[0049] For example, the functional module to be tested may be in the form of a Register Transfer Level (RTL) description file, or the functional module to be tested may be in the form of a Gate-Level netlist. The synthesis level (or the level of abstraction) of the RTL level is higher than that of the gate-level netlist. The circuit elements involved at the RTL level are usually registers or combinational logic, and the circuit elements described in the gate-level netlist are "gates" or circuit elements at the same level. The present disclosure does not specifically limit the form of the functional module to be tested.

[0050] For example, as Figure 1 shown, the power consumption analysis method provided by the embodiments of the present disclosure includes steps S10 to S40.

[0051] In step S10, obtain the input excitation corresponding to the functional module to be tested when it is in the target test state.

[0052] For example, the target test state is the expected working state of the functional module to be tested. For example, if it is desired that the functional module to be tested operates in a high power consumption state to test the thermal limit of the integrated circuit, the target test state may be the highest power consumption state; for example, if it is desired that the functional module to be tested operates in a low power consumption state to test the battery life of the integrated circuit when it is in the sleep state or low power state, the target test state may be the lowest leakage current state, or the lowest power consumption state. Of course, the target test state may also be other desired working states, and the present disclosure does not specifically limit this.

[0053] For example, step S10 may include: determining at least one simulation excitation; performing a simulation test on the functional module to be tested according to at least one simulation excitation; during the simulation test, using the simulation excitation input when the functional module to be tested is in the target test state as the input excitation.

[0054] For example, determining at least one simulation excitation may include: constructing at least one set of random input data according to the target test state of the functional module to be tested, and using at least one set of random input data as at least one simulation excitation; or determining at least one simulation excitation according to the module input-output behavior standard defined in the architecture design stage corresponding to the integrated circuit.

[0055] For example, the simulation test of the functional module to be tested according to at least one simulation stimulus may include: sequentially inputting at least one simulation stimulus into the input port of the functional module to be tested to obtain the output waveform of the functional module to be tested; judging whether the functional module to be tested is in the target test state according to the output waveform; in response to the functional module to be tested being in the target test state, taking the currently input simulation stimulus as the input stimulus, and in response to the functional module to be tested not being in the target test state, continuing to input the next simulation stimulus for the simulation test until the input stimulus is obtained.

[0056] For example, the functional module to be tested can be used as an independent unit circuit for simulation testing. At this time, the input stimulus does not need to reach the functional module to be tested through multi-level signal transmission, but can be directly input into the input port of the functional module to be tested. Therefore, it is easier to cover various simulation scenarios of the functional module to be tested, construct simulation stimuli under various simulation scenarios and directly input them into the functional module to be tested, and obtain the input stimulus when the functional module to be tested is in the target test state more conveniently, quickly and at low cost.

[0057] For example, the input stimulus is related to the target test state. For example, for a multiplier, when obtaining the input stimulus when the multiplier is in the highest power consumption state, multiple groups of random numbers can be constructed as simulation stimuli, and the simulation stimuli are directly input into the input port of the functional module to be tested (multiplier) to obtain the output waveform of the output port of the functional module to be tested. According to the output waveform, it can be judged whether the functional module to be tested is in the highest power consumption state. After obtaining the desired output waveform, the simulation stimulus that can output the desired output waveform is taken as the input stimulus.

[0058] For example, in the process of integrated circuit design, the output results of the architecture design stage are a formal architecture design document and a set of C models. The architecture design document describes the working principle of the integrated circuit, and the C model further defines the input and output behavior of the integrated circuit. For example, the simulation stimulus can be the fixed-point format input data defined in the C model related to the functional module to be tested.

[0059] In the process of obtaining the input stimulus corresponding to the functional module to be tested in the target test state, the functional module to be tested is analyzed as an independent unit circuit, so that the constructed simulation stimulus can be directly input into the input port of the functional module to be tested, and the power consumption analysis of the unit circuit can be directly carried out. Therefore, there is no need to regard the integrated circuit as a whole, and the input stimulus does not need to pass through multi-level signal transmission to reach the functional module to be tested, so that the input stimulus corresponding to the functional module to be tested in the target test state can be obtained quickly and at low cost.

[0060] For example, during the simulation test process, input stimuli can also be obtained based on the design of the entire integrated circuit. For example, the constructed simulation stimuli are input into the integrated circuit. The constructed simulation stimuli are mainly related to the functional module to be tested. Whether the functional module to be tested is in the target test state is determined according to the output waveform of the functional module to be tested, and the input stimuli are obtained. The specific process will not be elaborated here.

[0061] Figure 2 It is a schematic diagram of the simulation test of the functional module to be tested provided by at least one embodiment of the present disclosure.

[0062] As Figure 2 shown, for the functional module 102 to be tested, it can be used as an independent unit circuit for simulation testing. The simulation stimulus generator 101 is used to generate one or more simulation stimuli and input them into the functional module to be tested. The analog clock generator 103 is used to generate an analog clock signal and provide it to the functional module 102 to be tested. Thus, the functional module 102 to be tested can receive the simulation stimuli under the control of the analog clock signal, output the corresponding output waveform, and determine the input stimuli corresponding to the target test state of the functional module to be tested according to the output waveform.

[0063] In this embodiment, by performing simulation testing on the functional module to be tested as a separate unit circuit, a custom input stimulus can be conveniently established for the functional module to be tested, and various test scenarios can be more easily covered, so that the functional module to be tested is in the target test state.

[0064] In step S20, determine the state element corresponding to the input port of the functional module to be tested in the gate-level netlist file of the integrated circuit.

[0065] A state element is a circuit element in an integrated circuit that affects the circuit state. For example, state elements can include input ports (INPUT PORT), registers, memories, etc. of the integrated circuit.

[0066] During the design process of the integrated circuit, the state elements between different versions of RTL and netlist need to be matched, and here the matching means they have a one-to-one mapping relationship.

[0067] For example, if the functional module to be tested is in RTL form, the RTL file is synthesized to obtain a gate-level netlist file, and the circuit function of the gate-level netlist is the same as that of the RTL file. For example, the input port of the functional module to be tested has a corresponding state element in the gate-level netlist after synthesis. For example, the state element corresponding to the input port of the functional module to be tested in the gate-level netlist is a register, and under the control of the system clock, the register inputs the input signal into the functional module to be tested.

[0068] For example, integrated circuits are designed using a hierarchy design approach. After processes such as synthesis or optimization iterations, the hierarchy of the integrated circuit may change.

[0069] For example, the functional module to be tested belongs to a first integrated circuit design. The first integrated circuit design can be in the form of an RTL file or a gate-level netlist. The description form or hierarchical structure of the first integrated circuit design is different from that of the "gate-level netlist file of the integrated circuit". For example, the first integrated circuit design can be an RTL file. In this case, the description form of the first integrated circuit design is different from that of the "gate-level netlist file of the integrated circuit". For example, when the first integrated circuit design is also in the form of a gate-level netlist, the hierarchical structure of the first integrated circuit design is different from that of the gate-level netlist file of the integrated circuit.

[0070] For example, the hierarchy of the input port of the functional module to be tested in the first integrated circuit design is different from that of the state element corresponding to the input port in the gate-level netlist file of the integrated circuit. Therefore, in step S30, it is necessary to establish a mapping relationship between the input port of the functional module to be tested and the state element so that the input port of the functional module to be tested matches the corresponding state element. Thus, the integrated circuit can be simulated for power consumption analysis using the gate-level netlist file of the integrated circuit.

[0071] For example, the mapping relationship indicates that the input port of the functional module to be tested is mapped to the output port of the state element in the netlist file.

[0072] Figure 3 Schematic diagram of the mapping relationship between the functional module to be tested and the gate-level circuit structure provided by at least one embodiment of the present disclosure.

[0073] As Figure 3 shown, the functional module 100 to be tested belongs to a first integrated circuit design. The first integrated circuit design is, for example, in the form of an RTL file.

[0074] As Figure 3 shown, the functional module 100 to be tested includes input port A0, input port A1, and input port A2. In addition, the functional module to be tested also includes a clock signal input port CLK.

[0075] The gate-level circuit structure corresponding to the functional module to be tested in the netlist file of the integrated circuit is as Figure 3 shown by the gate-level circuit structure 200 in

[0076] For example, the state element corresponding to the input port A0 of the functional module to be tested is register 201_A0, the state element corresponding to the input port A1 of the functional module to be tested is register 201_A1, and the state element corresponding to the input port A2 of the functional module to be tested is register 201_A2.

[0077] As Figure 3 shown, the gate-level circuit structure 200 further includes a circuit logic 202 for implementing the circuit functions of the functional module to be tested, and an output register 203.

[0078] For example, the hierarchy of the input port of the functional module to be tested in the first integrated circuit design is different from the hierarchy of the corresponding state element in the gate-level circuit structure, and a mapping relationship needs to be established between the input port of the functional module to be tested and the state element.

[0079] For example, the mapping relationship is as follows:

[0080] DesignName0 / A0 => DesignName1 / U0 / Q0

[0081] DesignName0 / A1 => DesignName1 / U1 / Q1

[0082] DesignName0 / A2 => DesignName1 / U2 / Q2

[0083] ……

[0084] For example, the hierarchy (or hierarchical relationship) of the input port A0 is DesignName0 / A0, indicating that the input port A0 is within the design DesignName0; the hierarchy of the input port A1 is DesignName0 / A1; the hierarchy of the input port A2 is DesignName0 / A2.

[0085] For example, the state element corresponding to the input port A0 is the register 201_A0. The input port A0 is mapped to the output port Q0 of the register 201_A0 in the netlist file of the integrated circuit. The hierarchy of the register 201_A0 in the netlist file of the integrated circuit is DesignName1 / U0, which is different from the hierarchy of the input port A0 in the first integrated circuit design.

[0086] For example, the state element corresponding to the input port A1 is the register 201_A1. The input port A1 is mapped to the output port Q1 of the register 201_A1 in the netlist file of the integrated circuit. The hierarchy of the register 201_A1 in the netlist file of the integrated circuit is DesignName1 / U1, which is different from the hierarchy of the input port A1 in the first integrated circuit design.

[0087] Similarly, the status element corresponding to input port A2 is register 201_A2. Input port A2 is mapped to the output port Q2 of register 201_A2 in the netlist file of the integrated circuit. The hierarchy of register 201_A2 in the netlist file of the integrated circuit is DesignName1 / U2, which is different from the hierarchy of input port A2 in the first integrated circuit design.

[0088] Of course, the functional module to be tested may further include more input ports, and these input ports also have corresponding status elements in the netlist file of the integrated circuit. Similar to input port A0, mapping relationships are respectively established between these input ports and the corresponding status elements to make them match, which will not be elaborated here.

[0089] In step S40, based on the mapping relationship and the gate-level netlist file, simulation power analysis is performed on the integrated circuit. During the simulation power analysis, input stimuli are input into the status elements.

[0090] For example, step S40 may include: based on the mapping relationship, inputting the input stimuli into the status elements in the gate-level netlist file to simulate the circuit state when the input stimuli are input into the corresponding gate-level circuit structure of the functional module to be tested through the status elements; performing power analysis on the integrated circuit according to the circuit state.

[0091] For example, when performing power analysis, the input stimuli are input into the status elements, so that the input waveform at the input port of the functional module to be tested is the same as the waveform at the output port of the status element with which the mapping relationship is established. Thus, the corresponding gate-level circuit structure of the functional module to be tested can operate in the desired working state under the action of the input stimuli.

[0092] For example, according to the correspondence between the input ports of the functional module to be tested and the status elements in the gate-level netlist file of the integrated circuit, the power replay technology can be used to input the input stimuli into the status elements, replay the waveforms between the status elements cycle by cycle based on the status of the status elements, simulate the circuit state of the corresponding gate-level circuit structure of the functional module to be tested, and obtain the simulated waveform of the functional module to be tested.

[0093] For example, the power replay technology supports selecting the power analysis area of the integrated circuit, so that it is possible to perform separate power tests on the functional module to be tested in a targeted manner.

[0094] For example, based on the mapping relationship, the input excitation is input into the state elements in the gate-level netlist file to simulate the circuit state where the input excitation is input into the gate-level circuit structure corresponding to the function module to be tested through the state elements, which may include: setting the circuit parts other than the gate-level circuit structure corresponding to the function module to be tested in the gate-level netlist file of the integrated circuit to the non-operating state, and inputting the input excitation into the state elements; or only inputting the input excitation into the state elements and allowing the input excitation to propagate only through the gate-level circuit structure.

[0095] For example, in some embodiments, during the power consumption analysis process, the circuit parts other than the gate-level circuit structure in the gate-level netlist file of the integrated circuit can be set to the non-operating state. For example, other circuit parts do not provide input data and are in the "X" state (indeterminate state), and the input excitation is input into the corresponding state elements, thereby obtaining the power consumption analysis result only including the function module to be tested.

[0096] For example, in some other embodiments, during the power consumption analysis process, the input excitation can be injected only into the corresponding state elements and allowed to propagate only through the function module to be tested, thereby obtaining the power consumption analysis result only including the function module to be tested.

[0097] For example, according to the circuit state, performing power consumption analysis on the integrated circuit may include: obtaining the output result generated by the gate-level circuit structure when receiving the input excitation; and performing power consumption analysis on the gate-level circuit structure corresponding to the function module to be tested according to the output result.

[0098] For example, the output result may be a current waveform, and the dynamic power consumption of the gate-level circuit structure can be calculated through the current waveform to perform power consumption analysis on the gate-level circuit structure corresponding to the function module to be tested.

[0099] In this embodiment, a detailed power consumption analysis result at the function module level can be obtained. For example, a detailed power consumption analysis result of the function module to be tested can be obtained. Then, according to the result of the power consumption analysis, targeted optimization can be performed on the function module to be tested. Different from the current technical solutions that can only obtain the overall power consumption of the integrated circuit, the power consumption analysis method provided by at least one embodiment of the present invention can obtain a more fine-grained power consumption analysis result, such as at the function module level, so as to provide a decision reference for the optimization of these function modules during the optimization process of the integrated circuit.

[0100] For example, when the integrated circuit includes multiple function modules to be tested, the types of the multiple function modules to be tested can be the same, for example, all are multipliers.

[0101] For example, in some embodiments, the target test states of multiple functional modules to be tested may be the same. For example, at this time, step S10 may be performed on one of the functional modules to be tested to obtain the input excitation corresponding to the functional module to be tested when it is in the target test state. Then, in step S20, the state elements respectively corresponding to the input ports of each functional module to be tested in the gate-level netlist file of the integrated circuit are obtained, and in step S30, a mapping relationship is established between the input ports of each functional module to be tested and the corresponding state elements. Finally, in step S40, the input excitation is input into the state elements respectively corresponding to each functional module to be tested, and a simulation test is performed with reference to the process of step S40.

[0102] For example, in some other embodiments, when the integrated circuit includes multiple functional modules to be tested, the target test states of the multiple functional modules to be tested may not be completely the same. For example, the target test state of some functional modules to be tested is the first test state, and the target test state of other functional modules to be tested is the second test state. For example, at this time, step S10 may be performed on one of the functional modules to be tested to obtain the first input excitation corresponding to the functional module to be tested when it is in the first test state, and the second input excitation corresponding to the functional module to be tested when it is in the second test state. Then, in step S20, the state elements respectively corresponding to the input ports of each functional module to be tested in the gate-level netlist file of the integrated circuit are obtained, and in step S30, a mapping relationship is established between the input ports of each functional module to be tested and the corresponding state elements. Finally, in step S40, the first input excitation is input into the state element corresponding to the functional module to be tested whose target test state is the first test state, and the second input excitation is input into the state element corresponding to the functional module to be tested whose target test state is the second test state, and a power consumption analysis is performed with reference to the process of step S40. Of course, it should be noted that the target test state may also include the third test state, the fourth test state, etc., which will not be elaborated here.

[0103] For example, taking the functional module to be tested as a multiplier as an example, if an integrated circuit includes N multipliers and one of them is subject to simulation testing, the random distribution input when obtaining the expected waveform of the multiplier output is referred to step S10. Then, when performing power consumption analysis, this random distribution can be input into the state elements corresponding to the input ports of the N multipliers, and power consumption analysis can be performed in combination with the power replay technology; or, M of the N multipliers correspond to the first test state, and N - M multipliers correspond to the second test state. The input excitation corresponding to the multiplier in the first test state is the first random distribution, and the input excitation corresponding to the multiplier in the second test state is the second random distribution. When performing power consumption analysis, the first random distribution is input into the state elements corresponding to the input ports of the M multipliers, and the second random distribution is input into the state elements corresponding to the input ports of the N - M multipliers, and power consumption analysis is performed in combination with the power replay technology. Here, M and N are positive integers.

[0104] For example, at least some of the multiple functional modules to be tested have different hierarchical structures in the first integrated circuit design. For example, for N modules to be tested in an integrated circuit, the hierarchical structures of the N modules to be tested in the integrated circuit may not be exactly the same. For example, some modules to be tested are located at the top layer, some modules to be tested are located in module A under the first sub - design, some modules to be tested are located in module B under the second sub - design, and some modules to be tested are located in sub - module C under module A, etc. The present disclosure does not make specific limitations on this.

[0105] In the above - mentioned embodiments, taking the functional module to be tested as an independent circuit for simulation testing can obtain the input excitation of the functional module to be tested in the target test state more conveniently, quickly, and at low cost. Multiple functional modules to be tested can correspond to the same target test state or have different target test states. Each functional module to be tested can analyze power consumption independently, or the power consumption when all functional modules to be tested are in the target test state can also be comprehensively analyzed. Even if the integrated circuit itself has a complex and large structure, or the hierarchical structures of the functional modules to be tested in the integrated circuit are different, it does not affect the implementation of the solution, and power consumption analysis can still be performed.

[0106] For example, when an integrated circuit includes multiple functional modules to be tested, the types of the multiple functional modules to be tested can be different. For example, the functional module to be tested can include a computing unit, a transmission unit, etc.

[0107] For example, in some embodiments, based on the mapping relationship and the gate - level netlist file, performing power consumption analysis on an integrated circuit may include: based on the mapping relationship of each functional module to be tested and the gate - level netlist file, performing power consumption analysis on the integrated circuit; wherein, during the power consumption analysis process, power consumption analysis is independently performed on the multiple gate - level circuit structures corresponding to the multiple functional modules to be tested.

[0108] For example, in this embodiment, each functional module to be tested separately executes steps S10 - S30 to obtain the input excitations corresponding to the respective functional modules to be tested, the state elements corresponding to the input ports of the respective functional modules to be tested, and establish a mapping relationship between the state elements corresponding to the input ports of the respective functional modules to be tested and the input ports of the functional modules to be tested. Repeated parts will not be elaborated here. After that, the input excitations corresponding to the respective functional modules to be tested are respectively input into the state elements corresponding to the respective functional modules to be tested, so that the input excitations propagate in the integrated circuit through the corresponding gate - level circuit structure, and the overall power consumption of the integrated circuit is analyzed. For example, the thermal limit when all the functional modules of interest in the integrated circuit are in the highest power - consumption state can be tested, or the battery life when all the functional modules of interest in the integrated circuit are in the lowest power - consumption state can be tested.

[0109] For example, in some other embodiments, when the integrated circuit includes multiple functional modules to be tested, the functional modules to be tested can separately and independently execute steps S10 - S40 to independently perform parallel power - consumption analysis on the respective functional modules to be tested.

[0110] Corresponding to the above - mentioned power - consumption analysis method, at least one embodiment of the present disclosure further provides a power - consumption analysis device. Figure 4 It is a schematic block diagram of a power - consumption analysis device provided by at least one embodiment of the present disclosure.

[0111] For example, this power - consumption analysis device is used for the design of an integrated circuit, and the integrated circuit includes functional modules to be tested. The relevant descriptions regarding the functional modules to be tested can refer to the relevant content of the foregoing power - consumption analysis method, and will not be elaborated here.

[0112] For example, as Figure 4 shown, the power - consumption analysis device 300 includes: an acquisition unit 301, a determination unit 302, a mapping unit 303, and an analysis unit 304.

[0113] The acquisition unit 301 is configured to acquire the input excitation corresponding to the functional module to be tested in the target test state.

[0114] The determination unit 302 is configured to determine the state element corresponding to the input port of the functional module to be tested in the gate - level netlist file of the integrated circuit.

[0115] The mapping unit 303 is configured to establish a mapping relationship between the input port of the functional module to be tested and the state element;

[0116] The analysis unit 304 is configured to perform simulation power - consumption analysis on the integrated circuit based on the mapping relationship and the gate - level netlist file, wherein during the simulation power - consumption analysis process, the input excitation is input into the state element.

[0117] For example, when the obtaining unit 301 executes the operation of obtaining the input excitation corresponding to the to-be-tested functional module in the target test state, it includes performing the following operations: determining at least one simulation excitation; performing a simulation test on the to-be-tested functional module according to the at least one simulation excitation; during the simulation test, using the simulation excitation input when the to-be-tested functional module is in the target test state as the input excitation.

[0118] For example, when the obtaining unit 301 executes the operation of determining at least one simulation excitation, it includes performing the following operations: constructing at least one set of random input data according to the target test state of the to-be-tested functional module, and using the at least one set of random input data as the at least one simulation excitation; or determining at least one simulation excitation according to the module input-output behavior standard defined in the architecture design stage corresponding to the integrated circuit.

[0119] For example, when the obtaining unit 301 executes the operation of performing a simulation test on the to-be-tested functional module according to the at least one simulation excitation, it includes performing the following operations: sequentially inputting the at least one simulation excitation into the input port of the to-be-tested functional module to obtain the output waveform of the to-be-tested functional module; judging whether the to-be-tested functional module is in the target test state according to the output waveform; in response to the to-be-tested functional module being in the target test state, using the currently input simulation excitation as the input excitation, and in response to the to-be-tested functional module not being in the target test state, continuing to input the next simulation excitation for the simulation test until the input excitation is obtained.

[0120] For example, when the analysis unit 304 executes the operation of performing power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, it includes performing the following operations: based on the mapping relationship, inputting the input excitation into the state elements in the gate-level netlist file to simulate the circuit state where the input excitation is input to the gate-level circuit structure corresponding to the to-be-tested functional module through the state elements; performing power consumption analysis on the integrated circuit according to the circuit state.

[0121] For example, when the analysis unit 304 executes the operation of performing power consumption analysis on the integrated circuit according to the circuit state, it includes performing the following operations: obtaining the output result generated by the gate-level circuit structure when receiving the input excitation; performing power consumption analysis on the gate-level circuit structure corresponding to the to-be-tested functional module according to the output result.

[0122] When the analysis unit 304 executes the operation of, based on the mapping relationship, inputting the input excitation into the state elements in the gate-level netlist file to simulate the circuit state where the input excitation is input to the gate-level circuit structure corresponding to the to-be-tested functional module through the state elements, it includes performing the following operations: setting the circuit part other than the gate-level circuit structure in the gate-level netlist file of the integrated circuit to the non-operating state and inputting the input excitation into the state elements; or only inputting the input excitation into the state elements and allowing the input excitation to propagate only through the gate-level circuit structure.

[0123] For example, the target test state includes the state with the highest power consumption or the state with the lowest leakage current.

[0124] For example, the mapping relationship indicates that the input port of the functional module to be tested is mapped to the output port of the state element in the netlist file. For example, the power consumption analysis device 300 further includes an optimization unit (not shown), and the optimization unit is configured to optimize the functional module to be tested according to the result of the power consumption analysis.

[0125] For example, the functional module to be tested belongs to the first integrated circuit design, and the description form of the first integrated circuit design includes the register transfer level description file form or the gate-level netlist form; the description form or hierarchical structure of the first integrated circuit design is different from the gate-level netlist file of the integrated circuit.

[0126] For example, the integrated circuit includes multiple functional modules to be tested, and the target test states of the multiple functional modules to be tested are the same; or the target test states of the multiple functional modules to be tested are not completely the same.

[0127] For example, at least some of the multiple functional modules to be tested have different hierarchical structures in the first integrated circuit design.

[0128] For example, the acquisition unit 301, the determination unit 302, the mapping unit 303, and the analysis unit 304 include codes and programs stored in the memory; the processor can execute the codes and programs to implement some or all of the functions of the acquisition unit 301, the determination unit 302, the mapping unit 303, and the analysis unit 304 as described above. For example, the acquisition unit 301, the determination unit 302, the mapping unit 303, and the analysis unit 304 can be dedicated hardware devices used to implement some or all of the functions of the acquisition unit 301, the determination unit 302, the mapping unit 303, and the analysis unit 304 as described above. For example, the acquisition unit 301, the determination unit 302, the mapping unit 303, and the analysis unit 304 can be a circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiments of the present application, the combination of the one circuit board or multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0129] It should be noted that the acquisition unit 301 is used to implement Figure 1 step S10 shown, the determination unit 302 is used to implement Figure 1 step S20 shown, the mapping unit 303 is used to implement Figure 1 step S30 shown, and the analysis unit 304 is used to implement Figure 1 step S40 shown. Therefore, the specific description of the acquisition unit 301 can be referred to in the embodiments of the above power consumption analysis methodFigure 1 Regarding the relevant description of step S10 shown, for the specific description of the determination unit 302, reference can be made to the embodiments of the above power consumption analysis method Figure 1 Regarding the relevant description of step S20 shown, for the specific description of the mapping unit 303, reference can be made to the embodiments of the above power consumption analysis method Figure 1 Regarding the relevant description of step S30 shown, for the specific description of the analysis unit 304, reference can be made to the embodiments of the above power consumption analysis method Figure 1 Regarding the relevant description of step S40 shown. In addition, the power consumption analysis device can achieve technical effects similar to those of the foregoing power consumption analysis method, which will not be elaborated here.

[0130] At least one embodiment of the present disclosure further provides an electronic device, Figure 5 which is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0131] For example, as Figure 5 shown, the electronic device includes a processor 401, a communication interface 402, a memory 403, and a communication bus 404. The processor 401, the communication interface 402, and the memory 403 communicate with each other through the communication bus 404, and components such as the processor 401, the communication interface 402, and the memory 403 can also communicate through a network connection. The present disclosure does not limit the type and function of the network here.

[0132] For example, the memory 403 is used to non-transiently store computer-executable instructions. When the processor 401 is used to run the computer-executable instructions, the computer-executable instructions, when run by the processor 401, implement the power consumption analysis method according to any of the above embodiments. For the specific implementation of each step of this power consumption analysis method and the related explanatory content, reference can be made to the embodiments of the above power consumption analysis method, which will not be elaborated here.

[0133] For example, the implementation manner in which the processor 401 executes the program stored on the memory 403 to implement the power consumption analysis method is the same as the implementation manner mentioned in the embodiment part of the foregoing power consumption analysis method, which will not be elaborated here either.

[0134] For example, the communication bus 404 can be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0135] For example, the communication interface 402 is used to implement communication between the electronic device and other devices.

[0136] For example, the processor 401 and the memory 403 can be disposed on the server side (or cloud).

[0137] For example, the processor 401 can control other components in the electronic device to perform desired functions. The processor 401 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be of the X86 or ARM architecture, etc.

[0138] For example, the memory 403 can include any combination of one or more computer program products, and the computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions can be stored on the computer-readable storage media, and the processor 401 can run the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data can also be stored in the storage media.

[0139] For example, for a detailed description of the process of the electronic device performing power consumption analysis, reference can be made to the relevant descriptions in the embodiments of the power consumption analysis method, and repeated parts will not be elaborated.

[0140] Figure 6 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 6 shown, one or more computer-executable instructions 501 can be non-temporarily stored on the storage medium 500. For example, when the computer-executable instructions 501 are executed by the processor, one or more steps in the power consumption analysis method described above can be executed.

[0141] For example, the storage medium 500 can be applied to the above-mentioned electronic device and / or the power consumption analysis device 1400. For example, the storage medium 500 can include the memory 1003 in the electronic device.

[0142] For example, for the description of the storage medium 500, reference can be made to the description of the memory in the embodiments of the electronic device, and repeated parts will not be elaborated.

[0143] Those skilled in the art can understand that the content disclosed in the present disclosure can have various variations and improvements. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0144] In addition, although the present disclosure makes various references to certain units in the system according to the embodiments of the present disclosure, however, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0145] Flowcharts are used in the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps do not necessarily need to be carried out precisely in sequence. On the contrary, the steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes.

[0146] Those of ordinary skill in the art can understand that all or part of the steps in the above methods can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disc, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, the various modules / units in the above embodiments can be implemented in the form of hardware or in the form of software function modules. The present disclosure is not limited to any specific form of the combination of hardware and software.

[0147] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the related art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

Claims

1. A power consumption analysis method for use in the design of integrated circuits, wherein, The integrated circuit includes a functional module to be tested. The power consumption analysis method includes: Obtaining an input stimulus corresponding to the functional module to be tested when it is in a target test state; Determining a state element corresponding to the input port of the functional module to be tested in the gate-level netlist file of the integrated circuit; Establishing a mapping relationship between the input port of the functional module to be tested and the state element; Performing simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, wherein during the simulation power consumption analysis process, the input stimulus is input into the state element.

2. The power consumption analysis method according to claim 1, wherein, Obtaining an input stimulus corresponding to the functional module to be tested when it is in a target test state includes: Determining at least one simulation stimulus; Performing a simulation test on the functional module to be tested according to the at least one simulation stimulus; During the simulation test process, using the simulation stimulus input when the functional module to be tested is in the target test state as the input stimulus.

3. The power consumption analysis method according to claim 2, wherein Determining at least one simulation stimulus includes: According to the target test state of the functional module to be tested, constructing at least one set of random input data, and using the at least one set of random input data as the at least one simulation stimulus; or, Determining the at least one simulation stimulus according to the module input / output behavior standard defined during the architecture design phase corresponding to the integrated circuit.

4. The power consumption analysis method according to claim 2, wherein, Performing a simulation test on the functional module to be tested according to the at least one simulation stimulus includes: Sequentially inputting the at least one simulation stimulus into the input port of the functional module to be tested to obtain an output waveform of the functional module to be tested; Judging whether the functional module to be tested is in the target test state according to the output waveform; In response to the functional module to be tested being in the target test state, using the currently input simulation stimulus as the input stimulus, In response to the functional module to be tested not being in the target test state, continuing to input the next simulation stimulus for the simulation test until the input stimulus is obtained.

5. The power consumption analysis method according to claim 1, wherein, Performing power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file includes: Based on the mapping relationship, inputting the input stimulus into the state element in the gate-level netlist file to simulate the circuit state where the input stimulus is input into the gate-level circuit structure corresponding to the functional module to be tested through the state element; Performing power consumption analysis on the integrated circuit according to the circuit state.

6. The power consumption analysis method according to claim 5, wherein, Performing power consumption analysis on the integrated circuit according to the circuit state includes: Obtaining an output result generated by the gate-level circuit structure when receiving the input stimulus; Performing power consumption analysis on the gate-level circuit structure corresponding to the functional module to be tested according to the output result.

7. The power consumption analysis method according to claim 5, wherein, Based on the mapping relationship, inputting the input stimulus into the state element in the gate-level netlist file to simulate the circuit state where the input stimulus is input into the gate-level circuit structure corresponding to the functional module to be tested through the state element, includes: Set the circuit part other than the gate-level circuit structure in the gate-level netlist file of the integrated circuit to a non-operating state, and input the input stimulus into the state element; or Only input the input stimulus into the state element, and let the input stimulus propagate only through the gate-level circuit structure.

8. The power consumption analysis method according to any one of claims 1-7, wherein, The target test state includes the state with the highest power consumption or the state with the lowest leakage current.

9. The power consumption analysis method according to any one of claims 1-7, wherein, The mapping relationship indicates that the input port of the functional module to be tested is mapped to the output port of the state element in the netlist file.

10. The power consumption analysis method according to any one of claims 1-7 further includes: Optimize the functional module to be tested according to the result of the power consumption analysis.

11. The power consumption analysis method according to any one of claims 1-7, wherein, The functional module to be tested belongs to a first integrated circuit design, and the description form of the first integrated circuit design includes a register transfer level description file form or a gate-level netlist form; The description form or hierarchical structure of the first integrated circuit design is different from the gate-level netlist file of the integrated circuit.

12. The power consumption analysis method according to any one of claims 1-7, wherein, The integrated circuit includes a plurality of the functional modules to be tested, The target test states of the plurality of functional modules to be tested are the same; or The target test states of the plurality of functional modules to be tested are not completely the same.

13. The power consumption analysis method according to claim 11, wherein, At least some of the plurality of functional modules to be tested have different hierarchical structures in the first integrated circuit design.

14. A power consumption analysis device for the design of integrated circuits, wherein, The integrated circuit includes a functional module to be tested, The power consumption analysis device includes: An acquisition unit configured to acquire the input stimulus corresponding to the functional module to be tested in the target test state; A determination unit configured to determine the state element corresponding to the input port of the functional module to be tested in the gate-level netlist file of the integrated circuit; A mapping unit configured to establish a mapping relationship between the input port of the functional module to be tested and the state element; An analysis unit configured to perform a simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, wherein during the simulation power consumption analysis process, the input stimulus is input into the state element.

15. The power consumption analysis device according to claim 14, wherein, When the acquisition unit executes to acquire the input stimulus corresponding to the functional module to be tested in the target test state, it includes performing the following operations: Determine at least one simulation stimulus; Perform a simulation test on the functional module to be tested according to the at least one simulation stimulus; During the simulation test process, use the simulation stimulus input when the functional module to be tested is in the target test state as the input stimulus.

16. The power consumption analysis device according to claim 15, wherein, When the acquisition unit executes to perform a simulation test on the functional module to be tested according to the at least one simulation stimulus, it includes performing the following operations: Sequentially input the at least one simulation stimulus into the input port of the functional module to be tested to obtain the output waveform of the functional module to be tested; According to the output waveform, determine whether the functional module to be tested is in the target test state; In response to the functional module to be tested being in the target test state, use the currently input simulation stimulus as the input stimulus, In response to the function module to be tested not being in the target test state, continue to input the next simulation excitation for the simulation test until the input excitation is obtained.

17. The power consumption analysis device according to claim 14, wherein, When the analysis unit performs simulation power consumption analysis on the integrated circuit based on the mapping relationship and the gate-level netlist file, it includes performing the following operations: Based on the mapping relationship, input the input excitation into the state elements in the gate-level netlist file to simulate the circuit state when the input excitation is input into the gate-level circuit structure corresponding to the function module to be tested through the state elements; Perform power consumption analysis on the integrated circuit according to the circuit state.

18. The power consumption analysis device according to claim 17, wherein, When the analysis unit performs power consumption analysis on the integrated circuit according to the circuit state, it includes performing the following operations: Obtain the output result generated by the gate-level circuit structure when receiving the input excitation; Perform power consumption analysis on the gate-level circuit structure corresponding to the function module to be tested according to the output result.

19. The power consumption analysis device according to claim 17, wherein, When the analysis unit performs, based on the mapping relationship, inputting the input excitation into the state elements in the gate-level netlist file to simulate the circuit state when the input excitation is input into the gate-level circuit structure corresponding to the function module to be tested through the state elements, it includes performing the following operations: Set the circuit part other than the gate-level circuit structure in the gate-level netlist file of the integrated circuit to the non-operating state, and input the input excitation into the state elements; or Only input the input excitation into the state elements and let the input excitation propagate only through the gate-level circuit structure.

20. An electronic device, comprising: A memory that non-transiently stores computer-executable instructions; A processor configured to run the computer-executable instructions, wherein, when the computer-executable instructions are run by the processor, the power consumption analysis method according to any one of claims 1-13 is implemented.

21. A non-transitory computer-readable storage medium, wherein, The non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the power consumption analysis method according to any one of claims 1-13 is implemented.

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