Semiconductor memory device

Abstract

A semiconductor memory device capable of improving robustness of data input / output is provided. The semiconductor memory device of an embodiment includes a plurality of data latch circuits (XDL) for sensing input / output of data between a sense amplifier circuit and an input / output circuit, and a bus (XBUS) connected to the plurality of data latch circuits (XDL). The data latch circuit (XDL) includes an inverter circuit (XIV) for temporarily storing data input / output between the sense amplifier circuit and the input / output circuit, and an N-channel MOS transistor (TN31), (TN32) and a P-channel MOS transistor (TP31) connected in parallel between the inverter circuit (XIV) and the bus (XBUS). The N-channel MOS transistors (TN31), (TN32) are multiplied.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2021-154184 (Filing Date: September 22, 2021). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor memory device. BACKGROUND

[0004] A conventional semiconductor memory device has a plurality of data latch circuits for input and output of data between a sense amplifier and an input and output circuit. The plurality of data latch circuits are connected to each other via a data line. Data output from the sense amplifier is temporarily stored in the data latch circuits and then output from the input and output circuit via the data line. SUMMARY

[0005] According to the disclosed embodiments, a semiconductor memory device capable of improving robustness of data input and output is provided.

[0006] The semiconductor memory device of the embodiments includes a plurality of data latch circuits for input and output of data between a sense amplification circuit and an input and output circuit, and a data line connected to the plurality of data latch circuits. The data latch circuit includes a data storage portion that temporarily stores data input and output between the sense amplification circuit and the input and output circuit, and at least one of an N-channel type MOS (Metal Oxide Semiconductor) transistor and a P-channel type MOS transistor provided between the data storage portion and the data line. At least one of the N-channel type MOS transistor and the P-channel type MOS transistor is multiplied. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing a schematic configuration of a storage system of the embodiments.

[0008] Figure 2 is a block diagram showing a schematic configuration of a semiconductor memory device of the embodiments.

[0009] Figure 3 is a circuit diagram showing a configuration of the semiconductor memory device of the embodiments.

[0010] Figure 4 is a block diagram showing a schematic configuration of a sense amplification unit of the embodiments.

[0011] Figure 5 is a block diagram showing a schematic configuration of a sense amplifier and an input and output circuit of the embodiments.

[0012] Figure 6 is a circuit diagram showing a configuration of a data latch circuit of the embodiment.

[0013] Figure 7 is a cross-sectional view showing a cross-sectional structure of a semiconductor storage device of the embodiment.

[0014] Figure 8 is a diagram schematically showing a planar structure of a data latch circuit periphery of a semiconductor storage device of the embodiment.

[0015] Figure 9 is a diagram schematically showing a planar structure of a data latch circuit periphery of a semiconductor storage device of the reference example.

[0016] Figure 10 is a circuit diagram showing an operation example of a data latch circuit of the embodiment.

[0017] Figure 11 is a circuit diagram showing an operation example of a data latch circuit of the embodiment.

[0018] Figure 12 is a circuit diagram showing an operation example of a data latch circuit of the embodiment.

[0019] Figure 13 is a circuit diagram showing an operation example of a data latch circuit of the embodiment.

[0020] Figure 14 is a circuit diagram showing an operation example of a data latch circuit of the embodiment.

[0021] Figure 15 is a circuit diagram showing a configuration of a data latch circuit of the reference example.

[0022] Figure 16 is a diagram schematically showing a planar structure of a data latch circuit periphery of a semiconductor storage device of the first modification example.

[0023] Figure 17 is a diagram schematically showing a planar structure of a data latch circuit periphery of a semiconductor storage device of the first modification example.

[0024] Figure 18 is a circuit diagram showing a part of a configuration of a data latch circuit of the second modification example.

[0025] Figure 19 is a circuit diagram showing a part of a configuration of a data latch circuit of the second modification example.

[0026] Figure 20 is a circuit diagram showing a part of a configuration of a data latch circuit of the third modification example.

[0027] Figure 21 is a circuit diagram showing a part of the configuration of the data latch circuit of the 4th modification example.

[0028] Figure 22 is a circuit diagram showing a part of the configuration of the data latch circuit of the 4th modification example.

[0029] Figure 23 is a circuit diagram showing a part of the configuration of the data latch circuit of the 4th modification example. DETAILED DESCRIPTION

[0030] Embodiments will be described below with reference to the accompanying drawings. In order to make the description easy to understand, the same reference numerals are used, wherever possible, to designate the same elements throughout the various drawings. The description of the same elements is omitted in some cases.

[0031] <EMBODIMENT>

[0032] (Configuration of Storage System)

[0033] As shown in FIG. 1, the storage system of the present embodiment is provided with a memory controller 1 and a semiconductor storage device 2. The semiconductor storage device 2 is a nonvolatile storage device configured as a NAND (Not And) type flash memory. The storage system is connectable to a host. The host is, for example, an electronic device such as a personal computer or a mobile terminal. Further, although only one semiconductor storage device 2 is illustrated in the drawing, a plurality of semiconductor storage devices 2 are actually provided in the storage system. Figure 1 Figure 1

[0034] The memory controller 1 controls the operation of writing data to the semiconductor storage device 2 in accordance with a write request from the host. In addition, the memory controller 1 controls the operation of reading data from the semiconductor storage device 2 in accordance with a read request from the host.

[0035] Between the memory controller 1 and the semiconductor storage device 2, various signals such as a chip enable signal / CE, a ready-busv signal / RB, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal RE, / RE, a write protect signal / WP, a signal DQ<7:0> of data, and a data strobe signal DQS, / DQS are transmitted and received.

[0036] ​​A chip enable signal / CE is a signal for enabling the semiconductor storage device 2. A ready / busy signal / RB is a signal for indicating whether the semiconductor storage device 2 is in a ready state or a busy state. The "ready state" means a state in which a command from the outside can be accepted. The "busy state" means a state in which a command from the outside cannot be accepted. An instruction latch enable signal CLE is a signal indicating that the signal DQ<7:0> is an instruction. An address latch enable signal ALE is a signal indicating that the signal DQ<7:0> is an address. A write enable signal / WE is a signal for taking a received signal into the semiconductor storage device 2, and is activated by the memory controller 1 every time an instruction, an address, and data are received. The memory controller 1 instructs the semiconductor storage device 2 to take in the signal DQ<7:0> during a period in which the signal / WE is at an "L" (Low) level.

[0037] A read enable signal RE, / RE is a signal for causing the memory controller 1 to read data from the semiconductor storage device 2. The read enable signal RE, / RE is used to control, for example, the operation timing of the semiconductor storage device 2 at the time of outputting the signal DQ<7:0>. A write protect signal / WP is a signal for instructing the semiconductor storage device 2 to prohibit data writing and deletion. The signal DQ<7:0> is the entity of data which is transmitted and received between the semiconductor storage device 2 and the memory controller 1, including an instruction, an address, and data. A data strobe signal DQS, / DQS is a signal for controlling the input / output timing of the signal DQ<7:0>.

[0038] The memory controller 1 has a RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. They are connected to each other through an internal bus 16.

[0039] The host interface 13 outputs a request and user data (write data) and the like received from a host to the internal bus 16. In addition, the host interface 13 transmits user data read from the semiconductor storage device 2 and a response from the processor 12 and the like to the host.

[0040] The memory interface 15 controls a process of writing user data and the like to the semiconductor storage device 2 and a process of reading user data and the like from the semiconductor storage device 2 based on an instruction of the processor 12.

[0041] The processor 12 comprehensively controls the memory controller 1. The processor 12 is a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. The processor 12 controls in accordance with a request received from a host via the host interface 13. For example, the processor 12 instructs the memory interface 15 to write user data and a parity code to the semiconductor storage device 2 in accordance with a request from the host. In addition, the processor 12 instructs the memory interface 15 to read out user data and a parity code from the semiconductor storage device 2 in accordance with a request from the host.

[0042] The processor 12 determines a storage area (storage area) of the user data stored in the RAM 11 on the semiconductor storage device 2. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 performs determination of the storage area for data (page data) in a page unit which is a write unit. The user data stored in one page of the semiconductor storage device 2 is also referred to as "cell data" hereinafter. The cell data is generally encoded and stored in the semiconductor storage device 2 in the form of a codeword. In the present embodiment, it is not necessarily encoded. The memory controller 1 can also store the cell data in the semiconductor storage device 2 without encoding, but Figure 1 The configuration in which encoding is performed is shown as an example. In the case where the memory controller 1 does not perform encoding, the page data coincides with the cell data. In addition, one codeword can be generated on the basis of one cell data, or one codeword can be generated on the basis of divided data divided from the cell data. In addition, one codeword can be generated using a plurality of cell data.

[0043] The processor 12 determines the storage area of the semiconductor storage device 2 which is a write destination, cell data by cell data. The storage area of the semiconductor storage device 2 is assigned a physical address. The processor 12 manages the storage area which is the write destination of the cell data using the physical address. The processor 12 specifies the determined storage area (physical address) and instructs the memory interface 15 to write the user data to the semiconductor storage device 2. The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. The processor 12 specifies the physical address corresponding to the logical address in the case where a read request including the logical address is received from the host, and specifies the physical address and instructs the memory interface 15 to read out the user data.

[0044] The ECC circuit 14 encodes the user data stored in the RAM 11 and generates a codeword. In addition, the ECC circuit 14 decodes the codeword read out from the semiconductor storage device 2.

[0045] RAM 11 temporarily stores user data received from the host before storing it in the semiconductor storage device 2, or temporarily stores data read from the semiconductor storage device 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0046] Figure 1 The diagram shows an example configuration of a memory controller 1 including an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the semiconductor memory device 2. Figure 1 The specific composition and configuration of the elements shown are not particularly limited.

[0047] In the event that a write request is received from the host Figure 1 The storage system operates as follows: Processor 12 temporarily stores data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword to memory interface 15. Memory interface 15 writes the input codeword to semiconductor storage device 2.

[0048] When a read request is received from the host Figure 1 The storage system operates as follows: The memory interface 15 inputs the codewords read from the semiconductor storage device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codewords and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0049] (Brief Structure of a Semiconductor Memory Device)

[0050] like Figure 2 As shown, the semiconductor memory device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a line decoder 27, a sense amplifier 28, an input / output pad group 30, a logic control pad group 31, and a power input terminal group 32.

[0051] The memory cell array 21 is the part that stores data. The memory cell array 21 is composed of multiple memory cell transistors associated with multiple bit lines and multiple word lines.

[0052] The input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS, / DQS with the memory controller 1. In addition, the input / output circuit 22 transmits commands and addresses within the signals DQ<7:0> to the register 24. Furthermore, the input / output circuit 22 transmits and receives write data and read data with the sense amplifier 28.

[0053] The logic control circuit 23 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal RE, / RE, and a write protect signal / WP from the memory controller 1. In addition, the logic control circuit 23 transmits a ready / busy signal / RB to the memory controller 1, notifying the outside of the state of the semiconductor memory device 2.

[0054] The register 24 temporarily holds various data. For example, the register 24 holds a command indicating a write operation, a read operation, and a delete operation, and the like. The command is input from the memory controller 1 to the input / output circuit 22, and is transmitted from the input / output circuit 22 to the register 24 to be held. In addition, the register 24 also holds an address corresponding to the command. The address is input from the memory controller 1 to the input / output circuit 22, and is transmitted from the input / output circuit 22 to the register 24 to be held. Furthermore, the register 24 also holds state information indicating the state of operation of the semiconductor memory device 2. The state information is updated by the sequencer 25 at any time according to the state of operation of the memory cell array 21 and the like. The state information is output from the input / output circuit 22 to the memory controller 1 as a status signal according to a request from the memory controller 1.

[0055] The sequencer 25 controls the operation of each section including the memory cell array 21 based on control signals input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23.

[0056] The voltage generating circuit 26 is a section that generates voltages required for each of a write operation, a read operation, and a delete operation of data in the memory cell array 21. The voltages include, for example, voltages applied to a plurality of word lines and a plurality of bit lines of the memory cell array 21, respectively. The operation of the voltage generating circuit 26 is controlled by the sequencer 25.

[0057] The row decoder 27 is a circuit including a group of switches for applying voltages to a plurality of word lines of the memory cell array 21, respectively. The row decoder 27 receives a block address and a row address from the register 24, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the states of the switches of the group of switches to apply a voltage from the voltage generating circuit 26 to the selected word line. The operation of the row decoder 27 is controlled by the sequencer 25.

[0058] The sense amplifier 28 is a circuit used to adjust the voltage applied to the bit lines of the memory cell array 21, or to read out the voltage of the bit lines and convert it into data. When reading data, the sense amplifier 28 acquires the data read from the memory cell transistors of the memory cell array 21 to the bit lines and transmits the acquired read data to the input / output circuit 22. When writing data, the sense amplifier 28 transmits the data written via the bit lines to the memory cell transistors. The operation of the sense amplifier 28 is controlled by the sequencer 25.

[0059] The input / output pad group 30 is a portion provided with multiple terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 22. Each terminal is individually configured to correspond to the signals DQ<7:0> and the data strobe signals DQS and / DQS.

[0060] The logic control pad group 31 is a portion provided with multiple terminals for transmitting and receiving signals between the memory controller 1 and the logic control circuit 23. Each terminal is individually configured to correspond to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protect signal / WP, and ready-busy signal / RB.

[0061] The power input terminal group 32 is a portion provided with multiple terminals for receiving the applied voltages required for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltage Vcc, VccQ, Vpp, and the ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage provided externally as the operating power supply, for example, approximately 3.3V. The power supply voltage VccQ is, for example, 1.2V. VccQ is the voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than Vcc, for example, 12V.

[0062] (Circuit configuration of a memory cell array)

[0063] Next, the circuit configuration of the memory cell array 21 will be described.

[0064] like Figure 3 As shown, the storage cell array 21 contains multiple block BLKs. Figure 3 Only one of the multiple block BLKs is shown in the image. The other block BLKs of the storage cell array 21 are configured similarly to those shown in the image. Figure 3 The structures shown are the same.

[0065] like Figure 3As shown, the block BLK includes, for example, 4 string units SU (SU0 to SU3). In addition, each string unit SU includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, 8 memory cell transistors MT (MT0 to MT7) and selection transistors ST1, ST2.

[0066] Further, the number of memory cell transistors MT is not limited to 8, and can be, for example, 32, 48, 64, 96. For example, in order to improve the off characteristics, the selection transistors ST1, ST2 can each be constituted by a plurality of transistors, rather than by a single transistor. Furthermore, a dummy cell transistor can be provided between the memory cell transistor MT and the selection transistors ST1, ST2.

[0067] The memory cell transistors MT are arranged in a manner connected in series between the selection transistor ST1 and the selection transistor ST2. The memory cell transistor MT7 on the one end side is connected to the source of the selection transistor ST1, and the memory cell transistor MT0 on the other end side is connected to the drain of the selection transistor ST2.

[0068] The gates of the selection transistors ST1 of each of the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3, respectively. The gates of the selection transistors ST2 are commonly connected to the same selection gate line SGS among the plurality of string units SU within the same block BLK. The gates of the memory cell transistors MT0 to MT7 within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. That is, the word lines WL0 to WL7 and the selection gate line SGS are common among the plurality of string units SU0 to SU3 within the same block BLK, and the selection gate lines SGD are individually provided for each of the string units SU0 to SU3 even within the same block BLK.

[0069] In the memory cell array 21, n bit lines BL (BL0, BL1,..., BL(n-1)) are provided. "n" is an integer corresponding to the number of NAND strings NS included in one string unit SU. For example, in a case where the semiconductor storage device 2 is configured in a manner that 16 kByte data is written to or read out from the memory cell array 21 as one unit, "n" is 131072 (2 raised to the 17th power). The drains of the selection transistors ST1 of the respective NAND strings NS are connected to the corresponding bit lines BL. The sources of the selection transistors ST2 of the respective NAND strings NS are connected to the source line SL. The source line SL is common to the sources of the plurality of selection transistors ST2 possessed by the block BLK.

[0070] Data stored in multiple memory cell transistors MT located within the same BLK is deleted all at once. On the other hand, data reading and writing are performed uniformly on multiple memory cell transistors MT connected to one word line WL and belonging to one string cell SU.

[0071] Furthermore, in the following explanation, the collection of 1-bit data stored by multiple memory cell transistors MT connected to a word line WL and belonging to a string cell SU is called a "page". Figure 3 In the text, one of the sets consisting of multiple memory cell transistors MT as described above is labeled with the symbol "MG".

[0072] (Composition of the sensing amplifier)

[0073] The sense amplifier 28 includes n sense amplifier circuits associated with each of the n bit lines BL. Figure 4 This represents the circuit configuration of one sensing amplifier circuit SAC out of n sensing amplifier circuits.

[0074] like Figure 4 As shown, the sensing amplifier circuit SAC includes a sensing amplifier section SA and data latch circuits SDL, ADL, BDL, CDL, and XDL. The sensing amplifier section SA and the data latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS to transmit and receive data. More specifically, the data latch circuits SDL, ADL, BDL, and CDL are commonly connected via the LBUS bus, and the data latch circuit XDL is connected to the bus DBUS. The LBUS bus and the DBUS bus are connected via a transistor TRXX. The gate of the transistor TRXX is input with a control signal SW. The control signal SW is generated, for example, by a sequencer 25.

[0075] The sensing amplifier section SA, for example, senses the data read from the corresponding bit line BL during the readout operation and determines whether the read data is "0" or "1". The sensing amplifier section SA includes, for example, a P-channel MOS transistor TR1, N-channel MOS transistors TR2 to TR9, and a capacitor C10.

[0076] One end of a transistor TR1 is connected to a power supply line, and the other end of the transistor TR1 is connected to a transistor TR2. A gate of the transistor TR1 is connected to a node INV in a data latch circuit SDL. One end of the transistor TR2 is connected to the transistor TR1, and the other end of the transistor TR2 is connected to a node COM. A gate of the transistor TR2 is input with a control signal BLX. One end of a transistor TR3 is connected to the node COM, and the other end of the transistor TR3 is connected to a transistor TR4. A gate of the transistor TR3 is input with a control signal BLC. The transistor TR4 is a high-voltage MOS transistor. One end of the transistor TR4 is connected to the transistor TR3. The other end of the transistor TR4 is connected to a corresponding bit line BL. A gate of the transistor TR4 is input with a control signal BLS.

[0077] One end of a transistor TR5 is connected to the node COM, and the other end of the transistor TR5 is connected to a node SRC. A gate of the transistor TR5 is connected to the node INV. One end of a transistor TR6 is connected between the transistor TR1 and the transistor TR2, and the other end of the transistor TR6 is connected to a node SEN. A gate of the transistor TR6 is input with a control signal HLL. One end of a transistor TR7 is connected to the node SEN, and the other end of the transistor TR7 is connected to the node COM. A gate of the transistor TR7 is input with a control signal XXL.

[0078] One end of a transistor TR8 is connected to a ground, and the other end of the transistor TR8 is connected to a transistor TR9. A gate of the transistor TR8 is connected to the node SEN. One end of the transistor TR9 is connected to the transistor TR8, and the other end of the transistor TR9 is connected to a bus line LBUS. A gate of the transistor TR9 is input with a control signal STB. One end of a capacitor C10 is connected to the node SEN. The other end of the capacitor C10 is input with a clock CLK.

[0079] The control signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by the sequencer 25. In addition, the power supply line connected to one end of the transistor TR1 is applied, for example, with an internal power supply voltage of the semiconductor storage device 2, that is, a voltage Vdd, and the node SRC is applied, for example, with a ground voltage of the semiconductor storage device 2, that is, a voltage Vss.

[0080] The data latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold read data. The data latch circuit XDL is connected to the input / output circuit 22, and is used for sensing input and output of data between the sense amplifier circuit SAC and the input / output circuit 22.

[0081] The data latch circuit SDL includes, for example, inverters IV11 and IV12, and transistors TR13 and TR14, which are N-channel MOS transistors. The input node of inverter IV11 is connected to node LAT. The output node of inverter IV11 is connected to node INV. The input node of inverter IV12 is connected to node INV. The output node of inverter IV12 is connected to node LAT. One end of transistor TR13 is connected to node INV, and the other end of transistor TR13 is connected to the bus LBUS. The gate of transistor TR13 is fed with the control signal STI. One end of transistor TR13 is connected to node LAT, and the other end of transistor TR14 is connected to the bus LBUS. The gate of transistor TR14 is fed with the control signal STL.

[0082] For example, the data stored in node LAT is equivalent to the data stored in the data latch circuit SDL. Similarly, the data stored in node INV is equivalent to the inverted data stored in node LAT. The circuit configurations of data latch circuits ADL, BDL, and CDL are, for example, the same as those of data latch circuit SDL, and therefore their descriptions are omitted. Hereinafter, data latch circuits ADL, BDL, and CDL will be collectively referred to as "data latch circuit DL". The circuit configuration of data latch circuit XDL will be described below.

[0083] like Figure 5 As shown, the sensing amplifier 28 has k sensing amplification units SAU (SAU0 to SAU(k-1)). Each sensing amplification unit SAU includes m sensing amplifier sections SA (SA0 to SA(m-1)), m data latch circuits DL (DL0 to DL(m-1)), and m data latch circuits XDL (XDL0 to XDL(m-1)). "m" and "k" are integers that satisfy "m×k=n". For example, "m" is 16 (2 to the power of 4), and "k" is 8192 (2 to the power of 13). In other words, n (131072, 2 to the power of 17) sensing amplification circuits SAC are divided into k (8192, 2 to the power of 13) sensing amplification units SAU, and each sensing amplification unit SAU includes m (16, 2 to the power of 4) sensing amplification circuits SAC.

[0084] m data latch circuits XDL0 to XDL(m-1) are connected to the input / output circuit 22 via m buses XBUS (XBUS0 to XBUS(m-1)). The m buses XBUS0 to XBUS(m-1) are, for example, shared for 32 to 64 multiple sensing amplification units (SAUs). In other words, multiple sensing amplification units (SAUs), for example 32 to 64, are connected to the m buses XBUS0 to XBUS(m-1). These multiple sensing amplification units (SAUs) are connected to the input / output circuit 22 via buses XBUS0 to XBUS(m-1). The buses XBUS0 to XBUS(m-1) connecting these multiple sensing amplification units (SAUs) are grouped together, and multiple groups of buses XBUS0 to XBUS(m-1) are connected to the input / output circuit 22. In this embodiment, the bus XBUS corresponds to a data wiring.

[0085] The input / output circuit 22 includes a data conversion unit 220 and an input / output control unit 221. The data conversion unit 220 and the input / output control unit 221 are interconnected via multiple wiring XL.

[0086] The data conversion unit 220 functions as a serializer during read operations, converting the parallel data transmitted from the data latch circuits XDL0 to XDL(m-1) via buses XBUS0 to XBUS(m-1) into serial signals, and then sending them to the input / output control unit 221 via multiple wirings XL. During write operations, the data conversion unit 220 functions as a deserializer, converting the serial signals transmitted from the input / output control unit 221 via multiple wirings XL into parallel data, and then transmitting them to buses XBUS0 to XBUS(m-1).

[0087] The input / output control unit 221 is a part that controls the serial signal transmission between multiple input / output lines I / O and multiple wiring lines XL.

[0088] (Construction of the data latch circuit XDL)

[0089] Next, the configuration of the data latch circuit XDL will be explained.

[0090] like Figure 6 As shown, the data latch circuit XDL includes TP11-14, TP21, and TP31, which are P-channel MOS transistors, and TN11-13, TN21, TN31, and TN32, which are N-channel MOS transistors.

[0091] The transistors TP11, TP12, TN11, TN12 constitute a cross-connection inverting circuit XIV. That is, the transistors TP11, TN11 constitute a first inverting circuit, connected in series at a node LAT. The respective gates of the transistors TP11, TN11 are connected to a node INV. The node LAT and the node INV function as an output and an input, respectively, of the first inverting circuit. The transistors TP12, TN12 constitute a second inverting circuit, connected in series at the node INV. The respective gates of the transistors TP12, TN12 are connected to the node LAT. The node LAT and the node INV function as an input and an output, respectively, of the second inverting circuit.

[0092] Of the two ends of the current path of the transistor TP11, the end opposite to the end connected to the node LAT is connected to a power supply potential node VDD via a transistor TP13. The power supply potential node VDD is supplied with a power supply potential Vdd. The gate of the transistor TP13 is input with a control signal XLL generated by the sequencer 25. The transistor TP13 functions as a switching circuit turned on / off based on the control signal XLL.

[0093] Of the two ends of the current path of the transistor TP12, the end opposite to the end connected to the node INV is connected to the power supply potential node VDD via a transistor TP14. The gate of the transistor TP14 is input with a control signal XLI generated by the sequencer 25. The transistor TP12 functions as a switching circuit turned on / off based on the control signal XLI.

[0094] Of the two ends of the current path of the transistor TN11, the end opposite to the end connected to the node LAT is connected to a ground potential node VSS via a transistor TN13. The ground potential node VSS is supplied with a ground potential Vss. The gate of the transistor TN13 is input with a control signal XNL generated by the sequencer 25. The transistor TN13 functions as a switching circuit turned on / off based on the control signal XNL.

[0095] Of the two ends of the current path of the transistor TN12, the end opposite to the end connected to the node INV is connected to the ground potential node VSS.

[0096] The transistors TP21, TN21 are connected in parallel between the bus DBUS and the node INV. The gate of the transistor TP21 is input with a control signal XNI generated by the sequencer 25. The gate of the transistor TN21 is input with a control signal XTI generated by the sequencer 25. The transistors TP21, TN21 function as switching circuits turned on / off based on the control signals XNI, XTI.

[0097] The transistors TP31, TN31, TN32 are connected between the bus XBUS and the node LAT. The transistors TN31, TN32 are connected in series. The transistor TP31 is connected in parallel with the series-connected transistors TN31, TN32. The gate of the transistor TP31 is input with the control signal XNL generated by the sequencer 25. The gates of the transistors TN31, TN32 are each input with the control signal XTL generated by the sequencer 25. The transistors TP31, TN31, TN32 function as a switching circuit that is turned on / off based on the control signals XNL, XTL. In the present embodiment, the transistors TN31, TN32 correspond to the multiplexed transistors.

[0098] (Cross-sectional structure of semiconductor storage device)

[0099] As shown in FIG. 2, the semiconductor storage device 2 has a structure in which the peripheral circuit PER and the memory cell array 21 are disposed in this order on a semiconductor substrate 40. Figure 7

[0100] In the memory cell array 21, a plurality of NAND strings NS are formed above a conductor layer 520. The conductor layer 520 is also called a buried source line (BSL) and corresponds to a source line SL. Figure 3

[0101] Above the conductor layer 520, a wiring layer 533 functioning as a select gate line SGS, a plurality of wiring layers 532 functioning as word lines WL, and a wiring layer 531 functioning as a select gate line SGD are laminated. Between the laminated wiring layers 533, 532, 531, an insulating layer not shown is disposed.

[0102] In the memory cell array 21, a plurality of memory holes 534 are formed. The memory hole 534 is a hole that penetrates the wiring layers 533, 532, 531 and the insulating layer not shown therebetween in the up-down direction and reaches the conductor layer 520.

[0103] The portions of the memory hole 534 that cross the laminated wiring layers 533, 532, 531, respectively, function as transistors. Of the plurality of transistors, the transistor located at the portion that crosses the wiring layer 531 functions as a select transistor ST1. Of the plurality of transistors, the transistor located at the portion that crosses the wiring layer 532 functions as a memory cell transistor MT (MT0 to MT7). Of the plurality of transistors, the transistor located at the portion that crosses the wiring layer 533 functions as a select transistor ST2.

[0104] Above the memory hole 534, a wiring layer 616 functioning as a bit line BL is formed. The upper end of the memory hole 534 is connected to the wiring layer 616 via a contact plug 539. ​​

[0105] Along the depth direction of the paper surface of the NAND string NS, a plurality of structures identical to the structure shown in FIG. 6 are arranged. Figure 7 A set of a plurality of NAND strings NS arranged in a row along the depth direction of the paper surface of the NAND string NS forms one string unit SU. Figure 7 Figure 7 A portion of the peripheral circuit PER is arranged between the semiconductor substrate 40 and the conductor layer 520 (source line SL). The peripheral circuit PER is a circuit provided to realize a write operation, a read operation, and a delete operation of data in the memory cell array 21 and the like.

[0106] The sense amplifier 28, the row decoder 27, the voltage generating circuit 26, and the like shown in FIG. 5 become a portion of the peripheral circuit PER. Figure 2

[0107] The peripheral circuit PER includes transistors TR formed on the upper surface of the semiconductor substrate 40, and a plurality of conductors 611 to 615. The conductors 611 to 615 are wiring layers formed of a conductor such as metal. The conductors 611 to 615 are formed so as to be distributed at a plurality of height positions, and are electrically connected to each other via contacts 620 to 623. The contacts 620 to 623 are formed by forming a contact hole so as to penetrate an insulating layer not shown in the up-and-down direction, and filling an electrically conductive material such as tungsten into the inside of the contact hole. The conductor 615 is electrically connected to a wiring layer 616 (bit line BL) via a contact 624.

[0108] Figure 8 A portion of the structure of the peripheral circuit PER of the semiconductor storage device 2, particularly, a planar structure of a portion constituting the data latch circuit XDL is schematically shown. Further, a portion of the structure of the peripheral circuit PER of the semiconductor storage device 2, particularly, a planar structure of a portion constituting the data latch circuit XDL is schematically shown. Figure 8 A planar structure of a portion constituting two data latch circuits XDL1, XDL2 is shown in FIG. 10.

[0109] As shown in FIG. 11, in the semiconductor storage device 2, a source-drain portion LW1, a gate portion LT1, a source-drain portion LW2, a gate portion LT2, a source-drain portion LW3, and a gate portion LT3 are sequentially arranged. Figure 8

[0110] ​​​The source-drain section LW1 is equipped with source-drain sections LW1_1 and LW1_2, which function as the source or drain of each transistor TN31 in the data latch circuits XDL1 and XDL2. Source-drain sections LW1_1 and LW1_2 are connected to the bus XBUS. The gate section LT1 is equipped with gate sections LT1_1 and LT1_2, which function as the gate of each transistor TN31 in the data latch circuits XDL1 and XDL2. Through-holes V31 connected to the gates of transistor TN31 are formed in gate sections LT1_1 and LT1_2, respectively. The source-drain section LW2 is equipped with source-drain sections LW2_1 and LW2_2, which function as the source or drain of each transistor TN31 in the data latch circuits XDL1 and XDL2, and also as the source or drain of transistor TN32.

[0111] In the gate section LT2, gate sections LT2_1 and LT2_2 are configured to function as the gates of transistors TN32 in data latch circuits XDL1 and XDL2, respectively. Through-holes V32 connected to the gates of transistors TN32 are formed in gate sections LT2_1 and LT2_2, respectively. In the source / drain section LW3, source / drain sections LW3_1 and LW3_2 are configured to function as the source or drain of transistors TN32 in data latch circuits XDL1 and XDL2, and also as the source or drain of transistor TN11. Source / drain sections LW3_1 and LW3_2 are connected to node LAT. In the gate section LT3, gate sections LT3_1 and LT3_2 are configured to function as the gates of transistors TN11 in data latch circuits XDL1 and XDL2, respectively.

[0112] When the orientation of each of the LW1, LT1, LW2, LT2, LW3, and LT3 is set to the depth direction Y, the through holes V31 and V32 are arranged on the same straight line parallel to the depth direction Y. A common wiring LTG extending along the depth direction Y is connected to the through holes V31 and V32. The control signal XTL is input from the sequencer 25 to the through holes V31 and V32 via the wiring LTG. In this embodiment, the wiring LTG is equivalent to a common signal line.

[0113] The semiconductor memory device 2 in this embodiment is as follows: Figure 8 As shown, a so-called dual-gate method is employed, meaning the gates of transistor TN31 and transistor TN32 in each data latch circuit XDL1 and XDL2 are located in different parts. In the case of using the dual-gate method, as... Figure 8As shown, the portions LW1_1, LT1_1, LW2_1, LT2_1, LW3_1, and LT3_1 that constitute the data latch circuit XDL1 and the portions LW1_2, LT1_2, LW2_2, LT2_2, LW3_2, and LT3_2 that constitute the other data latch circuit XDL2 are arranged in the lateral direction X.

[0114] On the other hand, in the case of manufacturing the semiconductor memory device 2 as shown in FIG. 2, the transistors TN31 and TN32 that are duplicated can be provided. Figure 9 Figure 9 In the semiconductor memory device 2 of the reference example shown in FIG. 2, the source-drain portion LW1, the gate portion LT1, the source-drain portion LW2, the gate portion LT2, the source-drain portion LW3, the gap portion LG, the source-drain portion LW4, and the gate portion LT3 are arranged in this order.

[0115] The source-drain portion LW1 functions as a source or a drain of each of the transistors TN31 and TN32 of the other data latch circuit XDL2. The source-drain portion LW1 is connected to the node LAT. The gate portion LT1 functions as a gate of each of the transistors TN31 and TN32 of the other data latch circuit XDL2. In the gate portion LT1, the vias V31 and V32 that are connected to the gates of the transistors TN31 and TN32 are provided. The source-drain portion LW2 functions as a source or a drain of each of the transistors TN31 and TN32 of the data latch circuit XDL1 and functions as a source or a drain of each of the transistors TN31 and TN32 of the other data latch circuit XDL2. The source-drain portion LW2 is connected to the bus XBUS.

[0116] The gate portion LT2 functions as a gate of each of the transistors TN31 and TN32 of the data latch circuit XDL1. In the gate portion LT2, the vias V31 and V32 that are connected to the gates of the transistors TN31 and TN32 are provided. The source-drain portion LW3 functions as a source or a drain of each of the transistors TN31 and TN32 of the data latch circuit XDL1. The source-drain portion LW3 is connected to the node LAT. The gap portion LG is provided between the source-drain portion LW3 and the source-drain portion LW4.

[0117] ​In the source-drain portion LW4, a source-drain portion LW4_1, LW4_2 functioning as the source or drain of each of the transistors TN11 of the data latch circuit XDL1, XDL2 is provided. The source-drain portion LW4_1 is connected to the source-drain portion LW3 via a wire WW1. The source-drain portion LW4_2 is connected to the source-drain portion LW1 via a wire WW2. The source-drain portions LW4_1, LW4_2 are connected to the node LAT. In the gate portion LT3, a gate portion LT3_1, LT3_2 functioning as the gate of each of the transistors TN11 of the data latch circuit XDL1, XDL2 is provided.

[0118] The semiconductor storage device 2 of this reference example adopts a so-called double via method, that is, two vias V31, V32 are provided in the gate portions LT1, LT2, respectively. In this configuration, in order to prevent the potential of the source-drain portion LW4_2 from changing based on the potential of the source-drain portion LW3, it is necessary to divide the source-drain portion LW3 from the source-drain portion LW4, and form a gap portion LG therebetween. As shown in FIG. 6, in the semiconductor storage device 2 of the present embodiment, such a configuration is not necessary, and thus the semiconductor storage device 2 can be made thin accordingly. Thereby, the chip area can be reduced, and thus the cost can be reduced. Figure 8

[0119] (Action example of the data latch circuit XDL)

[0120] Next, an action example of the data latch circuit XDL will be described.

[0121] - Latching of data -

[0122] When latching data in the data latch circuit XDL, the sequencer 25 causes the data latch circuit XDL to act as shown in FIG. 7. As shown in FIG. 7, the sequencer 25 maintains the control signals XTL, XTI, XLI, XLL at a low level, and maintains the control signals XNL, XNI at a high level. The high level has a potential of a size to turn off the P-channel MOS transistor and turn on the N-channel MOS transistor, for example, the power supply potential Vdd. The low level has a potential of a size to turn on the P-channel MOS transistor and turn on the N-channel MOS transistor, for example, the ground potential Vss. Figure 10 Figure 10 By setting the potential of each of the control signals XNL, XTL, XTI, XLI, XLL, XNI to the above levels, the transistors TP13, TP14, TN13 become in an on state, and the transistors TP21, TN21, TP31, TN31, TN32 become in an off state. In the data latch circuit XDL, the data D is latched in the node LAT via the transistor TN13, and the data D is latched in the node LAT via the transistor TN32.

[0123] Figure 10 ​​​In the present embodiment, the transistors in the on state are surrounded by dotted-line boxes. By the on / off states of the transistors as described above, the nodes LAT, INV are both cut off from both the buses DBUS, XBUS. On the other hand, the cross-coupled inverter circuit XIV is kept at each of the potentials of the nodes LAT, INV because it is connected to the power supply potential node VDD and the ground potential node VSS. That is, the node LAT maintains a high or low potential according to the digital data held by the data latch circuit XDL. The node INV maintains a potential at a level opposite to that of the digital data held by the data latch circuit XDL. Thus, in the present embodiment, the cross-coupled inverter circuit XIV corresponds to a data holding section which temporarily holds the data input and output between the sense amplifier circuit SAC and the input and output circuit 22.

[0124] - Data input from the bus DBUS

[0125] When data is transferred from the bus DBUS to the data latch circuit XDL, the sequencer 25 causes the transistor TRXX to be in the on state by setting the control signal SW shown in Fig. 9 to the high level. For this reason, the bus DBUS has a potential based on the data which should be transferred to the data latch circuit XDL. If the data which should be transferred is the high level, the potential of the bus DBUS is maintained at the high level. On the other hand, if the data which should be transferred is the low level, the potential of the bus DBUS is maintained at the low level. Figure 4 At the time point when the data input from the bus DBUS to the data latch circuit XDL is started, the data latch circuit XDL is in the state shown in Fig. 10. When the data is input from the bus DBUS to the data latch circuit XDL, the sequencer 25 causes the data latch circuit XDL to act as shown in Fig. 11.

[0126] Figure 10 Figure 11 As shown in Fig. 12, the sequencer 25 maintains the transistors TP31, TN31, TN32 in the off state by maintaining the control signal XNL at the high level and the control signal XTL at the low level. For this reason, the node LAT is cut off from the bus XBUS.

[0127] In addition, the sequencer 25 maintains the transistor TP13 in the on state by maintaining the control signal XLL at the low level. Further, the sequencer 25 maintains the transistor TP14 in the off state by maintaining the control signal XLI at the high level. Figure 11

[0128] In addition, the sequencer 25 maintains the transistor TP13 in the on state by maintaining the control signal XLL at the low level. Further, the sequencer 25 maintains the transistor TP14 in the off state by maintaining the control signal XLI at the high level.

[0129] ​​​In this state, sequencer 25 keeps control signal XNI low and control signal XTI high, while transistors TP21 and TN21 are turned on. Consequently, node INV is connected to bus DBUS, the level of node INV becomes the level of bus DBUS, and the level of node LAT becomes the opposite of the level of bus DBUS. That is, if the potential of bus DBUS is high, the potential of node INV becomes high, and the level of node LAT becomes low. Thus, high-level data on bus DBUS is transmitted to the data latch circuit XDL. Conversely, if the potential of bus DBUS is low, the potential of node INV becomes low, and the level of node LAT becomes high. Thus, low-level data on bus DBUS is transmitted to the data latch circuit XDL.

[0130] - Data output to the XBUS bus -

[0131] At the moment when data output to the XBUS bus begins, the data latch circuit XDL exhibits... Figure 10 The state shown. When outputting data from the data latch circuit XDL to the bus XBUS, the sequencer 25 causes the data latch circuit XDL to... Figure 12 As shown in the diagram.

[0132] like Figure 12 As shown, sequencer 25 keeps transistors TP21 and TN21 off by keeping control signal XNI high and control signal XTI low. Therefore, node INV is disconnected from the bus DBUS.

[0133] In addition, the sequencer 25 keeps transistors TP13, TP14, and TN13 in the ON state by keeping control signals XLL and XLI at a low level and control signal XNL at a high level.

[0134] In this state, sequencer 25 keeps transistors TN31 and TN32 in the ON state by setting the control signal XTL to ON. Furthermore, since the control signal XNL input to the gate of transistor TP31 has been set to high level as described above, transistor TP31 is also kept in the ON state. Therefore, node LAT is connected to bus XBUS, and the level of node LAT is output to bus XBUS. That is, if the potential of node LAT is high, the potential of bus XBUS remains high, and high-level data is transmitted from data latch circuit XDL to bus XBUS. On the other hand, if the potential of node LAT is low, the potential of bus XBUS remains low, and low-level data is transmitted from data latch circuit XDL to bus XBUS.

[0135] - Data input from XBUS bus -

[0136] At the moment when data begins to be input from the XBUS bus, the data latch circuit XDL exhibits... Figure 10 The state shown. When data is input from the XBUS bus to the data latch circuit XDL, the sequencer 25 causes the data latch circuit XDL to... Figure 13 The operation is as shown. Furthermore, the operation of the data latch circuit XDL at this time is essentially the same as when data is input from the bus DBUS to the data latch circuit DL; simply switching the input side to the bus XBUS is sufficient. Therefore, a detailed explanation is omitted.

[0137] - Data output to the DBUS bus -

[0138] At the moment when data output to the DBUS bus begins, the data latch circuit XDL exhibits... Figure 10 The state shown. When outputting data from the data latch circuit XDL to the bus DBUS, the sequencer 25 causes the data latch circuit XDL to... Figure 14 The operation is as shown. Furthermore, the operation of the data latch circuit XDL at this time is essentially the same as the operation when outputting data from the data latch circuit XDL to the bus XBUS, simply by switching the output destination to the bus DBUS; therefore, a detailed explanation is omitted.

[0139] (Comparison of the data latch circuit XDL in the reference example with the data latch circuit XDL in this embodiment)

[0140] Figure 15 This shows the circuit diagram of the data latch circuit XDL for the reference example. (Comparison) Figure 15 The reference example shown has a data latch circuit XDL and Figure 6 As can be seen from the data latch circuit XDL of this embodiment, the data latch circuit XDL of this embodiment has two transistors TN31 and TN32, while the data latch circuit XDL of the reference example only has one transistor TN31. In the configuration of the data latch circuit XDL of the reference example, if an open-circuit fault occurs in the via connected to the gate of transistor TN31 or in the wiring connected to the via, not only will the operation of the data latch circuit XDL become unstable, but there is also a risk that the sensing amplification unit SAU, including the faulty data latch circuit XDL, and other sensing amplification units SAU connected to the data latch circuit XDL via the bus XBUS, will become unusable.

[0141] In detail, manufacturing such as Figure 7In the semiconductor memory device 2 shown, during the steps of connecting the via to the gate of the transistor TN31 and connecting the wiring to the via, an open-circuit fault may occur in the via or the wiring. If an open-circuit fault occurs in the via or wiring connected to the gate, the gate of the transistor TN31 will float, making it impossible to control the gate voltage. In this case, the gate voltage of the transistor TN31 becomes a very unstable voltage because it is determined by charge sharing from adjacent signals transmitted near the transistor TN31. The condition of the adjacent signals changes constantly, so eventually it will be impossible to control the switching on / off of the transistor TN31.

[0142] When data is latched in the data latch circuit XDL, transistor TN13 should ideally remain off. However, as described above, if the on / off state of transistor TN13 cannot be controlled, a so-called continuity failure may occur even when data is latched, meaning transistor TN13 may become on unexpectedly. On the other hand, when data is latched, the control signal XNL is set high to turn off transistor TP31, thus turning transistor TN13 on. Therefore, if transistor TN13 becomes on unexpectedly, there is a risk that the bus XBUS may connect to the ground potential node VSS. In other words, the bus XBUS connected to the data latch circuit XDL, which has a continuity failure transistor TN13, may unexpectedly become ground potential.

[0143] like Figure 5 As shown, for example, the data latch circuits XDL0 of multiple sensing amplification units (SAUs) are connected to a common bus XBUS. Therefore, if a continuity failure occurs in the data latch circuit XDL0 of one of the sensing amplification units (SAUs) due to transistor TN13, forcibly switching the bus XBUS to ground when other data latch circuits XDL0 that have not experienced a continuity failure are required to transmit data to the bus XBUS may result in inadequate data transmission. Consequently, not only the data latch circuit XDL0 with the continuity failure of transistor TN13, but all data latch circuits XDL0 sharing the bus XBUS with it will become unusable.

[0144] In addition, all the sensing amplifier circuits SAC0 to SAC(m-1) that share the DBUS bus with a certain data latch circuit XDL are controlled as a whole. Therefore, if the data latch circuit XDL experiences a circuit failure due to a circuit failure in transistor TN13 and its operation becomes unstable, all the sensing amplifier circuits SAC0 to SAC(m-1) that share the DBUS bus with the data latch circuit XDL may also become unusable.

[0145] In view of this point, the data latch circuit XDL of the present embodiment has, as shown in Figure 6 Fig. 16, two transistors TN31, TN32 as transistors corresponding to the control signal XTL. According to this configuration, even if one transistor TN31 has a short-circuit failure, as long as the other transistor TN32 is normal, the bus XBUS will not be shifted to the ground potential at a timing other than that intended. That is, even if either of the transistors TN31, TN32 has a short-circuit failure, the operation of the data latch circuit XDL can be ensured by the normal other transistor. Therefore, the robustness of data input / output can be improved.

[0146] (First Variation)

[0147] As a method of connecting the via hole V31 of the transistor TN31 and the via hole V32 of the transistor TN32 to the wiring, a method different from that shown in Figure 8 may also be employed.

[0148] For example, as shown in Figure 16 , different wirings LTG1, LTG2 can be connected to the via hole V31 of the transistor TN31 and the via hole V32 of the transistor TN32, respectively. In this configuration, the control signal XTL is input from the sequencer 25 to the wirings LTG1, LTG2, respectively.

[0149] Alternatively, as shown in Figure 17 , the via hole V31 of the transistor TN31 and the via hole V32 of the transistor TN32 can be arranged so as not to overlap in the depth direction Y. In this configuration, when the wirings LTG1, LTG2 are connected to the via hole V31 of the transistor TN31 and the via hole V32 of the transistor TN32, respectively, these wirings LTG1, LTG2 do not overlap. Therefore, as shown in Figure 16 , either of the wirings LTG1, LTG2 need not be bent. In this variation, the wirings LTG1, LTG2 correspond to individual signal lines.

[0150] (Second Variation)

[0151] The data latch circuit XDL of this variation has the configuration shown in Figure 18 . As shown in Figure 18 , in this data latch circuit XDL, between the bus XBUS and the node LAT, two transistors TP31, TP32 which are P-channel MOS transistors, and a transistor TN31 which is an N-channel MOS transistor are connected. The transistors TP31, TP32 are connected in series. The transistor TN31 is connected in parallel with the series-connected transistors TP31, TP32. According to this configuration, even if either of the transistors TP31, TP32 has a failure, the operation of the data latch circuit XDL can be ensured by the normal other transistor.

[0152] Alternatively, the data latch circuit XDL can also have Figure 19 The structure shown. (As illustrated) Figure 19 As shown, in the data latch circuit XDL, two CMOS transistors, TC31 and TC32, are connected between the bus XBUS and the node LAT. Transistor TC31 has an N-channel MOS transistor TN31 and a P-channel MOS transistor TP31. Similarly, transistor TC32 has an N-channel MOS transistor TN32 and a P-channel MOS transistor TP32. The N-channel MOS transistors TN31 and TN32 are connected in series. The P-channel MOS transistors TP31 and TP32 are also connected in series.

[0153] According to this configuration, even if either transistor TC31 or TC32 fails, the operation of the data latch circuit XDL can be ensured by the other normal transistor.

[0154] (Example 3)

[0155] like Figure 20 As shown, in the data latch circuit XDL of this variation, transistors TN31 and TN32 are connected in series with transistor TN33, which is an N-channel transistor. With this configuration, even if one or two of the three transistors TN31, TN32, and TN33 fail, the operation of the data latch circuit XDL can be ensured by the remaining transistors.

[0156] Furthermore, N-channel MOS transistors can be multiplexed to a degree of 3 or higher. Alternatively, P-channel MOS transistors, which are not N-channel MOS transistors, can also be multiplexed to a degree of 3 or higher.

[0157] (Example 4)

[0158] The data latch circuit XDL in this variation example has... Figure 21 The structure shown. (As illustrated) Figure 21 As shown, in this data latch circuit XDL, three N-channel transistors, TN31, TN32, and TN33, are connected in series. The gates of transistors TN31 and TN32 are input to a control signal XTL. The gate of transistor TN32 is input to a control signal XTLL, which is different from the control signal XTL. In this variation, transistors TN31, TN32, and TN33 are equivalent to multiplexed transistors, with TN31 and TN32 equivalent to the first transistor and TN33 equivalent to the second transistor. Furthermore, the control signal XTL is equivalent to the first signal, and the control signal XTLL is equivalent to the second signal.

[0159] In addition, in the semiconductor memory device 2, there is suchFigure 8 In the case of the configuration shown in FIG. 8, for example, when an open failure occurs in the middle portion P1 of the wiring LTG, there is a possibility that the gates of the transistors TN31 and TN32 each float. In this case, although the transistors TN31 and TN32 are provided in duplicate, there is a possibility that both of the transistors TN31 and TN32 have a pass failure.

[0160] In view of this point, if the configuration shown in FIG. 9 is employed, even when both of the transistors TN31 and TN32 have a pass failure, the operation of the data latch circuit XDL can be ensured by controlling the on / off of the transistor TN33 using the control signal XTLL. Thus, the robustness of the data input / output can be further improved. Figure 21

[0161] Further, the data latch circuit XDL can also have the configuration shown in FIG. 10. As shown in FIG. 10, in this data latch circuit XDL, the gates of the transistors TN31 and TN33 are input with the control signal XTL, and the gate of the transistor TN32 is input with a different control signal XTLL. In this modification example, the transistors TN31 and TN33 correspond to the first transistors, and the transistor TN32 corresponds to the second transistor. Figure 22 Figure 22 Alternatively, the data latch circuit XDL can also have the configuration shown in FIG. 11. As shown in FIG. 11, in this data latch circuit XDL, the four transistors TN31, TN32, TN33, and TN34 are connected in series. The gates of the transistors TN31 and TN34 are input with the control signal XTL, and the gates of the transistors TN32 and TN33 are input with a different control signal XTLL. In this modification example, the transistors TN31 and TN34 correspond to the first transistors, and the transistors TN32 and TN33 correspond to the second transistors.

[0162] Alternatively, the data latch circuit XDL can also have the configuration shown in FIG. 11. As shown in FIG. 11, in this data latch circuit XDL, the four transistors TN31, TN32, TN33, and TN34 are connected in series. The gates of the transistors TN31 and TN34 are input with the control signal XTL, and the gates of the transistors TN32 and TN33 are input with a different control signal XTLL. In this modification example, the transistors TN31 and TN34 correspond to the first transistors, and the transistors TN32 and TN33 correspond to the second transistors. Figure 23 Figure 23 If the configuration shown in FIG. 12 and FIG. 13 is employed, the same or similar effects and advantages as those of the configuration shown in FIG. 8 can be obtained.

[0163] If the configuration shown in FIG. 12 and FIG. 13 is employed, the same or similar effects and advantages as those of the configuration shown in FIG. 8 can be obtained. Figure 22 Figure 23 If the configuration shown in FIG. 12 and FIG. 13 is employed, the same or similar effects and advantages as those of the configuration shown in FIG. 8 can be obtained. Figure 21

[0164] <Other Embodiments>

[0165] The present application is not specifically limited as described above.

[0166] As shown in FIG. 14 and FIG. 15, it is sufficient that the semiconductor storage device 2 be configured to have at least one of the N-channel MOS transistor and the P-channel MOS transistor provided in multiple numbers between the bus XBUS and the node LAT. Figure 6 Figures 18-23

[0167] ​​​​​​​The present application includes those obtained by making appropriate design changes to the embodiments described above as long as they have the features of the present application. The elements, arrangement, conditions, shape, etc. of each of the embodiments are not limited to those described above and can be appropriately changed. Each of the elements of each of the embodiments can be appropriately combined as long as there is no technical contradiction.

[0168] [Explanation of symbols]

[0169] 2 semiconductor storage device

[0170] 22 input / output circuit

[0171] LTG, LTG1, LTG2 signal line

[0172] SAC sense amplifier circuit

[0173] TN31, TN32, TN33, TN34 N-channel MOS transistor

[0174] TP31, TP32 P-channel MOS transistor

[0175] XBUS bus (data line)

[0176] XDL data latch circuit

[0177] XIV inverter circuit (data holding section)

Claims

1. A semiconductor memory device, comprising: Multiple data latch circuits are used to sense the input and output of data between the amplifier circuit and the input / output circuit; and Data wiring is connected to multiple of the aforementioned data latch circuits; and The data latch circuit includes: The data storage unit temporarily stores the data input and output between the sensing amplification circuit and the input / output circuit; and At least one of an N-channel MOS transistor and a P-channel MOS transistor is disposed between the data storage section and the data wiring; At least one of the N-channel MOS transistor and the P-channel MOS transistor is multiplexed.

2. The semiconductor memory device according to claim 1, wherein At least one of the N-channel MOS transistor and the P-channel MOS transistor is multiplexed with a multiplication factor of 3 or more.

3. The semiconductor memory device according to claim 1 or 2, wherein When at least one of the N-channel MOS transistor and the P-channel MOS transistor is configured as a multiplexed transistor... The multiplexed transistor includes: The first transistor has its gate input with the first signal; and The gate of the second transistor is input with a second signal that is different from the first signal.

4. The semiconductor memory device according to claim 1 or 2, wherein The gates of the multiplexed transistors in the N-channel MOS transistor and the P-channel MOS transistor are connected to a common signal line.

5. The semiconductor memory device according to claim 1 or 2, wherein Each of the multiplexed transistors in at least one of the N-channel MOS transistors and the P-channel MOS transistors has an individual signal line connected to its gate.

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