Semiconductor structure and method of forming

Abstract

The application provides a semiconductor structure and a forming method. The semiconductor structure comprises a SiC substrate, a SiC epitaxial layer on a first surface of the SiC substrate, a body region extending from a part of the surface of the SiC epitaxial layer into the SiC epitaxial layer, a source trench contact hole structure on a side wall of the body region and extending from the surface of the SiC epitaxial layer into the SiC epitaxial layer or the SiC substrate, the source trench contact hole structure comprising a conductive layer and an insulating layer on a side wall and a bottom of the conductive layer, a source region in the body region, a heavy body region in the body region between the source region and the source trench contact hole structure, a gate structure on a part of the source region, the body region and the SiC epitaxial layer, a source electrode on the source trench contact hole structure, the heavy body region, a part of the source region and the gate structure, and a drain electrode on a second surface of the SiC substrate. The application can improve the performance of a SiC MOSFET device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming it. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, has been widely studied due to its wide bandgap, high critical breakdown field strength, high thermal conductivity, and high electron saturation drift velocity. It is expected to replace silicon (Si) devices and second-generation semiconductor devices in high-temperature, high-frequency, and high-power applications. Furthermore, since SiC is the only wide-bandgap semiconductor material that can be directly oxidized to silicon dioxide (SiO2), this will simplify the fabrication process of metal-oxide-semiconductor field-effect transistors (MOSFETs) using SiC. Therefore, SiC MOSFET devices have attracted considerable attention.

[0003] However, the structure of SiC MOSFET devices still needs improvement to enhance their performance. Summary of the Invention

[0004] The technical problem to be solved by this application is to improve the structure of SiC MOSFET devices in order to improve their performance.

[0005] To address the aforementioned technical problems, this application provides a semiconductor structure comprising: a SiC substrate, the SiC substrate including opposing first and second surfaces, and a SiC epitaxial layer comprising the first surface of the SiC substrate; a body region extending from a portion of the surface of the SiC epitaxial layer into the SiC epitaxial layer; and a source trench contact structure located on the sidewall of the body region and extending from the surface of the SiC epitaxial layer into the SiC epitaxial layer or the SiC substrate, the source trench contact structure comprising a conductive layer and an insulating layer located on the sidewall and bottom of the conductive layer, wherein the insulating layer covers... The substrate comprises at least two of the following layers: a SiC crystal layer, a metal salt layer, and a silicon dioxide layer, wherein the doping type of the SiC crystal layer and the body region is the same as the metal ion type in the metal salt layer, and the metal ion type is N-type or P-type; a source region located in the body region; a heavy body region located in the body region between the source region and the source trench contact hole structure; a gate structure located on a portion of the source region, the body region, and the SiC epitaxial layer; a source electrode located on the source trench contact hole structure, the heavy body region, a portion of the source region, and the gate structure; and a drain electrode located on the second surface of the SiC substrate.

[0006] In some embodiments of this application, the insulating layer includes at least one of a metal salt layer and a silicon dioxide layer and a SiC crystal layer, wherein the SiC crystal layer is in contact with the body region, the SiC epitaxial layer and the SiC substrate.

[0007] In some embodiments of this application, the insulating layer includes a metal salt layer, a silicon dioxide layer, and a SiC crystal layer, wherein the metal salt layer is located on the surface of the SiC crystal layer, and the silicon dioxide layer is located on the surface of the metal salt layer.

[0008] In some embodiments of this application, the thickness of the SiC crystal layer and the metal salt layer is 0.1 μm to 0.3 μm, and the thickness of the silicon dioxide layer is 0.1 μm to 0.2 μm.

[0009] In some embodiments of this application, the material of the metal salt layer includes at least one of aluminosilicate, AlTiOx, AlHfOx, and borosilicate.

[0010] In some embodiments of this application, the material of the conductive layer includes polycrystalline silicon.

[0011] In some embodiments of this application, the SiC substrate, the SiC epitaxial layer, and the source region have a first doping type, the body region and the heavy body region have a second doping type, and the first doping type and the second doping type are opposite.

[0012] This application also provides a method for forming a semiconductor structure, comprising: providing a SiC substrate, the SiC substrate including opposing first and second surfaces, and a SiC epitaxial layer including the first surface of the SiC substrate; forming a body region extending from a portion of the surface of the SiC epitaxial layer into the SiC epitaxial layer; forming a source trench contact hole structure extending from the surface of the SiC epitaxial layer into the SiC epitaxial layer or the SiC substrate in the sidewalls of the body region, wherein the source trench contact hole structure includes a conductive layer and an insulating layer located on the sidewalls and bottom of the conductive layer, wherein the insulating layer includes a SiC crystal layer and a metal layer. The substrate comprises at least two of a salt layer and a silicon dioxide layer, wherein the doping type of the SiC crystal layer and the body region is the same as the metal ion type in the metal salt layer, and the metal ion type is N-type or P-type; a source region, a heavy body region, and a gate structure are formed, wherein the source region is located in the body region, the heavy body region is located in the body region between the source region and the source trench contact hole structure, and the gate structure is located on a portion of the source region, the body region, and the SiC epitaxial layer; a source electrode is formed on the source trench contact hole structure, the heavy body region, a portion of the source region, and the gate structure, and a drain electrode is formed on the second surface of the SiC substrate.

[0013] In some embodiments of this application, the method of forming the source trench contact hole structure includes: forming a contact hole extending from the surface of the SiC epitaxial layer to the SiC epitaxial layer or the SiC substrate on the sidewall of the body region; forming the insulating layer on the sidewall and bottom of the contact hole; forming the conductive layer on the surface of the insulating layer, wherein the conductive layer fills the contact hole.

[0014] In some embodiments of this application, the insulating layer includes at least one of a metal salt layer and a silicon dioxide layer, and a SiC crystal layer; wherein the method of forming the SiC crystal layer includes: forming an α-SiC layer on the sidewall and bottom of the contact hole; and doping the α-SiC layer with impurity ions to transform the α-SiC layer into a SiC crystal layer.

[0015] In some embodiments of this application, the α-SiC layer is formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the gases used in the CVD or ALD process include SiH4, C3H8, and TMS, and the temperature is 300°C to 800°C.

[0016] In some embodiments of this application, the insulating layer comprises a SiC crystal layer and a metal salt layer, or the insulating layer comprises a SiC crystal layer, a metal salt layer, and a silicon dioxide layer; wherein the method for converting the α-SiC layer into a SiC crystal layer includes: forming a metal salt layer on the surface of the α-SiC layer; and using an annealing process to diffuse some of the metal ions in the metal salt layer into the α-SiC layer, thereby converting the α-SiC layer into a SiC crystal layer.

[0017] In some embodiments of this application, the method of forming the source region, the heavy body region, and the gate structure includes: forming a gate structure on a portion of the surface of the body region and on the surface of the SiC epitaxial layer between the body regions; forming a source region in the body regions on both sides of the gate structure, wherein the source region further extends below a portion of the gate structure; and forming a heavy body region in the body region between the source region and the source trench contact hole structure.

[0018] Compared with the prior art, the semiconductor structure and formation method of the present application have the following advantages:

[0019] The semiconductor structure of this application has a source trench contact hole structure extending from the surface of the SiC epitaxial layer to the SiC epitaxial layer or SiC substrate on the sidewall of the body region. This source trench contact hole structure can improve the electric field and protect the gate structure from its influence. The source trench contact hole structure includes a conductive layer and insulating layers located on the sidewalls and bottom of the conductive layer. The insulating layer includes at least two of the following: a SiC crystal layer, a metal salt layer, and a silicon dioxide layer. The SiC crystal layer and the body region have the same doping type. When the SiC crystal layer contacts the body region, a deeper electric field can be controlled. When the metal salt layer is located in the middle of the insulating layer, metal ions in the metal salt layer can diffuse to the layers on both sides. Therefore, the metal salt layer can provide impurity ions for the formation of the SiC crystal layer. The silicon dioxide layer can prevent the metal ions from diffusing into the conductive layer. Therefore, the structure of the insulating layer is not only beneficial to the fabrication process but also to the improvement of device performance.

[0020] The semiconductor structure formation method of this application can achieve doping and transformation of the SiC crystal layer by diffusion of metal ions in the metal salt layer when forming the insulating layer of the source trench contact hole structure, without the need for additional ion implantation process, which simplifies the process steps and avoids lattice damage caused by ion implantation process. Attached Figure Description

[0021] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0022] Figures 1 to 8 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in the embodiments of this application. Detailed Implementation

[0023] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0024] refer to Figure 8This application provides a semiconductor structure including a SiC substrate 100, a SiC epitaxial layer 200, a body region 300, a source trench contact structure, a gate structure 500, a source region 600, a heavy body region 700, a source electrode 800, and a drain electrode 900. The SiC substrate 100 can be made of 4H-SiC, 6H-SiC, 3C-SiC, or 15R-SiC, etc., and can be heavily doped, for example, with a doping concentration of 1E18cm⁻¹. -3 ~1E20cm -3 (i.e., 1×10) 18 cm -3 1×10 20 cm -3 The SiC substrate 100 can be N-type doped or P-type doped, with the specific doping type depending on the device type (e.g., N-type MOSFET or P-type MOSFET). This embodiment uses N-type doping as an example. The SiC substrate 100 includes a first surface 101 and a second surface 102 opposite to each other. The SiC epitaxial layer 200 is formed on the first surface 101. The doping type of the SiC epitaxial layer 200 is the same as that of the SiC substrate 100, and it has a first doping type. The doping concentration of the SiC epitaxial layer 200 can be lower than that of the SiC substrate 100; for example, the doping concentration of the SiC epitaxial layer 200 can be 1E14cm⁻¹. -3 Up to 1E16cm -3 .

[0025] The body region 300 extends from a portion of the surface of the SiC epitaxial layer 200 into the SiC epitaxial layer 200, and the body region 300 has a discrete structure, separated by the SiC epitaxial layer 200. The body region 300 has a second doping type opposite to the first doping type, for example, the body region 300 is p-type doped.

[0026] The source trench contact hole structure is located on the sidewall of the body region 300 and extends from the surface of the SiC epitaxial layer 200 into the SiC epitaxial layer 200 or the SiC substrate 100. The source trench contact hole structure can improve the electric field and protect the gate structure 500 from the influence of the electric field. The deeper the source trench contact hole structure, the stronger its ability to improve the electric field. This embodiment of the application uses the example of the source trench contact hole structure extending into the SiC substrate 100. The source trench contact hole structure includes a conductive layer 420 and an insulating layer 410 located on the sidewall and bottom of the conductive layer 420. The material of the conductive layer 420 may include polycrystalline silicon. The insulating layer 410 includes at least two of the following: a SiC crystal layer, a metal salt layer, and a silicon dioxide layer. The SiC crystal layer refers to a film layer with SiC crystal as the constituent material or as the main material. The metal salt layer refers to a film layer with metal salt as the constituent material or as the main material. The silicon dioxide layer refers to a film layer with silicon dioxide as the constituent material or as the main material. The doping type of the SiC crystal layer and the body region 300 is the same as the metal ion type in the metal salt layer, and the metal ion type is N-type or P-type. In this embodiment, the SiC crystal layer and the body region 300 are P-type doped, and the metal ion type in the metal salt layer is also P-type.

[0027] When the insulating layer 410 comprises at least one of a metal salt layer and a silicon dioxide layer, and a SiC crystal layer, the SiC crystal layer is located on the outermost side of the insulating layer 410. That is, the SiC crystal layer is in contact with the bulk region 300, the SiC epitaxial layer 200, and the SiC substrate 100. Because the SiC crystal layer is in contact with the bulk region 300, a deeper electric field can be controlled. When the insulating layer 410 comprises a metal salt layer, a silicon dioxide layer, and a SiC crystal layer, the stacking order is SiC crystal layer, metal salt layer, and silicon dioxide layer, meaning the metal salt layer is located on the surface of the SiC crystal layer, and the silicon dioxide layer is located on the surface of the metal salt layer. Because aluminum ions are present in the metal salt layer, these ions diffuse outwards during annealing. Therefore, when the metal salt layer is located in the middle layer, metal ions diffuse into the layers on both sides. Thus, the silicon dioxide layer on the surface of the metal salt layer prevents the metal ions from diffusing into the conductive layer 420. Meanwhile, in some embodiments, the SiC crystal layer is formed by doping an amorphous SiC layer (α-SiC layer) with N-type or P-type impurity ions. Metal ions from the metal salt layer can diffuse into the α-SiC layer, thus completing the transformation of the α-SiC layer into the SiC crystal layer. Therefore, the stacking order of the SiC crystal layer, the metal salt layer, and the silicon dioxide layer is not only beneficial for the fabrication process but also for improving device performance.

[0028] The material of the metal salt layer may include at least one of aluminosilicate, AlTiOx, AlHfOx, and borosilicate. Aluminum ions and / or boron ions in the metal salt layer can diffuse into the α-SiC layer, transforming α-SiC into SiC crystals.

[0029] The thickness of the SiC crystal layer and the metal salt layer can be 0.1 μm to 0.3 μm, and the thickness of the silicon dioxide layer can be 0.1 μm to 0.2 μm. When the film layer combination of the insulating layer 410 is different, the film layer thickness also varies. In some embodiments, the insulating layer 410 includes a SiC crystal layer and a metal salt layer, wherein the thickness of the SiC crystal layer can be 0.1 μm to 0.3 μm, and the thickness of the metal salt layer can be 0.1 μm to 0.2 μm. In some embodiments, the insulating layer 410 includes a SiC crystal layer and a silicon dioxide layer, wherein the thickness of the SiC crystal layer can be 0.1 μm to 0.3 μm, and the thickness of the silicon dioxide layer can be 0.1 μm to 0.2 μm. In some embodiments, the insulating layer 410 includes a metal salt layer and a silicon dioxide layer, wherein the thickness of the metal salt layer can be 0.1 μm to 0.3 μm, and the thickness of the silicon dioxide layer can be 0.1 μm to 0.2 μm. In some embodiments, the insulating layer 410 includes a SiC crystal layer, a metal salt layer, and a silicon dioxide layer. The thickness of the SiC crystal layer can be 0.1 μm to 0.3 μm, the thickness of the metal salt layer can be 0.1 μm to 0.2 μm, and the thickness of the silicon dioxide layer can be 0.1 μm to 0.2 μm.

[0030] The source region 600 is located within the body region 300, and the surface of the source region 600 is flush with the top surface of the body region 300. The source region 600 has a first doping type. The heavy body region 700 is located within the body region 300 between the source region 600 and the source trench contact hole structure, and the surface of the heavy body region 700 is flush with the top surface of the body region 300. The bottom surface of the heavy body region 700 may also be flush with the bottom surface of the source region 600. The heavy body region 700 has a second doping type, and the doping concentration of the heavy body region 700 is higher than that of the body region 300 to reduce contact resistance.

[0031] The gate structure 500 is located on a portion of the source region, the body region 300, and the SiC epitaxial layer 200. The gate structure 500 may include a gate dielectric layer and a gate layer located on the surface of the gate dielectric layer. The material of the gate dielectric layer may include silicon dioxide, silicon nitride, silicon oxynitride, etc., and the gate layer may include polysilicon.

[0032] The source electrode 800 is located on the source trench contact hole structure, the heavy body region 700, part of the source region 600 and the gate structure 500, and the drain electrode 900 is located on the second surface 102 of the SiC substrate 100.

[0033] This application also provides a method for forming the above-mentioned semiconductor structure, including:

[0034] Step S1: Provide a SiC substrate, the SiC substrate including opposing first and second surfaces, and the first surface of the SiC substrate including a SiC epitaxial layer;

[0035] Step S2: Form a bulk region extending from a portion of the surface of the SiC epitaxial layer into the SiC epitaxial layer;

[0036] Step S3: A source trench contact hole structure is formed on the sidewall of the body region, extending from the surface of the SiC epitaxial layer to the SiC epitaxial layer or the SiC substrate. The source trench contact hole structure includes a conductive layer and an insulating layer located on the sidewall and bottom of the conductive layer. The insulating layer includes at least two of the following: a SiC crystal layer, a metal salt layer, and a silicon dioxide layer. The doping type of the SiC crystal layer and the body region is the same as the metal ion type in the metal salt layer. The metal ion type is N-type or P-type.

[0037] Step S4: Form a source region, a body region, and a gate structure, wherein the source region is located in the body region, the body region is located in the body region between the source region and the source trench contact hole structure, and the gate structure is located on a portion of the source region, the body region, and the SiC epitaxial layer;

[0038] Step S5: Form a source electrode on the source trench contact hole structure, the heavy body region, part of the source region and the gate structure, and form a drain electrode on the second surface of the SiC substrate.

[0039] The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0040] refer to Figure 1 In step S1, a SiC substrate 100 is provided, the SiC substrate 100 having a first doping type, and a SiC epitaxial layer 200 is formed on a first surface 101 of the SiC substrate 100. The SiC epitaxial layer 200 can be formed by an epitaxial growth process. The SiC epitaxial layer 200 also has a first doping type, and the doping concentration of the SiC epitaxial layer 200 is lower than the doping concentration of the SiC substrate 100.

[0041] refer to Figure 2Step S2 is performed to form a body region 300 in the SiC epitaxial layer 200, wherein the body region 300 has a second doping type opposite to that of the SiC substrate 100 and the SiC epitaxial layer 200. The method for forming the body region 300 may include: forming a patterned mask layer on the surface of the SiC epitaxial layer 200, the patterned mask layer defining the location of the body region 300; using the patterned mask layer as a mask, performing ion implantation into the SiC epitaxial layer 200 using an ion implantation process to form the body region 300; and removing the patterned mask layer.

[0042] refer to Figure 3 A contact hole 401 is formed on the sidewall of the body region 300, and the contact hole 401 extends from the surface of the SiC epitaxial layer 200 into the SiC epitaxial layer 200 or the SiC substrate 100. In this embodiment, the extension to the SiC epitaxial layer 200 is used as an example for illustration. The contact hole 401 can be formed by photolithography.

[0043] refer to Figure 4An insulating layer 410 is formed on the sidewalls and bottom of the contact hole 401. In some embodiments, the insulating layer 410 comprises a SiC crystal layer and a metal salt layer. The method for forming the SiC crystal layer may include: forming an α-SiC layer on the sidewalls and bottom of the contact hole 401; and doping the α-SiC layer with impurity ions to transform the α-SiC layer into a SiC crystal layer. The α-SiC layer may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), wherein the gases used in the CVD or ALD process include SiH4, C3H8, and TMS (tetramethyl silane), and the temperature is 300°C to 800°C. The method for doping the α-SiC layer with impurity ions may be ion implantation or diffusion of metal ions from a metal salt layer. In this embodiment, the transformation from the α-SiC layer to the SiC crystal layer is achieved through the diffusion of metal ions in the metal salt layer. Specifically, a metal salt layer, such as an aluminosilicate layer, is first formed on the surface of the α-SiC layer using deposition processes such as chemical vapor deposition, atomic layer deposition, or sputtering. When the aluminosilicate layer is formed using chemical vapor deposition, the deposition gas includes silane, trimethylaluminum, and oxygen, and the ratio of aluminum atoms, silicon atoms, and oxygen atoms in the silane, trimethylaluminum, and oxygen is (20-40):(1-10):(40-60). Then, an annealing process is used to diffuse some of the aluminum ions in the metal salt layer into the α-SiC layer, transforming the α-SiC layer into the SiC crystal layer. In other embodiments, the insulating layer 410 also includes a silicon dioxide layer. After the aluminosilicate layer is formed and annealed, a silicon dioxide layer is also formed on the surface of the metal salt layer using deposition processes such as chemical vapor deposition or atomic layer deposition.

[0044] In some embodiments, the insulating layer 410 includes a SiC crystal layer and a silicon dioxide layer. The method for forming the insulating layer 410 may include: forming an α-SiC layer on the sidewall and bottom of the contact hole 401 using a chemical vapor deposition process or an atomic layer deposition process; doping the α-SiC layer with impurity ions using an ion implantation process to convert the α-SiC layer into a SiC crystal layer; and forming a silicon dioxide layer on the surface of the SiC crystal layer using a deposition process such as chemical vapor deposition or atomic layer deposition.

[0045] In some embodiments, the insulating layer 410 includes a metal salt layer and a silicon dioxide layer, and the method for forming the insulating layer 410 may include: forming a metal salt layer on the sidewall and bottom of the contact hole 401 by a deposition process such as chemical vapor deposition, atomic layer deposition or sputtering; and forming a silicon dioxide layer on the surface of the metal salt layer by a deposition process such as chemical vapor deposition or atomic layer deposition.

[0046] refer to Figure 5 A conductive layer 420 is formed on the surface of the insulating layer 410, and the conductive layer 420 fills the contact hole 401. The method for forming the conductive layer 420 may include: depositing a conductive material on the surfaces of the insulating layer 410, the body region 300, and the SiC epitaxial layer 200, and filling the contact hole 401 with the conductive material; and using a polishing process to make the surface of the conductive material flush with the surfaces of the body region 300 and the SiC epitaxial layer 200, thereby forming the conductive layer 420.

[0047] refer to Figure 6 A gate structure 500 is formed on a portion of the surface of the body region 300 and on the surface of the SiC epitaxial layer 200 between the body regions 300. The method of forming the gate structure 500 may include: forming a gate dielectric layer on a portion of the surface of the body region 300 and on the surface of the SiC epitaxial layer 200 between the body regions 300; and forming a gate layer on the surface of the gate dielectric layer.

[0048] refer to Figure 7 A source region 600 is formed in the body region 300 on both sides of the gate structure 500, and the source region 600 extends to a portion below the gate structure 500. The source region 600 can be formed by an ion implantation process, and the type of implanted ions is the same as the doping type of the SiC substrate and the SiC epitaxial layer. Then, a heavy body region 700 is formed in the body region 300 between the source region 600 and the source trench contact hole structure using an ion implantation process, and the type of implanted ions is the same as the doping type of the body region 300.

[0049] refer to Figure 8 A source electrode 800 is formed on the source trench contact hole structure, the heavy body region 700, a portion of the source region 600, and the gate structure 500, and a drain electrode 900 is formed on the second surface 102 of the SiC substrate 100. Prior to forming the source electrode 800, an insulating material 501 is formed on the sidewalls and surface of the gate structure 500 for electrical isolation.

[0050] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0051] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0052] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0053] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0054] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For example, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: The SiC substrate includes a first surface and a second surface opposite to each other, and the first surface of the SiC substrate includes a SiC epitaxial layer. The body region extends from a portion of the surface of the SiC epitaxial layer into the SiC epitaxial layer; A source trench contact hole structure is located on the sidewall of the body region and extends from the surface of the SiC epitaxial layer to the SiC epitaxial layer or the SiC substrate. The source trench contact hole structure includes a conductive layer and an insulating layer located on the sidewall and bottom of the conductive layer. The insulating layer includes at least one of a metal salt layer and a silicon dioxide layer and a SiC crystal layer. The SiC crystal layer is in contact with the body region, the SiC epitaxial layer, and the SiC substrate. The doping type of the SiC crystal layer and the body region is the same as the metal ion type in the metal salt layer. The metal ion type is N-type or P-type. The source region is located within the body region; The heavy body region is located in the body region between the source region and the source trench contact hole structure; A gate structure is located on a portion of the source region, the body region, and the SiC epitaxial layer; The source electrode is located on the source trench contact hole structure, the heavy body region, a portion of the source region, and the gate structure; The drain electrode is located on the second surface of the SiC substrate.

2. The semiconductor structure according to claim 1, characterized in that, The insulating layer includes a metal salt layer, a silicon dioxide layer, and a SiC crystal layer, wherein the metal salt layer is located on the surface of the SiC crystal layer, and the silicon dioxide layer is located on the surface of the metal salt layer.

3. The semiconductor structure according to claim 1, characterized in that, The thickness of the SiC crystal layer and the metal salt layer is 0.1 μm to 0.3 μm, and the thickness of the silicon dioxide layer is 0.1 μm to 0.2 μm.

4. The semiconductor structure according to claim 1, characterized in that, The material of the metal salt layer includes at least one of aluminosilicate, AlTiOx, AlHfOx, and borosilicate.

5. The semiconductor structure according to claim 1, characterized in that, The conductive layer is made of polycrystalline silicon.

6. The semiconductor structure according to claim 1, characterized in that, The SiC substrate, the SiC epitaxial layer, and the source region have a first doping type, and the bulk region and the heavy bulk region have a second doping type, wherein the first doping type and the second doping type are opposite.

7. A method for forming a semiconductor structure, characterized in that, include: A SiC substrate is provided, the SiC substrate including opposing first and second surfaces, and a SiC epitaxial layer is included on the first surface of the SiC substrate; A bulk region is formed extending from a portion of the surface of the SiC epitaxial layer into the SiC epitaxial layer; A source trench contact hole structure is formed on the sidewall of the body region, extending from the surface of the SiC epitaxial layer to the SiC epitaxial layer or the SiC substrate. The source trench contact hole structure includes a conductive layer and an insulating layer located on the sidewall and bottom of the conductive layer. The insulating layer includes at least one of a metal salt layer and a silicon dioxide layer, as well as a SiC crystal layer. The doping type of the SiC crystal layer and the body region is the same as the metal ion type in the metal salt layer, and the metal ion type is N-type or P-type. A source region, a body region, and a gate structure are formed, wherein the source region is located in the body region, the body region is located in the body region between the source region and the source trench contact hole structure, and the gate structure is located on a portion of the source region, the body region, and the SiC epitaxial layer; A source electrode is formed on the source trench contact hole structure, the heavy body region, a portion of the source region, and the gate structure, and a drain electrode is formed on the second surface of the SiC substrate.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The method for forming the source trench contact hole structure includes: Contact holes are formed on the sidewalls of the body region, extending from the surface of the SiC epitaxial layer to the SiC epitaxial layer or the SiC substrate; The insulating layer is formed on the sidewalls and bottom of the contact hole; The conductive layer is formed on the surface of the insulating layer, and the conductive layer fills the contact hole.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The method for forming the SiC crystal layer includes: An α-SiC layer is formed on the sidewalls and bottom of the contact hole; Impurity ions are doped into the α-SiC layer to transform it into a SiC crystal layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The α-SiC layer is formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD), wherein the gases used in the CVD or ALD process include SiH4, C3H8, and TMS, and the temperature is 300°C to 800°C.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The method for converting the α-SiC layer into a SiC crystalline layer includes: A metal salt layer is formed on the surface of the α-SiC layer; The annealing process allows some of the metal ions in the metal salt layer to diffuse into the α-SiC layer, transforming the α-SiC layer into a SiC crystal layer.

12. The method for forming a semiconductor structure according to claim 7, characterized in that, The method for forming the source region, the heavy body region, and the gate structure includes: A gate structure is formed on a portion of the surface of the body region and on the surface of the SiC epitaxial layer within the body region; Source regions are formed in the body regions on both sides of the gate structure, and the source regions also extend below a portion of the gate structure; A heavy body region is formed in the body region between the source region and the source trench contact hole structure.

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