Power amplification device

Abstract

Embodiments provide a power amplification device capable of improving operation reliability. A power amplification device (1) of one embodiment has a first amplifier (A1) to which a plurality of input terminals are applied with a plurality of voltages and which outputs a first output signal (OUTP1); a second amplifier (A2) to which a plurality of input terminals are applied with a plurality of voltages and which outputs a second output signal (OUTM1); a first circuit (LIM1) that outputs a third signal (OUTPLIM1) and a fourth signal (OUTMLIM1), the third signal being a signal in which the magnitude of the voltage value of the first output signal (OUTP1) is limited, and the fourth signal being a signal in which the magnitude of the voltage value of the second output signal (OUTM1) is limited; and a second circuit (CMFB1) that supplies, as a first feedback voltage (VCMFB1), the average of the voltage value of the third signal (OUTPLIM1) and the voltage value of the fourth signal (OUTMLIM1) to the first amplifier (A1) and the second amplifier (A2).

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-154124 (filed on September 22, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to power amplification devices. Background Technology

[0004] As one of the power amplification devices, the BTL (Balanced Transformer Less, Bridge-Tied Load, or Bridged Transformer Less) amplifier is known. Summary of the Invention

[0005] The implementation provides a power amplifier device that can improve operational reliability.

[0006] The power amplifier device of the embodiment includes: a first amplifier that outputs a first output signal by applying multiple voltages to multiple input terminals; a second amplifier that outputs a second output signal by applying multiple voltages to multiple input terminals; a first circuit that outputs a third signal and a fourth signal, wherein the third signal is a signal obtained by limiting the magnitude of the voltage value of the first output signal and the fourth signal is a signal obtained by limiting the magnitude of the voltage value of the second output signal; and a second circuit that sends the average value of the voltage values ​​of the third signal and the fourth signal as a first feedback voltage to the first amplifier and the second amplifier. Attached Figure Description

[0007] Figure 1 This is a circuit diagram showing an example of the power amplifier device of the first embodiment.

[0008] Figure 2 This is a circuit diagram showing an example of the operational amplifier included in the power amplifier device of the first embodiment.

[0009] Figure 3 This is a circuit diagram showing an example of the limiting circuit included in the power amplifier device of the first embodiment.

[0010] Figure 4 This is a circuit diagram showing an example of the intermediate voltage generation circuit included in the power amplifier device of the first embodiment.

[0011] Figure 5 This is a flowchart illustrating the operation of the power amplifier device according to the first embodiment.

[0012] Figure 6 is a diagram illustrating an effect of the power amplifying device of the first embodiment.

[0013] Figure 7 is a circuit diagram showing one example of an operational amplifier included in the power amplifying device of the first embodiment of the first modification.

[0014] Figure 8 is a circuit diagram showing one example of a limiter circuit included in the power amplifying device of the second modification of the first embodiment.

[0015] Figure 9 is a circuit diagram showing one example of the power amplifying device of the second embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, the same reference numerals are assigned to the components having substantially the same functions and configurations, and redundant descriptions are omitted at times. In addition, the description of one embodiment is also applicable to the description of other embodiments unless explicitly stated or otherwise rendered obvious.

[0017] 1. First Embodiment

[0018] The power amplifying device of the first embodiment will be described. In the present embodiment, the power amplifying device is described taking a BTL amplifier as an example.

[0019] 1.1 Configuration

[0020] 1.1.1 Circuit configuration of power amplifying device

[0021] The circuit configuration of the power amplifying device of the present embodiment will be described. Figure 1 is a circuit diagram showing one example of the power amplifying device. Figure 1

[0022] The power amplifying device 1 includes a power supply voltage line 2, a ground voltage line 3, a power supply voltage terminal T1, a ground voltage terminal T2, input terminals Tinpl, Tinml, output terminals Toutpl, Toutml, resistance elements Rs1, Rs2, a first operational amplifier Al, a second operational amplifier A2, resistance elements Rfl, Rf2, a limiter circuit LIM1, and an intermediate voltage generating circuit CMFB1.

[0023] The power supply voltage line 2 is connected to the power supply voltage terminal T1, and a power supply voltage VCC is applied from the outside.

[0024] The ground voltage line 3 is connected to the ground voltage terminal T2, and a ground voltage VSS is applied from the outside.

[0025] ​A signal INP1 is input from the outside to the input terminal Tinp1.

[0026] A signal INM1 is input from the outside to the input terminal Tinm1. The signal INM1 is a signal that inverts the phase of the signal NP1.

[0027] One end of the resistance element Rs1 is connected to the input terminal Tinp1, and the other end is connected to the node ND1.

[0028] One end of the resistance element Rs2 is connected to the input terminal Tinm1, and the other end is connected to the node ND2.

[0029] The first power supply voltage terminal of the first operational amplifier Al is connected to the power supply voltage line 2, and the second power supply voltage terminal is connected to the ground voltage line 3. The first operational amplifier Al has a first non-inverting input terminal (hereinafter, also referred to as "TDFBpl terminal"), a second non-inverting input terminal (hereinafter, also referred to as "TCFBpl terminal"), a first inverting input terminal (hereinafter, also referred to as "TDFBml terminal"), and a second inverting input terminal (hereinafter, also referred to as "TCFBml terminal"). The TDFBpl terminal of the first operational amplifier Al is connected to the node ND1, the TCFBpl terminal is connected to the node ND3, the TDFBml terminal is connected to the node ND2, and the TCFBml terminal is connected to the node ND4. A reference voltage VCMREF1 is applied to the node ND3. The reference voltage VCMREF1 is, for example, a voltage VCC / 2, but is not limited to the voltage VCC / 2. The output terminal of the first operational amplifier Al is connected to the output terminal Toutpl.

[0030] The first operational amplifier Al amplifies the voltage based on the voltage Vinpl of the node ND1 applied to the TDFBpl terminal, the voltage Vinml of the node ND2 applied to the TDFBml terminal, the voltage of the node ND3 applied to the TCFBpl terminal (the reference voltage VCMREF1), and the voltage of the node ND4 applied to the TCFBml terminal (a feedback voltage VCMFB1 described later). Then, the first operational amplifier Al outputs the amplified voltage as a signal OUTPl. The signal OUTPl is output from the output terminal Toutpl. The detailed configuration of the first operational amplifier Al is described later.

[0031] The first power supply voltage terminal of the second operational amplifier A2 is connected to the power supply voltage line 2, and the second power supply voltage terminal is connected to the ground voltage line 3. The second operational amplifier A2 has a first non-inverting input terminal (hereinafter, also referred to as "TDFBp2 terminal"), a second non-inverting input terminal (hereinafter, also referred to as "TCFBp2 terminal"), a first inverting input terminal (hereinafter, also referred to as "TDFBm2 terminal"), and a second inverting input terminal (hereinafter, also referred to as "TCFBm2 terminal"). The first non-inverting input terminal of the second operational amplifier A2 is connected to the node ND2, the second non-inverting input terminal is connected to the node ND3, the first inverting input terminal is connected to the node ND1, and the second inverting input terminal is connected to the node ND4. The output terminal of the second operational amplifier A2 is connected to the output terminal Toutm1.

[0032] The second operational amplifier A2 amplifies the voltage based on the voltage Vinm1 applied to the node ND2 of the TDFBp2 terminal, the voltage Vinp1 applied to the node ND1 of the TDFBm2 terminal, the voltage (reference voltage VCMREF1) applied to the node ND3 of the TCFBp2 terminal, and the voltage (feedback voltage VCMFB1 to be described later) applied to the node ND4 of the TCFBm2 terminal. Then, the second operational amplifier A2 outputs the amplified voltage as a signal OUTM1. The signal OUTM1 is output from the output terminal Toutm1. The detailed configuration of the second operational amplifier A2 will be described later.

[0033] One end of the resistive element Rf1 is connected to the output terminal Toutp1, and the other end is connected to the node ND2. The signal OUTP1 is fed back to the TDFBm1 terminal of the first operational amplifier A1 via the resistive element Rf1.

[0034] One end of the resistive element Rf2 is connected to the output terminal Toutm1, and the other end is connected to the node ND1. The signal OUTM1 is fed back to the TDFBm2 terminal of the second operational amplifier A2 via the resistive element Rf2.

[0035] Hereinafter, the feedback action via the resistive elements Rf1 and Rf2 will be referred to as "first feedback action".

[0036] The voltage VLIM1 is applied to the limiter circuit LIM1. The limiter circuit LIM1 is connected to the output terminals Toutpl, Toutml. The limiter circuit LIM1 receives the signal OUTpl from the first operational amplifier Al and the signal OUTml from the second operational amplifier A2. In addition, the limiter circuit LIM1 is connected to the intermediate voltage generating circuit CMFBl. The limiter circuit LIM1 transmits the signal OUTPLIM1 based on the signal OUTpl and the signal OUTMLIM1 based on the signal OUTml to the intermediate voltage generating circuit CMFBl. In addition, the limiter circuit LIM1 limits the magnitude of the voltage value of the signals OUTpl, OUTml (the maximum voltage value or the minimum voltage value of the signals OUTpl, OUTml) based on the voltage VLIM1. The detailed configuration of the limiter circuit LIM1 will be described later.

[0037] For example, in the case of limiting the maximum voltage value of the signals OUTpl, OUTml, the limiter circuit LIM1 determines the maximum voltage value Vmax of the signals OUTpl, OUTml based on the voltage VLIM1. In the case where the signals OUTpl, OUTml are smaller than the maximum voltage value Vmax, the limiter circuit LIM1 transmits the signals OUTpl, OUTml as the signals OUTPLIM1, OUTMLIM1 to the intermediate voltage generating circuit CMFBl. On the other hand, in the case where the signals OUTpl, OUTml are equal to or larger than the maximum voltage value Vmax, the limiter circuit LIM1 transmits the maximum voltage value Vmax as the signals OUTPLIM1, OUTMLIM1 to the intermediate voltage generating circuit CMFBl.

[0038] In the case of limiting the minimum voltage value of the signals OUTpl, OUTml, the limiter circuit LIM1 determines the minimum voltage value Vmin of the signals OUTpl, OUTml based on the voltage VLIM1. In the case where the signals OUTpl, OUTml are larger than the minimum voltage value Vmin, the limiter circuit LIM1 transmits the signals OUTpl, OUTml as the signals OUTPLIM1, OUTMLIM1 to the intermediate voltage generating circuit CMFBl. On the other hand, in the case where the signals OUTpl, OUTml are equal to or smaller than the minimum voltage value Vmin, the limiter circuit LIM1 transmits the minimum voltage value Vmin as the signals OUTpl, OUTml to the intermediate voltage generating circuit CMFBl.

[0039] An intermediate voltage generation circuit CMFB1 is connected to node ND4. CMFB1 generates the average value of signals OUTPLIM1 and OUTMLIM1 received from the limiting circuit LIM1. Then, CMFB1 sends this average value as a feedback voltage VCMFB1 to node ND4. In other words, voltage VCMFB1 is fed back from CMFB1 to terminals TCFBm1 of the first operational amplifier A1 and TCFBm2 of the second operational amplifier A2. The detailed configuration of the intermediate voltage generation circuit CMFB1 will be described below.

[0040] Hereinafter, the feedback action via the limiting circuit LIM1 and the intermediate voltage generation circuit CMFB1 will be referred to as "the second feedback action".

[0041] 1.1.2 Construction of the First Operational Amplifier

[0042] use Figure 2 The circuit configuration of the first operational amplifier A1 will be explained. Figure 2 This is a circuit diagram representing an example of the first operational amplifier A1. Furthermore, the second operational amplifier A2 has the same configuration as the first operational amplifier A1. In the following description, without specifying the source and drain of the transistor, either the source or drain of the transistor is referred to as "one end of the transistor," and the other end of the source and drain of the transistor is referred to as "the other end of the transistor."

[0043] The first operational amplifier A1 includes a first transconductance circuit Gm_DFB, a second transconductance circuit Gm_CFB, a resistor element R1, a driver stage circuit DS, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) P1 (hereinafter also referred to as "PMOS transistor"), and an n-channel MOSFET (hereinafter also referred to as "NMOS transistor") N1.

[0044] The non-inverting input terminal of the first transconductance circuit Gm_DFB is connected to the TDFBp1 ​​terminal of the first operational amplifier A1, and the inverting input terminal is connected to the TDFBm1 terminal of the first operational amplifier A1. The output terminal of the first transconductance circuit Gm_DFB is connected to node ND5. The output of the first transconductance circuit Gm_DFB is the current Idfb based on the voltage difference between the voltage Vinp1 applied from node ND1 to the non-inverting input terminal and the voltage Vinm1 applied from node ND2 to the inverting input terminal. Furthermore, the transconductance gm of the first transconductance circuit Gm_DFB is set to an arbitrary value. When there is no voltage difference between Vinp1 and Vinm1, the current Idfb is 0.

[0045] The non-inverting input terminal of the second transconductance circuit Gm_CFB is connected to the TCFBpl terminal of the first operational amplifier Al, and the inverting input terminal is connected to the TCFBml terminal of the first operational amplifier Al. The output terminal of the second transconductance circuit Gm_CFB is connected to the node ND5. The second transconductance circuit Gm_CFB outputs a current Icfb based on a voltage difference between the reference voltage VCMREFl applied to the non-inverting input terminal from the node ND3 and the feedback voltage VCMFBl applied to the inverting input terminal from the node ND4. Further, the transconductance gm of the second transconductance circuit Gm_CFB is set to an arbitrary value. In the absence of the voltage difference between the reference voltage VCMREFl and the feedback voltage VCMFBl, the current Icfb is 0.

[0046] One end of the resistive element Rl is connected to the node ND5, and the other end is grounded. The current Ir, which is a resultant of the current Idfb and the current Icfb, flows to the resistive element Rl. The current Ir is converted into the voltage Vr.

[0047] The voltage VCC is applied to the non-illustrated first power supply voltage terminal of the driver stage circuit DS, and the voltage VSS is applied to the non-illustrated second power supply voltage terminal. The input terminal of the driver stage circuit DS is connected to the node ND5, and the output terminals are connected to the nodes ND6 and ND7. The voltage Vr is applied to the driver stage circuit DS. The driver stage circuit DS amplifies the voltage Vr and outputs the amplified voltage to drive the PMOS transistor PI and the NMOS transistor Nl, which are constituted as a push-pull.

[0048] The voltage VCC is applied to one end of the PMOS transistor PI, the other end is connected to the node ND8, and the gate is connected to the node ND6. The PMOS transistor PI is set to the on state when the voltage difference between the voltage of the node ND6 and the voltage VCC exceeds the threshold voltage of the PMOS transistor PI, and outputs a current corresponding to the voltage difference between the voltage of the node ND6 and the voltage VCC to the node ND8.

[0049] One end of the NMOS transistor Nl is connected to the node ND8, the voltage VSS is applied to the other end, and the gate is connected to the node ND7. The NMOS transistor Nl is set to the on state when the voltage difference between the voltage of the node ND7 and the ground voltage VSS exceeds the threshold voltage of the NMOS transistor Nl, and outputs a current corresponding to the voltage difference between the voltage of the node ND7 and the voltage VSS to the node ND8.

[0050] If a current is output from the PMOS transistor PI or the NMOS transistor Nl, the voltage of the node ND8 is controlled in accordance with the value of the current output from the PMOS transistor PI or the NMOS transistor Nl. That is, the determination signal OUTPl is decided.

[0051] For example, in the case where the voltage Vr is positive, the current of the PMOS transistor P1 increases. At this time, the 1st operational amplifier Al outputs, as the signal OUTP1, a voltage amplified to the positive side with respect to the voltage Vr.

[0052] On the other hand, in the case where the voltage Vr is negative, the current of the NMOS transistor N1 increases. At this time, the 1st operational amplifier Al outputs, as the signal OUTP1, a voltage amplified to the negative side with respect to the voltage Vr.

[0053] 1.1.3 Configuration of the limiting circuit

[0054] The limiting circuit LIM1 is configured as follows. Figure 3 The configuration of the limiting circuit LIM1 will be described. Figure 3 FIG. 6 is a circuit diagram of a limiting circuit for a low side amplifier, which is an example of the limiting circuit LIM1.

[0055] The limiting circuit LIM1 includes NMOS transistors N2 and N3.

[0056] One end of the NMOS transistor N2 is connected to the output terminal Toutpl, the other end is connected to the intermediate voltage generating circuit CMFB1, and the gate is applied with the voltage VLIM1. The voltage VLIM1 is, for example, a voltage higher than the reference voltage VCMREF1, which makes the NMOS transistor N2 in an on state. The maximum voltage value Vmaxp of the signal OUTP1 is determined based on the voltage VLIM1. In the case where the signal OUTP1 is smaller than the maximum voltage value Vmaxp, the voltage value of the signal OUTPLIM1 becomes the voltage value of the signal OUTP1. In other words, the limiting circuit LIM1 transmits the signal OUTP1 to the intermediate voltage generating circuit CMFB1 as the signal OUTPLIM1. On the other hand, in the case where the signal OUTP1 is equal to or larger than the maximum voltage value Vmaxp, the voltage value of the signal OUTPLIM1 becomes the maximum voltage value Vmaxp. In other words, the limiting circuit LIM1 transmits the maximum voltage value Vmaxp to the intermediate voltage generating circuit CMFB1 as the signal OUTPLIM1.

[0057] One end of the NMOS transistor N3 is connected to the output terminal Toutml, the other end is connected to the intermediate voltage generation circuit CMFB1, and the gate is applied with the voltage VLIM1. The voltage VLIM1 is, for example, a voltage higher than the reference voltage VCMREF1, which turns the NMOS transistor N3 on. The maximum voltage value Vmaxm of the signal OUTM1 is determined based on the voltage VLIM1. In a case where the signal OUTM1 is smaller than the maximum voltage value Vmaxm, the voltage value of the signal OUTMLIM1 becomes the voltage value of the signal OUTM1. In other words, the limiting circuit LIM1 transmits the signal OUTM1 to the intermediate voltage generation circuit CMFB1 as the signal OUTMLIM1. On the other hand, in a case where the signal OUTM1 is the maximum voltage value Vmaxm or more, the voltage value of the signal OUTMLIM1 becomes the maximum voltage value Vmaxm. In other words, the limiting circuit LIM1 transmits the maximum voltage value Vmaxm to the intermediate voltage generation circuit CMFB1 as the signal OUTMLIM1.

[0058] 1.1.4 Configuration of the intermediate voltage generation circuit

[0059] The feedback operation of the power amplifying device 1 of the present embodiment will be described. Figure 4 The circuit configuration of the intermediate voltage generation circuit CMFB1 will be described. Figure 4 is a circuit diagram showing one example of the intermediate voltage generation circuit CMFB1.

[0060] The intermediate voltage generation circuit CMFB1 includes the resistive elements R2, R3. In addition, the resistive elements R2, R3 have the same resistance value.

[0061] One end of the resistive element R2 is connected to the limiting circuit LIM1, and the other end is connected to the node ND4.

[0062] One end of the resistive element R3 is connected to the node ND4, and the other end is connected to the limiting circuit LIM1.

[0063] Since the resistive elements R2, R3 have the same resistance value, the intermediate voltage generation circuit CMFB1 transmits the average of the voltage value of the signal OUTPLIM1 and the voltage value of the signal OUTMLIM1 to the node ND4 as the feedback voltage VCMFB1.

[0064] 1.2 Feedback operation

[0065] The feedback operation of the power amplifying device 1 of the present embodiment will be described. Figure 5 The feedback operation of the power amplifying device 1 of the present embodiment will be described. Figure 5 is a flowchart showing the feedback operation of the power amplifying device 1. Hereinafter, the first feedback operation and the second feedback operation of the second feedback operation will be described.

[0066] The limiter circuit LIM1 generates a signal OUTPLIM1 based on the voltage VLIM1 and the signal OUTP1, and a signal OUTMLIM1 based on the voltage VLIM1 and the signal OUTM1 (S10).

[0067] Then, the intermediate voltage generation circuit CMFB1 generates an average value of the voltage value of the signal OUTPLIM1 and the voltage value of the signal OUTMLIM1 (S11).

[0068] Then, the intermediate voltage generation circuit CMFB1 transmits the average value generated at S11 as the feedback voltage VCMFB1 to the TCFBm1 terminal of the 1st operational amplifier Al and the TCFBm2 terminal of the 2nd operational amplifier A2 (S12).

[0069] 1.3 Effects

[0070] According to the configuration of the present embodiment, it is possible to improve the operation reliability of the power amplifying device. Hereinafter, the effects of the power amplifying device 1 of the present embodiment will be described with reference to the accompanying drawings. Figure 6 The effects of the present embodiment will be described. Figure 6 is a view for explaining the effects of the power amplifying device 1 of the present embodiment.

[0071] Figure 6 The waveforms of the signal OUTP1, the signal OUTM1, and the signal of the difference (OUTP1-OUTM1) between the signal OUTP1 and the signal OUTM1 are shown. Further, in the example of Figure 6 In the example of

[0072] In the case where the amplitudes of the signals OUTP1, OUTM1 are small (region of [1]), clipping of the signals OUTP1, OUTM1 does not occur (no clipping). At the time of no clipping, the amplitudes of the signals OUTP1, OUTM1 symmetrically vibrate up and down, and the feedback voltage VCMFB1 is maintained as a constant value equal to the reference voltage VCMREF1.

[0073] On the other hand, in the case where the amplitudes of the signals OUTP1, OUTM1 are large (region of [2]), the signals OUTP1, OUTM1 are clipped on the voltage VSS side. At this time, by the 1st feedback operation, the amplitude of the signal OUTP1 or OUTM1 which is not clipped increases, so the signals OUTP1, OUTM1 are no longer symmetrically up and down.

[0074] In the present embodiment, as the second feedback operation, the following operation is performed. The limiter circuit LIM1 limits the maximum voltage value Vmax of the signals OUTP1, OUTM1 based on the voltage VLIM1. Therefore, the voltage values of the signals OUTPLIM1, OUTMLIM1 become the maximum voltage value Vmax or less determined based on the voltage VLIM1. The limiter circuit LIM1 transmits the signals OUTPLIM1, OUTMLIM1 to the intermediate voltage generation circuit CMFB1. The intermediate voltage generation circuit CMFB1 generates an average value of the voltage value of the signal OUTPLIM1 and the voltage value of the signal OUTMLIM1, and transmits the average value as the feedback voltage VCMFB1 to the first operational amplifier Al and the second operational amplifier A2. Since the voltage values of the signals OUTPLIM1, OUTMLIM1 are limited to the maximum voltage value Vmax or less, in the case where the amplitudes of the signals OUTP1, OUTM1 are large, the feedback voltage VCMFB1 also maintains a constant value equal to the reference voltage VCMREF1. That is, according to the configuration of the present embodiment, the unevenness of the midpoint potential of the signals OUTP1, OUTM1 is reduced.

[0075] In addition, the gain of the first operational amplifier Al is a constant value Rfl / Rsl, and the gain of the second operational amplifier A2 is a constant value Rf2 / Rs2, both at the time of no clipping and at the time of clipping. Therefore, it is possible to suppress the deterioration of the distortion of the signals OUTP1, OUTM1, and OUTP1-OUTM1.

[0076] Therefore, according to the present embodiment, it is possible to improve the operation reliability of the power amplifying device.

[0077] 1.4 First Modified Example

[0078] The power amplifying device 1 of the first modified example of the first embodiment will be described. In the power amplifying device 1 of the present modified example, the configurations of the first operational amplifier Al and the second operational amplifier A2 are different from those of the first embodiment. Hereinafter, the description will be made focusing on the points different from the first embodiment.

[0079] 1.4.1 Configuration of First Operational Amplifier

[0080] Adopting Figure 7 The circuit configuration of the first operational amplifier Al will be described. Figure 7 is a circuit diagram showing one example of the first operational amplifier Al. In addition, the second operational amplifier A2 has the same configuration as the first operational amplifier Al.

[0081] In the first operational amplifier Al, the first transconductance circuit Gm_DFB, the second transconductance circuit Gm_CFB, and the resistive element Rl are not used. The first operational amplifier Al further includes the first voltage-controlled voltage source A_DFB and the second voltage-controlled voltage source A_CFB.

[0082] The first power supply terminal of the first voltage-controlled voltage source A_DFB is connected to the node ND5, and the second power supply terminal is connected to the node ND9. The non-inverting input terminal of the first voltage-controlled voltage source A_DFB is connected to the TDFBpl terminal of the first operational amplifier Al, and the inverting input terminal is connected to the TDFBml terminal of the first operational amplifier Al. The first voltage-controlled voltage source A_DFB outputs the voltage difference dVdfb of the voltage Vinpl applied to the non-inverting input terminal from the node NDl and the voltage Vinml applied to the inverting input terminal from the node ND2. Further, the amplification of the first voltage-controlled voltage source A_DFB is set to an arbitrary value.

[0083] The first power supply terminal of the second voltage-controlled voltage source A_CFB is connected to the node ND9, and the second power supply terminal is grounded. The second voltage-controlled voltage source A_CFB outputs the voltage difference dVcfb of the reference voltage VCMREFl applied to the non-inverting input terminal from the node ND3 and the feedback voltage VCMFBl applied to the inverting input terminal from the node ND4. Further, the amplification of the second voltage-controlled voltage source A_CFB is set to an arbitrary value.

[0084] The other configurations of the first operational amplifier Al are the same as those of the first embodiment. Figure 2 The same is true.

[0085] The voltage Vd of the synthesized voltage difference dVdfb and the voltage difference dVcfb is applied to the driver stage circuit DS. The driver stage circuit DS amplifies the voltage Vd and outputs the amplified voltage to drive the PMOS transistor PI and the NMOS transistor Nl in a push-pull configuration.

[0086] 1.4.2 Effects

[0087] According to the configuration of the present modification example, the same effects as those of the first embodiment are exerted.

[0088] 1.5 Second Modification Example

[0089] The power amplifying device 1 of the second modification example of the first embodiment will be described. In the power amplifying device 1 of the present modification example, the configuration of the limiting circuit LIMl is different from that of the first embodiment. Hereinafter, the description will be made focusing on the points different from the first embodiment.

[0090] 1.5.1 Configuration of Limiting Circuit

[0091] The first voltage-controlled voltage source A_DFB is usedFigure 8 The circuit configuration of the limiter circuit LIM1 will be described. Figure 8 FIG. 6 is a circuit diagram of a limiter circuit for a high side amplifier, shown as one example of the limiter circuit LIM1.

[0092] The limiter circuit LIM1 includes PMOS transistors P2, P3.

[0093] One end of the PMOS transistor P2 is connected to the output terminal Toutpl, the other end is connected to the intermediate voltage generation circuit CMFB1, and the gate is applied with the voltage VLIM1. The voltage VLIM1 is, for example, a voltage lower than the reference voltage VCMREF1, which makes the PMOS transistor P2 to be in the on state. The minimum voltage value Vminp of the signal OUTPl is decided based on the voltage VLIM1. In the case where the signal OUTPl is larger than the minimum voltage value Vminp, the voltage value of the signal OUTPLIM1 becomes the voltage value of the signal OUTPl. In other words, the limiter circuit LIM1 transmits the signal OUTPl as the signal OUTPLIM1 to the intermediate voltage generation circuit CMFB1. On the other hand, in the case where the signal OUTPl is equal to or lower than the minimum voltage value Vminp, the voltage value of the signal OUTPLIM1 becomes the minimum voltage value Vminp. In other words, the limiter circuit LIM1 transmits the minimum voltage value Vminp as the signal OUTPLIM1 to the intermediate voltage generation circuit CMFB1.

[0094] One end of the PMOS transistor P3 is connected to the output terminal Toutml, the other end is connected to the intermediate voltage generation circuit CMFB1, and the gate is applied with the voltage VLIM1. The voltage VLIM1 is, for example, a voltage lower than the reference voltage VCMREF1, which makes the PMOS transistor P3 to be in the on state. The minimum voltage value Vminm of the signal OUTM1 is decided based on the voltage VLIM1. In the case where the signal OUTM1 is larger than the minimum voltage value Vminm, the voltage value of the signal OUTMLIM1 becomes the voltage value of the signal OUTM1. In other words, the limiter circuit LIM1 transmits the signal OUTM1 as the signal OUTMLIM1 to the intermediate voltage generation circuit CMFB1. On the other hand, in the case where the signal OUTM1 is equal to or lower than the minimum voltage value Vminm, the voltage value of the signal OUTMLIM1 becomes the minimum voltage value Vminm. In other words, the limiter circuit LIM1 transmits the minimum voltage value Vminm as the signal OUTMLIM1 to the intermediate voltage generation circuit CMFB1.

[0095] 1.5.2 Feedback operation

[0096] The feedback operation of the power amplifying device 1 of the present modification example will be described. The flowchart showing the second feedback operation of the power amplifying device 1 of the present modification example is the same as that of the first embodiment. Figure 5 The same applies.

[0097] 1.5.3 Effects

[0098] In the present modification example, as the second feedback operation, the limiter circuit LIM1 limits the minimum voltage value Vmin of the signals OUTP1, OUTM1 based on the voltage VLIM1. Therefore, the voltage values of the signals OUTPLIM1, OUTMLIM1 become the minimum voltage value Vmin or more decided based on the voltage VLIM1. For example, in the case where the reference voltage VCMREF1 is set to a voltage higher than the voltage VCC / 2 and lower than the voltage VCC, if the amplitudes of the signals OUTP1, OUTM1 become large, the signals OUTP1, OUTM1 generate clipping on the voltage VCC side. However, since the voltage values of the signals OUTPLIM1, OUTMLIM1 are limited to the minimum voltage value Vmin or more, according to the configuration of the present modification example, as in the first embodiment, the unevenness of the midpoint potential of the signals OUTP1, OUTM1 is small.

[0099] In addition, according to the configuration of the present modification example, as in the first embodiment, it is possible to suppress the deterioration of the distortion of the signals OUTP1, OUTM1, and OUTP1-OUTM1.

[0100] 2. Second Embodiment

[0101] The power amplifying device 1 of the second embodiment will be described. The power amplifying device 1 of the present embodiment differs from the first embodiment in that it includes a BTL amplifier (hereinafter, also referred to as "high-side amplifier HS") including a third operational amplifier A3 and a fourth operational amplifier A4. The second embodiment is a 2ch (2-channel) power amplifying device, unlike the first embodiment which is a 1ch (1-channel) power amplifying device. In the second embodiment, by sharing the power consumed in the high-side amplifier HS in the low-side amplifier LS, high-efficiency operation is possible, compared to a power amplifying device having two power amplifying devices of the first embodiment. Hereinafter, the description will be focused on the points different from the first embodiment.

[0102] 2.1 Circuit configuration of power amplifying device

[0103] The power amplifying device 1 of the present embodiment adopts Figure 9 The circuit configuration of the power amplifying device 1 of the present embodiment will be described. Figure 9 is a circuit diagram showing one example of the power amplifying device 1.

[0104] The power amplifying device 1 further includes a buffer circuit BUF, a first voltage wiring 4, and a first voltage terminal T3.

[0105] The buffer circuit BUF generates a voltage VCC / 2 as a voltage divided from a voltage between the power supply voltage wiring 2 and the ground voltage wiring 3.

[0106] The first voltage wiring 4 is connected to the first voltage terminal T3, and the voltage VCC / 2 is supplied from the buffer circuit BUF.

[0107] A BTL amplifier (hereinafter, also referred to as "low-side amplifier LS") including a first operational amplifier Al and a second operational amplifier A2 further includes switches SWl, SW2.

[0108] The switch SWl is connected to a first power supply voltage terminal of the first operational amplifier Al, and switches connection of the first power supply voltage terminal of the first operational amplifier Al to the power supply voltage wiring 2 and connection of the first power supply voltage terminal of the first operational amplifier Al to the first voltage wiring 4.

[0109] The switch SW2 is connected to a first power supply voltage terminal of the second operational amplifier A2, and switches connection of the first power supply voltage terminal of the second operational amplifier A2 to the power supply voltage wiring 2 and connection of the first power supply voltage terminal of the second operational amplifier A2 to the first voltage wiring 4.

[0110] For example, in a case where the amplitudes of the signals OUTPl, OUTMl are small (for example, voltage values (voltage values with respect to the voltage VCC) of the signals OUTPl, OUTMl are smaller than the voltage VCC / 2), the switches SWl, SW2 are connected to the first voltage wiring 4. Thereby, the voltage VCC / 2 and the voltage VSS are applied to the first operational amplifier Al and the second operational amplifier A2.

[0111] On the other hand, in a case where the amplitudes of the signals OUTPl, OUTMl are large (for example, a voltage value (a voltage value with respect to the voltage VCC) of the signal OUTPl or OUTMl is the voltage VCC / 2 or more), the switches SWl, SW2 are connected to the power supply voltage wiring 2. Thereby, the voltage VCC and the voltage VSS are applied to the first operational amplifier Al and the second operational amplifier A2.

[0112] In the low-side amplifier LS, the reference voltage VCMREFl is, for example, the voltage VCC / 4.

[0113] The high-side amplifier HS includes input terminals Tinp2, Tinm2, output terminals Toutp2, Toutm2, resistance elements Rs3, Rs4, a third operational amplifier A3, a fourth operational amplifier A4, resistance elements Rf3, Rf4, switches SW3, SW4, a limiting circuit LIM2, and an intermediate voltage generating circuit CMFB2.

[0114] The input terminals Tinp2, Tinm2 correspond to the input terminals Tinp1, Tinm1 of the low-side amplifier LS, respectively.

[0115] The output terminals Toutp2, Toutm2 correspond to the output terminals Toutp1, Toutm1 of the low-side amplifier LS, respectively.

[0116] The resistance elements Rs3, Rs4 correspond to the resistance elements Rs1, Rs2 of the low-side amplifier LS, respectively.

[0117] The TDFBp3 terminal, the TCFBp3 terminal, the TDFBm3 terminal, and the TCFBm3 terminal of the 3rd operational amplifier A3 correspond to the TDFBp1 terminal, the TCFBp1 terminal, the TDFBm1 terminal, and the TCFBm1 terminal of the 1st operational amplifier Al of the low-side amplifier LS, respectively. The 3rd operational amplifier A3 has the same configuration as the 1st operational amplifier Al.

[0118] The TDFBp4 terminal, the TCFBp4 terminal, the TDFBm4 terminal, and the TCFBm4 terminal of the 4th operational amplifier A4 correspond to the TDFBp2 terminal, the TCFBp2 terminal, the TDFBm2 terminal, and the TCFBm2 terminal of the 2nd operational amplifier A2 of the low-side amplifier LS, respectively. The 4th operational amplifier A4 has the same configuration as the 2nd operational amplifier A2.

[0119] The resistance elements Rf3, Rf4 correspond to the resistance elements Rfl, Rf2 of the low-side amplifier LS, respectively.

[0120] The switch SW3 is connected to the 2nd power supply voltage terminal of the 3rd operational amplifier A3, and switches the connection of the 2nd power supply voltage terminal of the 3rd operational amplifier A3 to the ground voltage wiring 3 and the connection of the 2nd power supply voltage terminal of the 3rd operational amplifier A3 to the 1st voltage wiring 4. The switch SW3 corresponds to the switch SWl of the low-side amplifier LS.

[0121] The switch SW4 is connected to the 2nd power supply voltage terminal of the 4th operational amplifier A4, and switches the connection of the 2nd power supply voltage terminal of the 4th operational amplifier A4 to the ground voltage wiring 3 and the connection of the 2nd power supply voltage terminal of the 4th operational amplifier A4 to the 1st voltage wiring 4. The switch SW4 corresponds to the switch SW2 of the low-side amplifier LS.

[0122] For example, in a case where the amplitude of the signals OUTP2, OUTM2 is small (for example, the voltage value of the signals OUTP2, OUTM2 (voltage value with respect to the voltage VSS) is VCC / 2 or more), the switches SW3, SW4 are connected to the first voltage line 4. Thereby, the voltage VCC and the voltage VCC / 2 are applied to the third operational amplifier A3 and the fourth operational amplifier A4.

[0123] On the other hand, in a case where the amplitude of the signals OUTP2, OUTM2 is large (for example, the voltage value of the signals OUTP2 or OUTM2 (voltage value with respect to the voltage VSS) is less than VCC / 2), the switches SW3, SW4 are connected to the ground voltage line 3. Thereby, the voltage VCC and the voltage VSS are applied to the third operational amplifier A3 and the fourth operational amplifier A4.

[0124] The limiting amplifier LIM2 corresponds to the limiting amplifier LIM1 of the low-side amplifier LS. The limiting amplifier LIM2 has the same configuration as the limiting amplifier LIM1 of the second modification of the first embodiment.

[0125] The intermediate voltage generation circuit CMFB2 corresponds to the intermediate voltage generation circuit CMFB1 of the low-side amplifier LS. The intermediate voltage generation circuit CMFB2 has the same configuration as the intermediate voltage generation circuit CMFB1.

[0126] The signals INP2, INM2 correspond to the signals INP1, INM1 of the low-side amplifier LS, respectively.

[0127] The nodes ND11, ND12 correspond to the nodes ND1, ND2 of the low-side amplifier LS, respectively.

[0128] The voltages Vinp2, Vinm2 correspond to the voltages Vinp1, Vinm1 of the low-side amplifier LS, respectively.

[0129] The reference voltage VCMREF2 and the feedback voltage VCMFB2 correspond to the reference voltage VCMREF1 and the feedback voltage VCMFB1 of the low-side amplifier LS, respectively. The reference voltage VCMREF2 is, for example, 3VCC / 4.

[0130] The nodes ND13, ND14 correspond to the nodes ND3, ND4 of the low-side amplifier LS, respectively.

[0131] The signals OUTP2, OUTM2 correspond to the signals OUTP1, OUTM1 of the low-side amplifier LS, respectively.

[0132] The voltage VLIM2 and the signals OUTPLIM2 and OUTMLIM2 correspond to the voltage VLIM1 and the signals OUTPLIM1 and OUTMLIM1 of the low-side amplifier LS, respectively.

[0133] 2.2 Feedback action

[0134] The feedback action of the power amplifying device 1 of the present embodiment will be described. The flowchart showing the second feedback action in the low-side amplifier LS and the high-side amplifier HS of the power amplifying device 1 of the present embodiment is the same as that of the first embodiment. Figure 5

[0135] 2.3 Effects

[0136] According to the configuration of the present embodiment, the same effects as those of the first embodiment are exerted.

[0137] In addition, as in the first embodiment, the unevenness of the midpoint potential of the signals OUTP1 and OUTM1 and the unevenness of the midpoint potential of the signals OUTP2 and OUTM2 are small. Therefore, the high-efficiency range of the power amplifying device 1 is maximized. Moreover, since the unevenness of the midpoint potential is small, in the power amplifying device having two or more power amplifying devices of the second embodiment, even if the output terminals of the low-side amplifiers LS and the output terminals of the high-side amplifiers HS are misconnected to each other, the potential difference between the misconnected output terminals is small, so the short-circuit current value flowing therethrough is small. Therefore, a circuit for protecting the short circuit with other channels does not need to be provided.

[0138] Of course, the present embodiment can also be applied to the first modification of the first embodiment.

[0139] 3. Modifications and the like

[0140] As described above, the power amplifying device (1) of the present embodiment has: a first amplifier (Al) to which a plurality of voltages are applied to a plurality of input terminals and which outputs a first output signal (OUTP1); a second amplifier (A2) to which a plurality of voltages are applied to a plurality of input terminals and which outputs a second output signal (OUTM1); a first circuit (LIM1) that outputs a third signal (OUTPLIM1) obtained by limiting the magnitude of the voltage value of the first output signal (OUTP1) and a fourth signal (OUTMLIM1) obtained by limiting the magnitude of the voltage value of the second output signal (OUTM1); and a second circuit (CMFB1) that transmits, as a first feedback voltage (VCMFB1), the average of the voltage value of the third signal (OUTPLIM1) and the voltage value of the fourth signal (OUTMLIM1) to the first amplifier (Al) and the second amplifier (A2).​

[0141] Furthermore, the embodiments are not limited to the above-described modes, and various modifications can be made.

[0142] The processing order of the flowcharts described in the above embodiments can be replaced as far as possible.

[0143] Several embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments and their modifications are included in the scope, spirit of the application, and are also included in the scope of the application as recited in the claims and equivalents thereof.

Claims

1. A power amplifying apparatus, comprising: a first amplifier to which a plurality of voltages are applied to a plurality of input terminals and which outputs a first output signal; a second amplifier to which a plurality of voltages are applied to a plurality of input terminals and which outputs a second output signal; a first circuit to output, as a third signal, a first maximum voltage value of the first output signal based on a third voltage or the first output signal smaller than the first maximum voltage value, based on a magnitude of a voltage value of the first output signal, and to output, as a fourth signal, a second maximum voltage value of the second output signal based on the third voltage or the second output signal smaller than the second maximum voltage value, based on a magnitude of a voltage value of the second output signal; and a second circuit to transmit, as a first feedback voltage, an average of a voltage value of the third signal and a voltage value of the fourth signal to the first amplifier and the second amplifier. In the plurality of input terminals of the first amplifier, a first non-inverting input terminal is applied with a first voltage corresponding to a first input signal, a first inverting input terminal is applied with a second voltage corresponding to a second input signal, a second non-inverting input terminal is applied with a first reference voltage, a second inverting input terminal is applied with the first feedback voltage. In the plurality of input terminals of the second amplifier, the first voltage is applied to a third inverting input terminal, the second voltage is applied to a third non-inverting input terminal, the first reference voltage is applied to a fourth non-inverting input terminal, the first feedback voltage is applied to a fourth inverting input terminal, the third signal is a signal in which a magnitude of a voltage value of the first output signal is limited based on the third voltage higher than the first reference voltage, and the fourth signal is a signal in which a magnitude of a voltage value of the second output signal is limited based on the third voltage.

2. The power amplifying apparatus according to claim 1, wherein the first circuit limits maximum voltage values of the first output signal and the second output signal.

3. A power amplifying apparatus, comprising: a first amplifier to which a plurality of voltages are applied to a plurality of input terminals and which outputs a first output signal; a second amplifier to which a plurality of voltages are applied to a plurality of input terminals and which outputs a second output signal; a first circuit to output, as a third signal, a first minimum voltage value of the first output signal based on a third voltage or the first output signal greater than the first minimum voltage value, based on a magnitude of a voltage value of the first output signal, and to output, as a fourth signal, a second minimum voltage value of the second output signal based on the third voltage or the second output signal greater than the second minimum voltage value, based on a magnitude of a voltage value of the second output signal; and a second circuit to transmit, as a first feedback voltage, an average of a voltage value of the third signal and a voltage value of the fourth signal to the first amplifier and the second amplifier. In the plurality of input terminals of the first amplifier, a first non-inverting input terminal is applied with a first voltage corresponding to a first input signal, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a second voltage corresponding to a second input signal is applied to a second non-inverting input terminal, a first reference voltage is applied to a second inverting input terminal, the first feedback voltage is applied to a second inverting input terminal; in the plurality of input terminals of the second amplifier, the first voltage is applied to a third inverting input terminal, the second voltage is applied to a third non-inverting input terminal, the first reference voltage is applied to a fourth non-inverting input terminal, the first feedback voltage is applied to a fourth inverting input terminal, the third signal is a signal based on the third voltage being lower than the first reference voltage limits the magnitude of the voltage value of the first output signal, and the fourth signal is a signal based on the third voltage limits the magnitude of the voltage value of the second output signal.

4. The power amplification device according to any one of claims 1 to 3, wherein the first amplifier generates the first output signal based on a first current and a second current, the first current being based on the first voltage and the second voltage, and the second current being based on the first reference voltage and the first feedback voltage.

5. The power amplification device according to any one of claims 1 to 3, wherein the first amplifier generates the first output signal based on a voltage difference between the first voltage and the second voltage, and a voltage difference between the first reference voltage and the first feedback voltage.

6. The power amplification device according to any one of claims 1 to 3, wherein the first circuit includes a first transistor and a second transistor; the first output signal is input to one end of the first transistor, the other end of which is connected to the second circuit, and the third voltage is applied to a gate electrode; the second output signal is input to one end of the second transistor, the other end of which is connected to the second circuit, and the third voltage is applied to a gate electrode.

7. The power amplification device according to any one of claims 1 to 3, wherein the second circuit includes a first resistance element and a second resistance element; one end of the first resistance element is connected to the first circuit, and the other end thereof is connected to the first amplifier and the second amplifier; one end of the second resistance element is connected to the first amplifier and the second amplifier, and the other end thereof is connected to the first circuit.

8. The power amplification device according to claim 7, wherein a resistance value of the first resistance element is equal to a resistance value of the second resistance element.

9. The power amplification device according to any one of claims 1 to 3, wherein the power amplification device has: a third amplifier to which a plurality of voltages are applied to a plurality of input terminals, and which outputs a third output signal; a fourth amplifier to which a plurality of voltages are applied to a plurality of input terminals, and which outputs a fourth output signal; a third circuit which outputs a fifth signal and a sixth signal, the fifth signal being a signal obtained by limiting the magnitude of the voltage value of the third output signal, and the sixth signal being a signal obtained by limiting the magnitude of the voltage value of the fourth output signal; and a fourth circuit which outputs a seventh signal and an eighth signal, the seventh signal being a signal obtained by limiting the magnitude of the voltage value of the fifth signal, and the eighth signal being a signal obtained by limiting the magnitude of the voltage value of the sixth signal. A fourth circuit that sends an average of a voltage value of the fifth signal and a voltage value of the sixth signal as a second feedback voltage to the third amplifier and the fourth amplifier.

10. The power amplifying device according to claim 9, wherein of the third amplifier, a fourth voltage corresponding to a third input signal is applied to a fifth non-inverting input terminal, a fifth voltage corresponding to a fourth input signal is applied to a fifth inverting input terminal, a second reference voltage is applied to a sixth non-inverting input terminal, the second feedback voltage is applied to a sixth inverting input terminal; of the fourth amplifier, the fourth voltage is applied to a seventh inverting input terminal, the fifth voltage is applied to a seventh non-inverting input terminal, the second reference voltage is applied to an eighth non-inverting input terminal, the second feedback voltage is applied to an eighth inverting input terminal.

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