Analog-to-digital converter, low-dropout regulator and comparison control circuit thereof

Abstract

The present application provides a comparison control circuit for an analog-to-digital converter and a low-dropout regulator, which includes a comparator, a Schmitt trigger, a capacitor bank, and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage level or a first low voltage level. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage level range, wherein the voltage level range is between the first low voltage level and the first high voltage level. The capacitor bank is configured to adjust the second input signal when controlled. The logic circuit is configured to control the capacitor bank according to the trigger signal, so as to correspondingly adjust the second input signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a comparison control circuit, an analog-to-digital converter and a low dropout regulator having the comparison control circuit. BACKGROUND

[0002] A comparator is a common semiconductor element that compares the voltage received by two input terminals and outputs a comparison signal. Comparators are widely used in various types of circuits, such as analog-to-digital converters (ADCs), analog low dropout regulators (LDOs), and the like. However, due to the influence of input signal noise, power supply noise, or a wide frequency bandwidth, the comparator often outputs an unclean comparison signal, which can cause the circuit to make a false judgment during operation, thereby causing the circuit to output an incorrect signal. SUMMARY

[0003] To solve the above problems, the present application provides a comparison control circuit. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor group, and a logic circuit. The comparator has a first input terminal, a second input terminal, and a first output terminal, and is configured to output a comparison signal from the first output terminal according to a first input signal received by the first input terminal and a second input signal received by the second input terminal, wherein the comparison signal is a first high voltage level or a first low voltage level. The Schmitt trigger has a third input terminal and a second output terminal, and is configured to output a trigger signal from the second output terminal according to the comparison signal received by the third input terminal and a voltage level range, wherein the trigger signal is a second high voltage level or a second low voltage level, and the voltage level range is between the first low voltage level and the first high voltage level. The capacitor group is configured to adjust the second input signal when controlled. The logic circuit is configured to control the capacitor group according to the trigger signal to correspondingly adjust the second input signal.

[0004] In some embodiments, the comparator is a single-ended input comparator.

[0005] In some embodiments, the capacitor group includes a plurality of capacitors C1 to C N Each capacitor has a first end and a second end.

[0006] In some embodiments, the first end of each capacitor is electrically connected to the second input terminal, and the second end of each capacitor is selectively electrically connected to a reference voltage source or a ground when controlled.

[0007] According to some embodiments, a low dropout voltage regulator comprises an error amplifier, a pass transistor, a voltage divider circuit, and the comparison control circuit. The error amplifier has a positive input terminal, a negative input terminal, and a third output terminal for outputting a control voltage from the third output terminal according to a feedback voltage received by the positive input terminal and a stable reference voltage level received by the negative input terminal. The pass transistor has a gate terminal, a drain terminal, and a source terminal for outputting an output voltage from the drain terminal according to the control voltage received by the gate terminal. The voltage divider circuit is configured to divide the output voltage and the feedback voltage such that the feedback voltage has the same value as the stable reference voltage level, and thus the output voltage has the same value as the stable reference voltage level. The comparison control circuit is configured to stabilize the output voltage, wherein the second input terminal is electrically connected to the drain terminal.

[0008] In some embodiments, the voltage divider circuit comprises a first voltage divider resistor and a second voltage divider resistor, wherein the first voltage divider resistor has a resistance value much smaller than the resistance value of the second voltage divider resistor.

[0009] According to some embodiments, an analog-to-digital converter comprises the comparison control circuit, wherein the first input signal is an analog input signal, the second input signal is a comparison voltage level, and the logic circuit is further configured to store and output a digital output signal.

[0010] In some embodiments, the capacitance value of the capacitor C i is twice the capacitance value of the capacitor C i+1 , the capacitance value of the capacitor C N-1 is equal to the capacitance value of the capacitor C N , and i = 1 ~ N-2.

[0011] In some embodiments, the capacitor group of the analog-to-digital converter is a capacitive digital-to-analog converter.

[0012] In some embodiments, the logic circuit of the analog-to-digital converter is a successive approximation register.

[0013] In summary, in some embodiments, the comparison control circuit can be applied to various types of circuits, so that the circuit can avoid noise problems caused by input signals or power supplies during operation, thereby ensuring that the circuit outputs correct and clean signals. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a circuit function block diagram of a comparison control circuit according to an embodiment of the present application;

[0015] Figure 2A FIG. 2 is a voltage waveform diagram of an external input signal received by a comparator in the comparison control circuit according to an embodiment of the present application;

[0016] Figure 2B This is a voltage waveform diagram of the comparator clock in a comparator control circuit according to an embodiment of the present invention;

[0017] Figure 2C This is a voltage waveform diagram of the comparison signal output by the comparator in a comparison control circuit according to an embodiment of the present invention.

[0018] Figure 3 This is a circuit diagram of an analog-to-digital converter according to an embodiment of the present invention;

[0019] Figure 4 This is a flowchart illustrating the operation of an analog-to-digital converter according to an embodiment of the present invention;

[0020] Figure 5 This is a circuit diagram of an analog low-dropout regulator according to an embodiment of the present invention;

[0021] Figure 6 This is a flowchart illustrating the operation of a simulated low-dropout regulator according to an embodiment of the present invention. Detailed Implementation

[0022] The following description, in conjunction with the accompanying drawings, will illustrate some embodiments of the present invention. For clarity, many implementation details will be described in the following description, but this is not intended to limit the invention.

[0023] Please refer to Figure 1 , Figure 1 This is a circuit functional block diagram of a comparison control circuit 100 according to an embodiment of the present invention. The comparison control circuit 100 includes a comparator 110, a Schmitt trigger 120, a logic circuit 130, and a capacitor bank 140, wherein the comparator 110 has a first input terminal 111, a second input terminal 112, and a first output terminal 113, and the Schmitt trigger 120 has a third input terminal 121 and a second output terminal 122. Figure 1 As shown, the third input terminal 121 of the Schmitt trigger 120 is electrically connected to the first output terminal 113 of the comparator 110, the logic circuit 130 is electrically connected to the second output terminal 122 of the Schmitt trigger 120, and the capacitor bank 140 is electrically connected to the second input terminal 112 of the comparator 110 and the logic circuit 130.

[0024] In some embodiments, comparator 110 is a single-ended input comparator, wherein comparator 110 receives a first input signal V at its first input terminal 111. in1 And receive the second input signal V from the second input terminal 112. in2 Comparator 110 is used to compare the first input signal V. in1and a second input signal V in2 and outputs a comparison signal from a first output terminal 113, wherein the comparison signal is either a first high voltage level or a first low voltage level. Please refer to Figure 2A 、 Figure 2B and Figure 2C , Figure 2A is a voltage waveform diagram of an external input signal received by the comparator 110 in the comparison control circuit 100 according to an embodiment of the present application. Figure 2B is a voltage waveform diagram of a clock of the comparator 110 in the comparison control circuit 100 according to an embodiment of the present application, wherein the clock of the comparator 110 is used to trigger the comparator 110 to output the comparison signal. Figure 2C is a voltage waveform diagram of the comparison signal outputted by the comparator 110 in the comparison control circuit 100 according to an embodiment of the present application, wherein the solid line waveform represents the waveform of the comparison signal, and the dashed-dotted line waveform represents the waveform caused by signal noise. In Figure 2A 、 Figure 2B and Figure 2C , the horizontal axis represents time in nanoseconds (ns), and the vertical axis represents voltage in volts (V). In this embodiment, the first high voltage level is 1 volt, the first low voltage level is 0 volt, the first input signal V in1 is the external input signal, the second input signal V in2 is a comparison voltage level V com , wherein the value of the comparison voltage level V com is 0.5 volt. When the value of the first input signal V in1 received by the first input terminal 111 of the comparator 110 (as shown by the dashed line L1 in Figure 2A ) is greater than or equal to the second input signal V in2 , the clock of the comparator 110 triggers the comparator 110 at the falling edge (as shown by the dashed line L1 in Figure 2B ), so that the comparator 110 outputs the first high voltage level from the first output terminal 113 (as shown by the dashed-dotted line box R1 in Figure 2C ). When the value of the first input signal V in1 received by the first input terminal 111 of the comparator 110 (as shown by the dashed line L2 in Figure 2A ) is less than the second input signal V in2 , the clock of the comparator 110 triggers the comparator 110 at the rising edge (as shown by the dashed line L2 in Figure 2B ), so that the comparator 110 outputs the first low voltage level from the first output terminal 113 (as shown by the dashed-dotted line box R2 in Figure 2C ).

[0025] The Schmitt trigger 120 is configured to output a trigger signal from the second output 122 based on the comparison signal received at the third input 121 and a voltage level range, wherein the trigger signal is a second high voltage level or a second low voltage level. In some embodiments, the user can define the voltage level range of the Schmitt trigger 120. In this embodiment, the voltage level range of the Schmitt trigger 120 is between the first low voltage level and the first high voltage level. When the comparison signal value received by the Schmitt trigger 120 is greater than or equal to the upper limit of the voltage level range, the Schmitt trigger 120 outputs the second high voltage level from the second output 122. When the comparison signal value received by the Schmitt trigger 120 is within the voltage level range (i.e., the comparison signal value is greater than or equal to the lower limit of the voltage level range and the comparison signal value is less than the upper limit of the voltage level range), the Schmitt trigger 120 does not perform any operation. When the comparison signal value received by the Schmitt trigger 120 is less than the lower limit of the voltage level range, the Schmitt trigger 120 outputs the second low voltage level from the second output terminal 122. In some embodiments, the value of the second high voltage level is 1 volt, and the value of the second low voltage level is 0 volts. Since the Schmitt trigger 120 has better analog signal noise immunity, placing the Schmitt trigger 120 in the comparison control circuit 100 can effectively resist the comparison signal noise output by the comparator 110 or the noise generated by the power supply, thereby avoiding problems during the operation of the comparison control circuit 100.

[0026] Capacitor bank 140 is used to adjust the second input signal V when controlled by logic circuit 130. in2 In some embodiments, the capacitor bank includes N capacitors C1-C2. N and N switches S1-S N Each capacitor has a first terminal and a second terminal. The first terminal of each capacitor is electrically connected to the second input terminal 112 of the comparator 110, and the second terminal of each capacitor, when controlled, can be selectively electrically connected to a reference voltage source V through a corresponding switch. ref Or grounded. When the second terminal of a capacitor is electrically connected to the reference voltage source V. ref When the capacitor is charged, it will be charged. When the second terminal of the capacitor is electrically connected to ground, the capacitor will be discharged.

[0027] Logic circuit 130 controls capacitor bank 140 according to the trigger signal to adjust the comparison voltage level accordingly. In other words, logic circuit 130 controls the corresponding switch in capacitor bank 140 based on the value of the trigger signal. Then, the corresponding capacitor in capacitor bank 140 is electrically connected to the reference voltage source V. refAlternatively, it can be grounded for charging or discharging. Finally, capacitor bank 140 calculates an adjusted comparison voltage level based on the capacitance value of each capacitor and outputs the adjusted comparison voltage level to the second input terminal 112 of comparator 110.

[0028] In some embodiments, the architecture of the comparison control circuit 100 can be applied to the analog-to-digital converter 200. Please refer to... Figure 3 , Figure 3 This is a circuit diagram of an analog-to-digital converter 200 according to an embodiment of the present invention. The analog-to-digital converter 200 includes a comparator 210, a Schmitt trigger 220, logic circuitry 230, and a capacitor bank 240. Figure 3 As shown, the third input terminal 221 of the Schmitt trigger 220 is electrically connected to the first output terminal 213 of the comparator 210, the logic circuit 230 is electrically connected to the second output terminal 222 of the Schmitt trigger 220, and the capacitor bank 240 is electrically connected to the second input terminal 212 of the comparator 210 and the logic circuit 230. In this embodiment, the signal received by the first input terminal 211 of the comparator 210 is the analog input signal V. ain The signal received at the second input terminal 212 of comparator 210 is the comparison voltage level V. com The signal received at the third input terminal 221 of the Schmitt trigger 220 is a comparison signal.

[0029] Analog-to-digital converter 200 is used to convert analog input signal V ain Converted into a digital output signal V with N bits dout In some embodiments, the analog-to-digital converter 200 receives the digital output signal V. dout The conversion begins with the most significant bit (MSB) and proceeds sequentially with the remaining bits until the digital output signal V is reached. dout Once the least significant bit (LSB) is converted, a complete analog-to-digital (ADC) signal conversion is finished. In some embodiments, the ADC 200 outputs a digital output signal V through logic circuit 230. dout The logic circuit 230 is a successive approximation register (SAR).

[0030] The capacitor bank 240 of the analog-to-digital converter 200 includes multiple capacitor switch groups. Each capacitor switch group includes a capacitor and a switch connected in series, and each capacitor switch group is connected in parallel. The parallel connection point of each capacitor switch group is electrically connected to the second input terminal 212 of the comparator 210. When controlled, each switch of the capacitor bank 240 selectively connects the corresponding capacitor electrically to the reference voltage source V. ref Or grounded, where the reference voltage source Vref It is a fixed voltage value. In some embodiments, the capacitor C i The capacitance value is capacitor C. i+1 Twice the capacitance value, capacitance C N-1 The capacitance value is equal to the capacitance C. N The capacitance value is given by i = 1 to N-2. In some embodiments, the capacitor bank 240 is a capacitive digital-to-analog converter, wherein the capacitive digital-to-analog converter converts a digital signal into an analog signal by storing charge in the capacitor. For example, in this embodiment, the capacitor bank 240 includes four capacitors C1-C4 and four switches S1-S4. If the digital signal received by the capacitor bank 240 is (1100), then capacitors C1 and C2 are electrically connected to the reference voltage source V. ref Capacitors C3 and C4 will be grounded. Assume the reference voltage source V... ref The value of C4 is 1 volt (V), and the capacitance of C4 is C. Since capacitors connected in parallel are equal to the sum of their capacitances, and the impedance of a capacitor is inversely proportional to its capacitance, the voltage level V output by capacitor bank 240 to comparator 210 is... com The value is 0.75 volts (V), and the formula is as follows:

[0031]

[0032] Please refer to Figure 4 , Figure 4 This is a flowchart illustrating the operation of an analog-to-digital converter 200 according to an embodiment of the present invention. Figure 4 As shown, in step S10, when the analog input signal V ain When the analog-to-digital converter 200 is input, the analog-to-digital converter 200 will convert the analog input signal V... ain Sample-and-Hold (S&H) and convert the analog input signal V ain The input is fed to comparator 210. The purpose of sampling is to ensure that the analog-to-digital converter 200 maintains the analog input signal V during operation. ain Consistency, to avoid digital output signal V dout An error is generated. In step S20, comparator 210 compares the analog input signal V at the first input terminal 211. ain and the comparison voltage level V at the second input terminal 212 com A comparison signal is output from the first output terminal 213 to the Schmitt trigger 220 of the analog-to-digital converter 200. In step S30, the Schmitt trigger 220 outputs a trigger signal from the second output terminal 222 to the logic circuit 230 of the analog-to-digital converter 200 based on the comparison signal and a voltage level range.

[0033] In step S40, the logic circuit 230 stores the trigger signal as the corresponding bit of the analog input signal V ain in sequence (from the largest significant bit to the smallest significant bit). Then, the logic circuit 230 controls the corresponding switch of the capacitor bank 240 of the analog-to-digital converter 200 according to the trigger signal, so that the corresponding capacitor of the capacitor bank 240 is electrically connected to the reference voltage source V ref or the ground. For example, if the current conversion sequence is the second bit, the logic circuit 230 stores the trigger signal as the second significant bit of the analog input signal V ain . If the value of the trigger signal is 1, the logic circuit 230 controls the switch S2 of the capacitor bank 240, so that the capacitor C2 of the capacitor bank 240 is electrically connected to the reference voltage source V ref for charging.

[0034] In step S50, the capacitor bank 240 calculates an adjusted comparison voltage level V com according to the capacitance value of each capacitor, and outputs the adjusted comparison voltage level V com to the comparator 210. In step S60, the analog-to-digital converter 200 repeats the steps S20-S50 to perform the next round of bit conversion, until all the bits of the analog input signal V ain are converted, i.e., step S70. Since the capacitance values of the capacitors of the capacitor bank 240 are different, the value of the comparison voltage level V com output by the capacitor bank 240 is different in each round of bit conversion. As each round of bit conversion is performed, the value of the comparison voltage level V com received by the comparator 210 gradually approaches the value of the analog input signal V ain . When the value of the comparison voltage level V com received by the comparator 210 is equal to the value of the analog input signal V ain , it means that the analog-to-digital converter 200 has completely converted the analog input signal V ain into all the bits of the digital output signal V dout . Therefore, in step S70, the analog-to-digital converter 200 outputs the digital output signal V dout through the logic circuit 230, and ends this time of analog signal conversion.

[0035] In another embodiment, the comparison control circuit 100 can also be applied in an analog low dropout regulator 300. Please refer to Figure 5 , Figure 5Fig. 1 shows a circuit schematic diagram of an analog low-dropout regulator 100 according to an embodiment of the present application. The analog low-dropout regulator 100 includes an error amplifier 110, a pass transistor 120, a voltage divider circuit 130, and a comparison control circuit 140, wherein the error amplifier 110 has a positive input terminal 112, a negative input terminal 111, and a third output terminal 113, the pass transistor 120 has a gate terminal 121, a drain terminal 122, and a source terminal 123, and the comparison control circuit 140 includes a comparator 141, a Schmitt trigger 142, a logic circuit 143, and a capacitor group 144. As shown in Fig. 1, the gate terminal 121 of the pass transistor 120 is electrically connected to the third output terminal 113 of the error amplifier 110, the voltage divider circuit 130 is electrically connected to the drain terminal 122 of the pass transistor 120 and the positive input terminal 112 of the error amplifier 110, and the second input terminal 141b of the comparator 141 is electrically connected to the drain terminal 122 of the pass transistor 120. In this embodiment, the signal received by the first input terminal 141a of the comparator 141 is a comparison voltage level V com , and the signal received by the second input terminal 141b of the comparator 141 is an output voltage V out .

[0036] The error amplifier 110 is configured to output a control voltage from the third output terminal 113 according to a feedback voltage V fb received by the positive input terminal 112 and a stable reference voltage level V sref received by the negative input terminal 111, wherein the control voltage is used to control the voltage of the gate terminal 121 of the pass transistor 120. When the feedback voltage V fb is greater than the stable reference voltage level V sref , the error amplifier 110 adjusts the voltage of the gate terminal 121 of the pass transistor 120 such that a current value flowing through the pass transistor 120 decreases to lower the output voltage V out . When the feedback voltage V fb is less than the stable reference voltage level V sref , the error amplifier 110 adjusts the voltage of the gate terminal 121 of the pass transistor 120 such that the current value increases to raise the output voltage V out .

[0037] The pass transistor 120 is configured to output an output voltage V out from the drain terminal 122 according to the control voltage received by the gate terminal 121. In some embodiments, the pass transistor 120 receives an input voltage V in from the source terminal 123. When the gate terminal 121 of the pass transistor 120 receives the control voltage from the error amplifier 110, the pass transistor 120 outputs the output voltage V out from the drain terminal 122, wherein the input voltage V in is used to charge the capacitor group 144.in the value of the output voltage V out In some embodiments, the pass transistor 320 is a P-type metal-oxide-semiconductor field-effect transistor (PMOS).

[0038] The voltage dividing circuit 330 is configured to divide the output voltage V out and the feedback voltage V fb such that the value of the feedback voltage V fb is the same as the stable reference voltage level V sref , and in turn, the value of the output voltage V out is the same as the stable reference voltage level V sref , where the stable reference voltage level V sref is a fixed voltage value that is not affected by temperature or signal noise. In some embodiments, the voltage dividing circuit 330 includes a first voltage dividing resistor R fb1 and a second voltage dividing resistor R fb2 , where the resistance value of the first voltage dividing resistor R fb1 is much smaller than the resistance value of the second voltage dividing resistor R fb2 . Assuming the error amplifier 310 is an ideal amplifier, we can calculate that the value of the output voltage V out will be equal to the stable reference voltage level V sref , as shown in the following equation:

[0039]

[0040]

[0041] In some embodiments, the comparison control circuit 340 is configured to stabilize the output voltage V out . When the pass transistor 320 outputs the output voltage V out from the drain terminal 322, the output voltage V out may be adjusted to be more stable by the comparison control circuit 340. In some embodiments, the output voltage V out is input into the comparison control circuit 340 via the second input terminal 341b of the comparator 341, and the output voltage V out is compared with the comparison voltage level V com received by the first input terminal 341a of the comparator 341. When the value of the output voltage V out is greater than the comparison voltage level V com , the comparison control circuit 340 controls the capacitor bank 344 through the logic circuit 343 to reduce the value of the output voltage V out to the comparison voltage level V com . When the value of the output voltage V out is less than the comparison voltage level V comAt that time, the comparator control circuit 340 controls the capacitor bank 344 through the logic circuit 343 to adjust the output voltage V. out The value is raised to the comparison voltage level V com In some embodiments, the comparison voltage level V received at the first input terminal 341a of comparator 341 com Equal to stable reference voltage level V sref .

[0042] In some embodiments, the user can adjust the output voltage V according to the output voltage V. out The value of the capacitor group 344 is user-defined, specifying the number of capacitors and the capacitance value of each capacitor. A larger number of capacitors in 344 indicates more variations in the output voltage; a smaller number of capacitors indicates fewer variations. A larger capacitance value indicates a wider range of output voltage values; a smaller capacitance value indicates a narrower range. For example, if the output voltage V... out The value is relatively small (e.g., output voltage V). out (The value is 1 volt), and users can set a smaller number of capacitors with smaller capacitance values ​​in capacitor bank 344 to save costs.

[0043] Please refer to Figure 6 , Figure 6 This is a flowchart illustrating the operation of a simulated low-dropout regulator 300 according to an embodiment of the present invention. Figure 6 As shown, in step S80, the analog low-dropout regulator 300 will convert the input voltage V in The input is given to the source terminal 323 of the turn-on transistor 320. In step S90, the analog low-dropout regulator 300 will stabilize the reference voltage level V. sref and feedback voltage V fb The inputs are respectively fed to the negative input terminal 311 and the positive input terminal 312 of the error amplifier 310. At this time, the error amplifier 310 will adjust according to the stable reference voltage level V. sref and feedback voltage V fb A control voltage is output to the gate terminal 321 of the turn-on transistor 320. In step S100, the gate terminal 321 of the turn-on transistor 320 receives the control voltage, causing the turn-on transistor 320 to enter the turn-on state and output an output voltage V from the drain terminal 322. out If the output voltage V at this time out The value is not equal to the stable reference voltage level V. sref The analog low-dropout regulator 300 adjusts the output voltage V through the voltage divider circuit 330 and the error amplifier 310. out This, in turn, causes the output voltage Vout the value of the output voltage V sref .

[0044] In step S110, when the value of the output voltage V out is equal to the stable reference voltage level V sref , the comparator 341 of the comparison control circuit 340 receives the output voltage V out through the second input terminal 341b, and outputs a comparison signal to the third input terminal 342a of the Schmitt trigger 342 of the comparison control circuit 340 according to the output voltage V out and the comparison voltage level V com received by the first input terminal 341a. In step S120, the Schmitt trigger 342 outputs a trigger signal to the logic circuit 343 of the comparison control circuit 340 according to the comparison signal and a voltage level range from the second output terminal 342b. In step S130, the logic circuit 343 controls the corresponding switch of the capacitor group 344 of the comparison control circuit 340 according to the trigger signal, so that the corresponding capacitor of the capacitor group 344 is charged or discharged. Finally, in step S140, the capacitor group 344 calculates an adjusted output voltage V out according to the capacitance value of each capacitor and outputs it.

[0045] In summary, according to some embodiments of the comparison control circuit 100, even if the input signal or the power signal in each type of circuit is mixed with noise, these circuits can resist the noise through the comparison control circuit 100, thereby avoiding the failure of operation or the output of errors. For example, the application of the architecture of the comparison control circuit 100 in the analog-to-digital converter 200 can make the analog-to-digital converter 200 output a more accurate digital output signal V dout . The analog low-dropout voltage regulator 300 can adjust the output voltage V out through the comparison control circuit 340, so that the output voltage V out becomes more stable.

[0046] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and any person with ordinary knowledge in the art can modify and change the technical features of the present application without departing from the spirit and scope of the present application, and these modifications and changes still belong to the scope of the patent protection sought by the present application.

[0047] Legend of reference signs:

[0048] 100: comparison control circuit

[0049] 110: comparator

[0050] 111: first input

[0051] 112: second input

[0052] 113: first output

[0053] 120: Schmitt trigger

[0054] 121: third input

[0055] 122: second output

[0056] 130: logic circuit

[0057] 140: capacitor bank

[0058] 200: analog-to-digital converter

[0059] 210: comparator

[0060] 211: first input

[0061] 212: second input

[0062] 213: first output

[0063] 220: Schmitt trigger

[0064] 221: third input

[0065] 222: second output

[0066] 230: logic circuit

[0067] 240: capacitor bank

[0068] 300: analog low dropout regulator

[0069] 310: error amplifier (EA)

[0070] 311: negative input

[0071] 312: positive input

[0072] 313: third output

[0073] 320: pass transistor (TP)

[0074] 321: gate terminal

[0075] 322: drain terminal

[0076] 323: source terminal

[0077] 330: voltage divider circuit

[0078] 340: comparison control circuit

[0079] 341: comparator

[0080] 341a: first input

[0081] 341b: second input

[0082] 341c: first output

[0083] 342: Schmitt trigger

[0084] 342a: third input

[0085] 342b: second output

[0086] 343: logic circuit

[0087] 344: capacitor bank

[0088] L1: dotted line

[0089] L2: dotted line

[0090] R1: one-dot chain box

[0091] R2: one-dot chain box

[0092] R fb1 : first voltage dividing resistor

[0093] R fb2 : second voltage dividing resistor

[0094] C1-C4: capacitor

[0095] S1-S4: switch

[0096] S10-S140: step

[0097] V ain : analog input signal

[0098] V com : comparison voltage level

[0099] V dout : digital output signal

[0100] V fb : feedback voltage

[0101] V in : input voltage

[0102] V in1 : first input signal

[0103] V in2 : second input signal

[0104] Vout : output voltage

[0105] V ref : reference voltage source

[0106] V sref : stable reference voltage level

Claims

1. A comparison control circuit, comprising: a comparator having a first input terminal, a second input terminal and a first output terminal, the comparator receiving a first input signal from the first input terminal and a second input signal from the second input terminal, the comparator comparing the first input signal and the second input signal and outputting a comparison signal from the first output terminal, wherein the comparison signal is a first high voltage level or a first low voltage level; a Schmitt trigger having a third input terminal and a second output terminal, the Schmitt trigger outputting a trigger signal from the second output terminal according to the comparison signal received by the third input terminal and a voltage level range, wherein the trigger signal is a second high voltage level or a second low voltage level, the voltage level range being between the first low voltage level and the first high voltage level; a capacitor bank for adjusting the second input signal when controlled; and a logic circuit for controlling the capacitor bank according to the trigger signal to correspondingly adjust the second input signal. The comparator is a single-ended input comparator.

2. The comparison control circuit of claim 1, wherein, A first terminal of each of the capacitors is electrically connected to the second input terminal, and a second terminal of each of the capacitors is selectively electrically connected to a reference voltage source or a ground when controlled.

3. The comparison control circuit of claim 1, wherein, The capacitor bank comprises a plurality of capacitors C1 to C N wherein each of the capacitors has a first end and a second end.

4. The comparison control circuit of claim 3, wherein, 5. An analog low-dropout regulator, comprising: an error amplifier having a positive input terminal, a negative input terminal and a third output terminal, the error amplifier outputting a control voltage from the third output terminal according to a feedback voltage received by the positive input terminal and a stable reference voltage level received by the negative input terminal; a pass transistor having a gate terminal, a drain terminal and a source terminal, the pass transistor outputting an output voltage from the drain terminal according to the control voltage received by the gate terminal; a voltage divider circuit for dividing the output voltage and outputting the feedback voltage; and a comparison control circuit according to any one of claims 1 to 4 for stabilizing the output voltage, wherein the second input terminal is electrically connected to the drain terminal. The voltage divider circuit comprises a first voltage dividing resistor and a second voltage dividing resistor, wherein a resistance value of the first voltage dividing resistor is much smaller than a resistance value of the second voltage dividing resistor.

7. An analog-to-digital converter, comprising:

6. The analog low dropout regulator of claim 5, wherein, a comparator having a first input terminal, a second input terminal and a first output terminal, the comparator comparing the first input terminal and the second input terminal and outputting a comparison signal from the first output terminal, wherein the comparison signal is a first high voltage level or a first low voltage level; a Schmitt trigger having a third input terminal and a second output terminal, the Schmitt trigger outputting a trigger signal from the second output terminal according to the third input terminal and a voltage level range, wherein the trigger signal is a second high voltage level or a second low voltage level, the voltage level range being between the first low voltage level and the first high voltage level; ​ ​ a capacitor bank comprising a plurality of capacitor switch banks, each of the capacitor switch banks comprising a capacitor in series with a switch, the plurality of capacitor switch banks being connected in parallel with each other, the plurality of switches being controlled to selectively electrically connect the plurality of capacitors to either a reference voltage source or a ground, a point of connection of the plurality of capacitors being electrically connected to the second input terminal; and and a logic circuit for controlling the plurality of switches of the capacitor bank in accordance with the trigger signal.

8. The analog-to-digital converter of claim 7, wherein, Capacitor C i The capacitance value is capacitor C. i+1 Twice the capacitance value, capacitance C N-1 The capacitance value is equal to the capacitance C. N The capacitance value, where i = 1 ~ N-2.

9. The analog-to-digital converter of claim 7, wherein, The capacitor bank is a capacitor digital-to-analog converter.

10. The analog-to-digital converter of claim 7, wherein, The logic circuit is a successive approximation register.

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