Data stream clock signal generation circuit, method, electronic device and storage medium

Abstract

The present invention provides a circuit, method, electronic device, and storage medium for generating a data stream clock signal. The circuit includes: a frequency tracking module for generating a frequency adjustment signal based on a blanking interval end marker signal and a horizontal synchronization signal; a phase-locked loop module connected to the frequency tracking module for receiving a link clock signal and a frequency adjustment signal, generating a data stream clock signal based on the link clock signal, and adjusting the frequency of the data stream clock signal based on the frequency adjustment signal to dynamically equalize the generated data stream clock signal with the initial data stream clock signal of the source device transmitting the video signal. In this manner, the data stream clock signal generation circuit of the present invention can dynamically equalize the generated data stream clock signal with the initial data stream clock signal of the source device transmitting the video signal, thereby avoiding data loss caused by buffer overflow or underflow due to unequal periods.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a circuit, method, electronic device and storage medium for generating a data stream clock signal. Background Art

[0002] During video signal transmission, the transmitter and receiver must synchronize their clocks. Clock synchronization at the receiver isn't about obtaining the exact same absolute time as the transmitter, but rather about aligning the clock information with the received data so that the data can be correctly recovered from the received waveform.

[0003] However, in actual use, due to the sensitivity limitations of electronic components in the circuit, it is impossible to achieve clock equality in the circuit, resulting in the clocks of the transmitter and receiver being out of sync, which may cause video data loss during transmission. Summary of the Invention

[0004] The present invention provides a data stream clock signal generation circuit, method, electronic equipment and storage medium, which are used to solve the problem of video data loss caused by clock signal asynchrony in the prior art.

[0005] The present invention provides a data stream clock signal generation circuit, comprising: a phase-locked loop module and a frequency tracking module; the frequency tracking module is used to generate a frequency adjustment signal according to a blanking area end mark signal and a horizontal synchronization signal; wherein the blanking area end mark signal is a pulse signal generated in a video signal emitted by a source device according to the position of the blanking area end mark on the time axis; the horizontal synchronization signal is a horizontal synchronization signal in a timing format signal group for controlling screen display generated according to the data stream clock signal; the phase-locked loop module is connected to the frequency tracking module, is used to receive a link clock signal and a frequency adjustment signal, generate a data stream clock signal according to the link clock signal, and adjust the frequency of the data stream clock signal according to the frequency adjustment signal, so that the generated data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal.

[0006] According to a data stream clock signal generation circuit provided by the present invention, a frequency tracking module is used to receive a tracking signal; within the effective area of ​​the tracking signal, the frequency tracking module compares the first position where a pulse of a blanking area end mark signal appears on the time axis with the second position where a pulse of a horizontal synchronization signal appears on the time axis, and generates a frequency adjustment signal based on the comparison result.

[0007] According to a data stream clock signal generation circuit provided by the present invention, the frequency tracking module includes a phase frequency detector and a modulator; the modulator is respectively connected to the phase frequency detector and the phase locked loop module; the phase frequency detector is used to compare the first position where the pulse of the blanking area end mark signal appears on the time axis with the second position where the pulse of the horizontal synchronization signal appears on the time axis within the effective area of ​​the tracking signal to obtain a comparison result; the modulator is used to generate a frequency adjustment signal according to the comparison result.

[0008] According to a data stream clock signal generation circuit provided by the present invention, a phase-locked loop module includes a voltage-controlled oscillator, an in-loop phase detector, a first calculation module, and a second calculation module; the second calculation module is connected to the frequency tracking module; the first calculation module is connected to the in-loop phase detector, the first calculation module is used to receive a link clock signal and a first parameter, and input the calculation result of dividing the link clock signal by the first parameter into the in-loop phase detector; the output end of the in-loop phase detector is connected to the voltage-controlled oscillator, the voltage-controlled oscillator outputs a data stream clock signal, and inputs the data stream clock signal into the second calculation module, and the second calculation module inputs the calculation result of dividing the data stream clock signal by the second parameter into the in-loop phase detector.

[0009] The present invention also provides a method for generating a data stream clock signal, comprising: generating a frequency adjustment signal based on a blanking area end mark signal and a horizontal synchronization signal; wherein the blanking area end mark signal is a pulse signal generated in a video signal emitted by a source device according to the position of the blanking area end mark on the time axis; the horizontal synchronization signal is a horizontal synchronization signal in a timing format signal group for controlling screen display generated based on the data stream clock signal; receiving a link clock signal and a frequency adjustment signal, generating a data stream clock signal based on the link clock signal, and adjusting the frequency of the data stream clock signal based on the frequency adjustment signal so that the generated data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal.

[0010] According to a method for generating a data stream clock signal provided by the present invention, a frequency adjustment signal is generated based on a blanking area end mark signal and a horizontal synchronization signal, including: receiving a tracking signal; within a valid area of ​​the tracking signal, comparing a first position where a pulse of the blanking area end mark signal appears on the time axis with a second position where a pulse of the horizontal synchronization signal appears on the time axis, and generating a frequency adjustment signal based on the comparison result.

[0011] According to a method for generating a data stream clock signal provided by the present invention, a frequency adjustment signal is generated based on a comparison result, including: if the second position on the time axis is later than the first position, a first instruction is generated, and the first instruction causes the frequency of the data stream clock signal to increase; if the second position on the time axis is earlier than the first position, a second instruction is generated, and the second instruction causes the frequency of the data stream clock signal to decrease.

[0012] According to a method for generating a data stream clock signal provided by the present invention, a frequency adjustment signal is generated based on a comparison result, and the method also includes: determining a deviation time based on a first position and a second position; generating a frequency acceleration instruction based on the deviation time; and determining the acceleration of the frequency change of the data stream clock signal based on the acceleration instruction.

[0013] The present invention also provides an electronic device comprising any of the above-mentioned data stream clock signal generating circuits.

[0014] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-mentioned circuit methods for generating a data stream clock signal.

[0015] The data stream clock signal generation circuit, method, electronic device and storage medium provided by the present invention are as follows: the frequency tracking module generates a frequency adjustment signal according to the blanking area end mark signal and the horizontal synchronization signal; the phase-locked loop module is connected to the frequency tracking module, receives the link clock signal and the frequency adjustment signal, generates a data stream clock signal according to the link clock signal, and adjusts the frequency of the data stream clock signal according to the frequency adjustment signal, so that the generated data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal. Through the above method, the data stream clock signal generation circuit of the present invention can make the generated data stream clock signal dynamically equal to the initial data stream clock signal of the source device that sends the video signal, and then use the cache module to buffer the dynamic drift in frequency, so that the data cached in the cache module fluctuates up and down. As long as overflow or underflow does not occur, dynamic balance is achieved, avoiding data loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 1 is a schematic structural diagram of an embodiment of a circuit for generating a data stream clock signal according to the present invention;

[0018] Figure 2 1 is a timing diagram of an embodiment of a data stream clock signal generated by the present invention;

[0019] Figure 3 It is a flow chart of an embodiment of a method for generating a data stream clock signal according to the present invention. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0021] The present invention provides a data stream clock signal generation circuit, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of a data stream clock signal generation circuit according to the present invention. In this embodiment, the data stream clock signal generation circuit includes a phase-locked loop module 110 and a frequency tracking module 120. Phase-locked loop module 110 can be considered as generating the initial data stream clock signal, while frequency tracking module 120 can be considered as subsequently tracking the frequency of the data stream clock signal.

[0022] The frequency tracking module 120 is configured to generate a frequency adjustment signal according to the blanking interval end flag signal and the horizontal synchronization signal.

[0023] Among them, the blanking area end mark signal is a pulse signal generated in the video signal emitted by the source device according to the position of the blanking area end mark on the time axis; the horizontal synchronization signal is a horizontal synchronization signal in the timing format signal group that controls the display of the picture generated according to the data stream clock signal.

[0024] In some embodiments, the frequency tracking module 120 is used to receive the tracking signal; in the effective area of ​​the tracking signal (such as Figure 2 The frequency tracking module 120 compares the first position where the blanking area end mark signal pulse appears on the time axis with the second position where the horizontal synchronization signal pulse appears on the time axis, and generates a frequency adjustment signal according to the comparison result.

[0025] The phase-locked loop module 110 is connected to the frequency tracking module and is configured to receive a link clock signal and a frequency adjustment signal, generate a data stream clock signal based on the link clock signal, and adjust the frequency of the data stream clock signal based on the frequency adjustment signal so that the generated data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal.

[0026] When the display device receives a video signal and displays it, the source device sends the video signal and the link clock signal to the receiving end of the display IC area. The receiving end generates a timing format signal group for controlling the display of the picture based on the video signal and the link clock signal, and sends the timing format signal group for controlling the display of the picture to the data processor, so that the data processor controls the display panel for display according to the timing format signal group.

[0027] Optionally, the phase-locked loop module includes a voltage-controlled oscillator 113 , an in-loop phase detector 112 , a first calculation module 111 and a second calculation module 114 ; the second calculation module 114 is connected to the frequency tracking module 120 .

[0028] The first calculation module 111 is connected to the in-loop phase detector 112. The first calculation module 111 is used to receive the link clock signal and the first parameter, and input the calculation result of dividing the link clock signal by the first parameter into the in-loop phase detector 112. The output end of the in-loop phase detector 112 is connected to the voltage-controlled oscillator 113.

[0029] The voltage controlled oscillator 113 outputs a data stream clock signal and inputs the data stream clock signal into the second calculation module 114 . The second calculation module 114 inputs a calculation result of dividing the data stream clock signal by a second parameter into the in-loop phase detector 112 .

[0030] Optionally, the first parameter may be an Nvid parameter, and the second parameter may be an Mvid parameter. The Mvid parameter and the Nvid parameter may be obtained through the MSA parameter.

[0031] Optionally, the frequency tracking module 120 includes a phase frequency detector 121 and a modulator 122 ; the modulator 122 is connected to the phase frequency detector 121 and the phase locked loop module 110 , respectively.

[0032] The frequency detector 121 is used to compare the first position of the pulse of the blanking area end mark signal on the time axis with the second position of the pulse of the horizontal synchronization signal on the time axis within the effective area of ​​the tracking signal to obtain a comparison result; the modulator 122 is used to generate a frequency adjustment signal according to the comparison result.

[0033] The data stream clock signal generation circuit of this embodiment can be applied to technologies that dynamically change the frame refresh rate. For example, free-sync is a technology that can achieve a dynamically variable refresh rate. Free-sync is transmitted via a DP (DisplayPort) video signal.

[0034] Dynamically changing frame refresh rate technology encompasses the production of video content, the rendering of live video, and the display of video on display devices. This constitutes an industry chain, and all devices in this chain must support dynamic variable refresh rate technology within the same specifications. The source device reads the display device's data to determine whether the display supports dynamic frame refresh rate changes. It then performs a handshake with the display device to confirm that both parties support this capability before transmitting the signal format for dynamically changing frame refresh rates.

[0035] The timing format signal group that controls the screen display includes the horizontal synchronization signal HS, the vertical synchronization signal VS, the data valid signal (Data Enable, DEN), the pixel signal, and the data stream clock signal. The pixel signal includes R (Vr), G (Yg), and B (Ub) signals.

[0036] When it is determined that the first blanking area end mark BE of each frame in the video signal arrives, the picture data in the video signal is stored in the cache module FIFO; in response to the rising edge of the data valid signal DEN, the picture data is read from the cache module FIFO.

[0037] The purpose of the frequency tracking module is to make the frequency of the data stream clock signal nearly equal to the frequency of the original data stream clock signal of the source device to avoid overflow or underflow in the buffer module and data loss. To achieve this goal, it can be ensured that the time period between the original BE and BE is equal to the period between HS and HS in the timing format signal group of the control screen display reconstructed by the reference data stream clock signal. In fact, due to the sensitivity limitations of the voltage-controlled oscillator of the phase-locked loop module, it is impossible to achieve complete equality in the circuit, but it is possible to achieve dynamic equality, that is, the average period over a period of time is equal. The buffer module is then used to buffer the dynamic drift in frequency, so that the data cached in the buffer module fluctuates up and down. As long as overflow or underflow is maintained, dynamic balance is achieved.

[0038] If the horizontal synchronization signal HS appears later than the blanking area end mark BE, the frequency of the data stream clock signal will be accelerated; if the horizontal synchronization signal HS appears earlier than the blanking area end mark BE, the frequency of the data stream clock signal will be slowed down.

[0039] In summary, this embodiment provides a data stream clock signal generation circuit, including a frequency tracking module and a phase-locked loop module. The frequency tracking module can generate a frequency adjustment signal based on the blanking area end mark signal and the horizontal synchronization signal; the phase-locked loop module can generate a data stream clock signal based on the link clock signal, and adjust the frequency of the data stream clock signal according to the frequency adjustment signal, so that the generated data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal, and then use the cache module to buffer the dynamic drift in frequency, which can avoid data loss caused by overflow or underflow of the cache due to unequal periods.

[0040] The following describes a method for generating a data stream clock signal provided by the present invention. The method for generating a data stream clock signal described below and the circuit for generating a data stream clock signal described above can refer to each other.

[0041] The present invention also provides a method for generating a data stream clock signal. Figure 2-3 , Figure 2 1 is a timing diagram of an embodiment of a data stream clock signal generated by the present invention. Figure 3 FIG. 1 is a flow chart of an embodiment of a method for generating a data stream clock signal according to the present invention. In this embodiment, the method for generating a data stream clock signal includes steps S110 to S120, each of which is as follows:

[0042] S110: Generate a frequency adjustment signal according to the blanking area end flag signal and the horizontal synchronization signal.

[0043] Among them, the blanking area end mark signal is a pulse signal generated in the video signal emitted by the source device according to the position of the blanking area end mark on the time axis; the horizontal synchronization signal is a horizontal synchronization signal in the timing format signal group that controls the display of the picture generated according to the data stream clock signal.

[0044] Optionally, the step of generating a frequency adjustment signal according to the blanking area end flag signal and the horizontal synchronization signal specifically includes:

[0045] Receive the tracking signal; within the effective area of ​​the tracking signal, compare the first position of the blanking area end mark signal pulse on the time axis with the second position of the horizontal synchronization signal pulse on the time axis, and generate a frequency adjustment signal based on the comparison result.

[0046] In some embodiments, the step of generating a frequency adjustment signal according to the comparison result specifically includes:

[0047] If the second position on the time axis is later than the first position, a first instruction is generated, which speeds up the frequency of the data stream clock signal; if the second position on the time axis is earlier than the first position, a second instruction is generated, which slows down the frequency of the data stream clock signal.

[0048] S120: Receive a link clock signal and a frequency adjustment signal, generate a data stream clock signal according to the link clock signal, and adjust the frequency of the data stream clock signal according to the frequency adjustment signal so that the generated data stream clock signal is dynamically equal to the initial data stream clock signal of the source device that sends the video signal.

[0049] Furthermore, in some embodiments, the step of generating a frequency adjustment signal according to the comparison result further includes:

[0050] Determine a deviation time based on the first position and the second position; generate a frequency acceleration instruction based on the deviation time; and determine an acceleration of the frequency change of the data stream clock signal based on the acceleration instruction. The frequency change of the data stream clock signal includes frequency acceleration and frequency deceleration.

[0051] For example, if the horizontal sync signal pulse is followed by the blanking interval end marker pulse, it indicates that the data stream clock signal is slow and needs to be accelerated. The frequency tracking module's phase frequency detector measures the deviation time between the two and counts it using a delta value. The comparison result is sent to the modulator. The modulator uses this control signal combined with the delta value to calculate the parameters that affect the frequency change of the voltage-controlled oscillator in the phase-locked loop module. The modulator then sends the new parameters to the phase-locked loop module, causing the phase-locked loop module to generate a new data stream clock signal frequency.

[0052] exist Figure 2 In the embodiment, the horizontal synchronization signal pulse HS' is obtained based on the horizontal synchronization signal HS and the DIV parameter; the blanking area end mark pulse BE' is obtained based on the blanking area end mark signal BE and the DIV parameter. Specifically, BE'=BE / DIV; HS'=HS / DIV.

[0053] Optionally, the comparison result may include a frequency acceleration instruction, a first instruction, and a second instruction. The first instruction and the second instruction may be represented by "0" and "1." For example, the first instruction is a control signal with Up = 1 and Down = 0; the second instruction is a control signal with Up = 0 and Down = 1. The frequency acceleration instruction may be represented by a delta value. The frequency acceleration instruction may be used in conjunction with the first and second instructions to control the frequency change of the data stream clock signal.

[0054] The δ value can be positive or negative. When the frequency acceleration instruction is used with the first instruction, the frequency of the data stream clock signal increases, and the δ value is a positive number greater than 0. When the frequency acceleration instruction is used with the second instruction, the frequency of the data stream clock signal decreases, and the δ value is a negative number less than 0.

[0055] And the absolute value of the δ value is related to the distance between the first position and the second position. When the distance between the first position and the second position is greater, the absolute value of the δ value is greater, and the frequency adjustment speed of the data stream clock signal is faster; when the distance between the first position and the second position is smaller, the absolute value of the δ value is smaller, and the frequency adjustment speed of the data stream clock signal is slower.

[0056] When the next horizontal synchronization signal HS reconstructed from the newly generated frequency is compared with the next blanking interval end mark BE, the aforementioned method is continued to obtain new parameters for whether the phase-locked loop module should speed up or slow down. This cycle can maintain an average dynamic balance between the period of the actual output horizontal synchronization signal HS and the period of the blanking interval end mark BE, thereby achieving a reconstructed data stream clock signal that is substantially equal to the original frequency of the source device.

[0057] like Figure 2 As shown, in response to the rising edge of the tracking signal, the blanking area end marker signal BE' and the horizontal synchronization signal begin to be compared. Specifically, the first position where a pulse of the blanking area end marker signal BE' appears on the time axis is compared with the second position where a pulse of the horizontal synchronization signal HS' appears on the time axis. It can be seen that in the first cycle, the second position is later than the first position, so a command (Up = 1, Down = 0, δ = a) is generated and sent to the modulator.

[0058] In the second cycle, the second position is later than the first position, and an instruction (Up=1, down=0, δ=b) is generated and sent to the modulator; wherein a>b.

[0059] In the third cycle, the second position is earlier than the first position, so a command (Up=0, down=1, δ=-c) is generated and sent to the modulator. After that, the tracking signal is low, so the comparison between the blanking area end mark BE' signal and the horizontal synchronization signal HS' is stopped.

[0060] In response to the next rising edge of the tracking signal, the blanking area end marker BE' signal and the horizontal synchronization signal HS' are compared. In the fourth cycle, if the second position is earlier than the first position, a command (Up = 0, Down = 1, δ = -d) is generated and sent to the modulator. Where c < d.

[0061] In the fifth cycle, the second position is equal to the first position, and an instruction (Up=0, down=0, δ=0) is generated and sent to the modulator.

[0062] In summary, this embodiment provides a method for generating a data stream clock signal. The method generates a frequency adjustment signal based on a blanking interval end marker signal and a horizontal synchronization signal. The method receives a link clock signal and a frequency adjustment signal, generates a data stream clock signal based on the link clock signal, and adjusts the frequency of the data stream clock signal based on the frequency adjustment signal to dynamically equalize the generated data stream clock signal with the initial data stream clock signal of the source device transmitting the video signal. The frequency adjustment signal can be used to adjust the frequency of the data stream clock signal using a first instruction, a second instruction, and a frequency acceleration instruction, thereby achieving fine frequency adjustment, ensuring clock signal synchronization, and preventing video data loss.

[0063] The present invention further provides an electronic device. In this embodiment, the electronic device may include any of the aforementioned data stream clock signal generating circuits. The steps and principles thereof have been described in detail in the aforementioned method and will not be repeated here.

[0064] On the other hand, the present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the data stream clock signal generation method provided by the above methods. Its steps and principles have been introduced in detail in the above methods and will not be repeated here.

[0065] The circuit embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of these modules may be selected based on actual needs to achieve the objectives of this embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0066] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A data stream clock signal generating circuit, characterized in that: Applied to dynamically change the frame refresh rate, the data stream clock signal generation circuit includes: a phase-locked loop module and a frequency tracking module; The frequency tracking module is configured to generate a frequency adjustment signal based on a blanking area end marker signal and a horizontal synchronization signal; wherein the blanking area end marker signal is a pulse signal generated in the video signal emitted by the source device according to the position of the blanking area end marker on the time axis; and the horizontal synchronization signal is a horizontal synchronization signal in a timing format signal group for controlling picture display generated based on the data stream clock signal; the phase-locked loop module is connected to the frequency tracking module and is configured to receive a link clock signal and the frequency adjustment signal, generate a data stream clock signal according to the link clock signal, and adjust the frequency of the data stream clock signal according to the frequency adjustment signal so that the generated data stream clock signal is dynamically equal to an initial data stream clock signal of a source device transmitting the video signal; The frequency tracking module is used to receive a tracking signal; within the effective area of ​​the tracking signal, the frequency tracking module compares the first position where the pulse of the blanking area end mark signal appears on the time axis with the second position where the pulse of the horizontal synchronization signal appears on the time axis, and generates the frequency adjustment signal based on the comparison result.

2. The data stream clock signal generating circuit according to claim 1, characterized in that: The frequency tracking module includes a frequency detector and a modulator; The modulator is connected to the frequency detector and the phase-locked loop module respectively; the frequency detector is used to compare the first position where the pulse of the blanking area end mark signal appears on the time axis with the second position where the pulse of the horizontal synchronization signal appears on the time axis within the effective area of ​​the tracking signal to obtain the comparison result; The modulator is configured to generate the frequency adjustment signal according to the comparison result.

3. The data stream clock signal generating circuit according to claim 1, characterized in that: The phase-locked loop module includes a voltage-controlled oscillator, an in-loop phase detector, a first calculation module and a second calculation module; the second calculation module is connected to the frequency tracking module; The first calculation module is connected to the in-loop phase detector, and is configured to receive the link clock signal and a first parameter, and input a calculation result of dividing the link clock signal by the first parameter into the in-loop phase detector; The output end of the in-loop phase detector is connected to the voltage-controlled oscillator, which outputs a data stream clock signal and inputs the data stream clock signal into the second calculation module. The second calculation module inputs a calculation result of dividing the data stream clock signal by a second parameter into the in-loop phase detector.

4. A method for generating a data stream clock signal, characterized in that: Applied to dynamically change the frame refresh rate, the method for generating the data stream clock signal includes: generating a frequency adjustment signal based on a blanking area end marker signal and a horizontal synchronization signal; wherein the blanking area end marker signal is a pulse signal generated in the video signal emitted by the source device according to the position of the blanking area end marker on the time axis; and the horizontal synchronization signal is a horizontal synchronization signal in a timing format signal group for controlling picture display generated based on the data stream clock signal; receiving a link clock signal and the frequency adjustment signal, generating a data stream clock signal according to the link clock signal, and adjusting the frequency of the data stream clock signal according to the frequency adjustment signal so that the generated data stream clock signal is dynamically equal to an initial data stream clock signal of a source device transmitting the video signal; Generating a frequency adjustment signal according to the blanking area end flag signal and the horizontal synchronization signal includes: receiving tracking signals; In the effective area of ​​the tracking signal, the first position where the blanking area end mark signal pulse appears on the time axis is compared with the second position where the horizontal synchronization signal pulse appears on the time axis, and the frequency adjustment signal is generated according to the comparison result.

5. The method for generating a data stream clock signal according to claim 4, wherein: Generating the frequency adjustment signal according to the comparison result includes: If the second position is later than the first position on the time axis, a first instruction is generated, wherein the first instruction increases the frequency of the data stream clock signal; If the second position is earlier than the first position on the time axis, a second instruction is generated, wherein the second instruction slows down the frequency of the data stream clock signal.

6. The method for generating a data stream clock signal according to claim 5, wherein: The generating the frequency adjustment signal according to the comparison result further includes: determining a deviation time based on the first position and the second position; generating a frequency acceleration instruction according to the deviation time; The acceleration of the frequency change of the data stream clock signal is determined according to the acceleration instruction.

7. An electronic device, characterized in that: A circuit for generating a data stream clock signal comprising the circuit according to any one of claims 1 to 3.

8. A computer-readable storage medium comprising a computer program, characterized in that When the computer program is executed by a processor, the method for generating a data stream clock signal according to any one of claims 4 to 6 is implemented.

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