Multilayer circuit board and method for manufacturing the same

Abstract

The application discloses a multilayer circuit board and a preparation method thereof, and relates to the technical field of printed circuit boards. The multilayer circuit board comprises: a plurality of layer plates which are arranged in a stack, the plurality of layer plates are symmetrically arranged about a center plane which is perpendicular to the stacking direction, and the top of each layer plate is provided with a load chip; the multilayer circuit board is provided with a power supply via, and the power supply via penetrates through the plurality of layer plates; the multilayer circuit board is also provided with guide holes, the guide holes are arranged on part of the plurality of layer plates, and the guide holes are used for electrically connecting part of the pins of the load chip and a signal transmission layer in the plurality of layer plates; wherein, the guide holes are multiple; at least part of the plurality of guide holes are multi-stage blind buried holes formed by laser. The embodiment of the application enables the power supply layer to meet the CAF test condition, so that the multilayer circuit board can meet the CAF test condition.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, specifically to a multilayer circuit board and its fabrication method. Background Technology

[0002] In related technologies, circuit boards used in vehicles typically have through-holes, some of which serve as power vias and others as signal vias. To ensure the circuit board meets CAF (Conductive Anodic Filament) test conditions, the distance between the wall of a power via and the wall of a nearby signal via must be greater than or equal to 0.4 mm, and the distance between the wall of a power via and copper traces with different electrical properties must be greater than or equal to 0.17 mm.

[0003] With the rapid development of vehicle intelligence technology, the chips used have more and more functions and more and more pins, while the packaging space left for the chips is getting smaller and smaller. This makes the pin spacing smaller and smaller, which makes it impossible to meet the CAF test conditions in the circuit board. Summary of the Invention

[0004] This application aims to at least partially address one of the technical problems in the related art. To this end, this application provides a multilayer circuit board and a method for fabricating the same.

[0005] In a first aspect, embodiments of this application provide a multilayer circuit board, comprising: a plurality of stacked layers, the plurality of layers being symmetrically arranged about a central plane perpendicular to the stacking direction, and a load chip being disposed on the top of each layer; the multilayer circuit board having power vias that penetrate through the plurality of layers; the multilayer circuit board also having guide holes, the guide holes being formed on a portion of the plurality of layers, the guide holes being used to electrically connect a portion of the pins of the load chip to a signal transmission layer in the plurality of layers; wherein, there are a plurality of guide holes; at least a portion of the plurality of guide holes are multi-stage blind-buried vias formed by laser.

[0006] In some embodiments, the signal transmission layer includes multiple layers; the signal transmission layer closer to the top of the multiple signal transmission layers is electrically connected to a portion of the pins of the load chip through the multi-level blind via.

[0007] In some embodiments, a portion of the plurality of guide holes are mechanically drilled holes, the depth of which is greater than the depth of the multi-stage blind vias; the signal transmission layer further from the top of the plurality of signal transmission layers is electrically connected to a portion of the pins of the load chip through the mechanically drilled holes, or electrically connected to a portion of the pins of the load chip through both the multi-stage blind vias and the mechanically drilled holes.

[0008] In some embodiments, the mechanically drilled hole is disposed in a non-power layer; some of the signal transmission layers are located below the power layer, and the signal transmission layers located below the power layer are electrically connected to some pins of the load chip through the mechanically drilled hole and multi-stage blind and buried vias formed in the power layer.

[0009] In some embodiments, the plurality of layers include: a top layer, an intermediate layer, and a bottom layer, wherein the intermediate layer is located between the top layer and the bottom layer; the intermediate layer includes a power layer and a signal transmission layer, a ground layer is disposed between two adjacent signal transmission layers, and a ground layer is disposed between the signal transmission layer and the adjacent power layer; some pins of the load chip are electrically connected to the power layer through the power via.

[0010] In some embodiments, the power layer includes a first power layer; the guide hole includes a first mechanical borehole; the first mechanical borehole extends from the top layer to a ground layer adjacent to and above the first power layer.

[0011] In some embodiments, a plurality of signal transmission layers are disposed between the top layer and the first power layer; the signal transmission layer closer to the top of the plurality of signal transmission layers has a laser-formed multi-level blind via on the corresponding layer plate of the top layer, so that the signal transmission layer closer to the top of the plurality of signal transmission layers is electrically connected to the pins of the load chip through the multi-level blind via; the signal transmission layer closer to the first power layer of the plurality of signal transmission layers is electrically connected to the pins of the load chip through the first mechanically drilled hole.

[0012] In some embodiments, the power layer further includes a second power layer spaced apart from the first power layer, the second power layer being located below the first power layer, and a dielectric layer being disposed between the second power layer and the first power layer; the guide hole further includes a second mechanical borehole; the second mechanical borehole extends from the bottom layer to a ground layer adjacent to and located below the second power layer.

[0013] In some embodiments, the signal transmission layer is disposed between the bottom layer and the second power layer; the layer plate located between the first mechanical hole and the second mechanical hole is provided with laser-formed multi-stage blind and buried vias, so that the signal transmission layer is electrically connected to some pins of the load chip through the first mechanical hole, the multi-stage blind and buried vias and the second mechanical hole.

[0014] The multilayer circuit board provided in this application embodiment comprises multiple stacked layers, with a load chip disposed on the top of each layer. The multiple layers are symmetrically arranged about a center plane perpendicular to the stacking direction. The multilayer circuit board includes power vias that penetrate the multiple layers. It also includes guide holes, which are formed on some of the layers and used to electrically connect some pins of the load chip to a signal transmission layer within the layer. Multiple guide holes are provided, and at least some of them are multi-stage blind / buried vias formed by laser engraving. In this way, some pins of the top-mounted load chip can be electrically connected to the signal transmission layer through the guide holes. The guide holes do not require space on the power layer, or they require relatively little space, allowing the power layer to have more space for power vias. This enables the power layer to meet CAF test conditions, thereby enabling the multilayer circuit board to meet CAF test conditions.

[0015] Secondly, embodiments of this application provide a method for manufacturing a multilayer circuit board as described in any of the preceding claims, wherein the multilayer circuit board includes a plurality of stacked layers, and the plurality of layers are symmetrically arranged about a central plane perpendicular to the stacking direction;

[0016] The preparation method includes:

[0017] Select the symmetrical layers located on both sides of the central plane from among multiple layers;

[0018] The symmetrically placed layers on both sides of the central plane are placed and pressed together to obtain a layer assembly.

[0019] The shelving units are placed symmetrically and assembled so that the two shelving units on the same layer after assembly are symmetrical.

[0020] Simultaneously, guide holes are processed on the assembled layer panels; wherein, the guide holes include multi-stage blind holes formed by laser or mechanical drilling holes.

[0021] In some embodiments, the plurality of layers include: a top layer, an intermediate layer, and a bottom layer, wherein the intermediate layer is located between the top layer and the bottom layer;

[0022] The intermediate layer includes a power layer and a signal transmission layer. A ground layer is provided between two adjacent signal transmission layers, and a ground layer is provided between a signal transmission layer and its adjacent power layer. The power layer has a first power layer and a second power layer that are spaced apart. A dielectric layer is provided between the first power layer and the second power layer, and the first power layer is located above the second power layer.

[0023] The top layer to the ground layer adjacent to and above the first power layer is symmetrical to the bottom layer to the ground layer adjacent to and below the second power layer.

[0024] The ground layer adjacent to and above the first power layer, and the corresponding layer of the first power layer, are symmetrical with the ground layer adjacent to and below the second power layer.

[0025] The first power layer to the dielectric layer adjacent to and below the first power layer are symmetrical with the second power layer to the dielectric layer adjacent to and above the second power layer.

[0026] The preparation method provided in this application involves splitting symmetrical layer boards, placing symmetrical layer boards located on both sides of the central plane, and simultaneously pressing them together to obtain a layer board group. The layer board groups are then symmetrically placed and assembled, such that the layer boards in the same layer of the two assembled layer board groups are symmetrical. At the same time, guide holes are processed on the two assembled layer board groups, which can reduce the number of pressing and hole processing steps, simplify the processing flow of multilayer circuit boards, shorten the production cycle, and reduce production costs.

[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0028] Figure 1a This is a schematic diagram showing the location of the power via and other vias;

[0029] Figure 1b This is a schematic diagram showing the location of power vias and other electrical property copper foils.

[0030] Figure 1c This is a schematic diagram showing the relative positions of the power supply system and the 0.65pitch BGA load chip.

[0031] Figure 1d This is a schematic diagram of the pinout for a 0.65pitch BGA load cell.

[0032] Figure 1e This is a schematic diagram of the via distribution on the power layer of a circuit board in related technologies;

[0033] Figure 2 This is a schematic diagram of the structure of a multilayer circuit board provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the structure of a multilayer circuit board provided in another embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the structure of a 16-layer plate provided in one embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the structure of a 16-layer plate provided in another embodiment of this application;

[0037] Figure 6 This is a schematic flowchart of a preparation method provided in an embodiment of this application.

[0038] Explanation of reference numerals in the attached figures:

[0039] 1. Layer; 11. Top Layer; 12. Middle Layer; 121. Power Layer; 121a. First Power Layer; 121b. Second Power Layer; 122. Signal Transmission Layer; 123. Ground Layer; 124. Dielectric Layer; 13. Bottom Layer;

[0040] 21. Power supply via; 22. Pilot hole; 221. Multi-stage blind buried via; 221a. Second-stage blind buried via; 222. Mechanical drilling; 222a. First mechanical drilling; 222b. Second mechanical drilling;

[0041] 3. Load chip. Detailed Implementation

[0042] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0043] In related technologies, circuit boards used in vehicles typically have through-hole vias, some of which serve as power vias and others as signal vias. These circuit boards usually need to meet CAF (Constant Airflow) test conditions. The CAF test conditions are: temperature 85℃, humidity 85%, bias voltage 100V, test time 1000 hours, and the judgment criterion is a resistance ≥10MΩ. Circuit boards that meet the above CAF test conditions, such as... Figure 1a and Figure 1b As shown, the distance d1 between the hole wall (drill edge) of the power via and the hole wall (drill edge) of other vias is required to be ≥0.4mm, and the distance d2 between the hole wall (drill edge) of the power via and other electrical property copper foils is required to be ≥0.275mm.

[0044] When the circuit board is accepted according to IPC CLASS 3 standards, the minimum finished via diameter is 0.2mm, the drill bit diameter is 0.25mm, and the via pad diameter is 0.4mm (as shown in the via ring diameter in the figure). However, when the load chip on this circuit board uses a 0.65mm pitch BGA package, where 65mm pitch refers to the distance between the center of the pins of the device and the center of the adjacent pins, the circuit board cannot meet the CAF test conditions.

[0045] Specifically, the circuit board features through-hole vias, following a traditional via routing method. The pins of the 0.65mm pitch BGA are led out from the layer through these vias to achieve electrical connections with other components. During operation, such as... Figure 1c As shown, current needs to be output from the power supply system through power vias in the board to the power pins of the 0.65mm pitch BGA. The area where the power pins are located is as follows: Figure 1d As shown.

[0046] like Figure 1e As shown, the center-to-center pin spacing in a 0.65-pitch BGA is 0.65 mm. The reasonable via spacing on the circuit board is d3 = 0.65 mm. The via pad diameter is 0.4 mm. The minimum copper trace width for the power layer is d4 = 0.1 mm. The non-power via-to-copper trace spacing (i.e., the distance from the edge of the via pad to the copper trace) is A = (0.65 - 0.4 - 0.1) / 2 = 0.075 mm. The copper trace to drill bit spacing is B = 0.075 + (0.4 - 0.25) / 2 = 0.15 mm, which is far less than the 0.275 mm required by CAF testing conditions, thus failing to meet CAF testing requirements. Therefore, the area on the circuit board corresponding to the 0.65 mm pitch BGA, especially the power layer in this area, is the bottleneck area of ​​the circuit board design.

[0047] To overcome the above problems, this application provides a multilayer circuit board. By setting guide holes on the multilayer circuit board, each guide hole is opened on a portion of multiple layers, so that some pins of the load chip are electrically connected to the signal transmission layer of the multilayer circuit board through the guide holes. This allows the load chip to be electrically connected to external devices through the signal transmission layer. In this way, the guide holes do not need to occupy the space of the power layer, or the guide holes occupy relatively little space on the power layer, so that the power layer has more space for laying power vias. This enables the power layer of the multilayer circuit board to meet the CAF test conditions, thereby enabling the multilayer circuit board to meet the CAF test conditions.

[0048] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0049] Please refer to Figure 2 The circuit board provided in this application embodiment is a multilayer circuit board, which has multiple stacked layers 1. A load chip 3 is disposed on one side of each layer 1. For ease of description, the stacking direction of the multiple layers 1 is referred to as the up-down direction, and the side of the layer 1 used to dispose of the load chip 3 is referred to as the upper side (or top).

[0050] At least some of the multiple layers 1 are symmetrical layers. The multiple layers 1 have a central plane Z parallel to the horizontal plane or perpendicular to the stacking direction. This central plane Z can serve as a symmetry plane, and at least some of the multiple layers 1 are symmetrically arranged about this central plane Z. Taking an 8-layer multilayer circuit board as an example, the top 4 layers 1 and the bottom 4 layers 1 are symmetrical about the central plane Z. Taking a 16-layer multilayer circuit board as another example, the top 8 layers 1 and the bottom 8 layers 1 are symmetrical about the central plane Z.

[0051] The multilayer circuit board is provided with power vias 21, which penetrate multiple layers 1. For example, in a multilayer circuit board with 16 layers, the power vias 21 penetrate all 16 layers 1. The power vias 21 are used to electrically connect the power pins of the load chip 3 to the power layer 121 in the multilayer circuit board.

[0052] The multilayer circuit board also includes vias 22, which are formed on portions of the multiple layers 1. These vias 22 are used to electrically connect some pins of the load chip 3 to the signal transmission layer 122 in the layer 1. Specifically, the pins of the load chip 3 can be electrically connected to the signal transmission layer 122 in the layer 1 through one or more vias 22. Furthermore, the walls of the vias 22 can be coated with a conductive material to give them conductive properties.

[0053] For example, for the signal transmission layer 122 located above the power layer 121, the via 22 can extend from the top of the multilayer circuit board to the signal transmission layer 122, electrically connecting some pins of the load chip 3 to the signal transmission layer 122. In this way, the electrical connection channel between some pins of the load chip 3 and the signal transmission layer 122 located above the power layer 121 does not need to occupy the space of the power layer 121.

[0054] There may be multiple guide holes 22, each of which is formed on a portion of a plurality of layers 1. For example, at least some of the multiple guide holes 22 are multi-level blind buried vias 221, such as second-order or third-order blind buried vias. Specifically, the multi-level blind buried via 221 can be a laser-formed via with a diameter smaller than that of vias in related technologies; for example, the diameter of the multi-level blind buried via 221 is smaller than that of a power supply via 21.

[0055] For example, for the signal transmission layer 122 located above the power layer 121, a multi-level blind via 221 can be provided in the top of the multilayer circuit board and the layer corresponding to the signal transmission layer 122, and some pins of the load chip 3 can be electrically connected to the signal transmission layer 122 through the multi-level blind via 221.

[0056] Additionally, the signal transmission layer 122, located below the power layer 121, can also be electrically connected to some pins of the load chip 3 via multi-stage blind / buried vias 221. Multi-stage blind / buried vias 221 can be provided from the top of the layer circuit board to the layer corresponding to the signal transmission layer 122 below the power layer 121. Thus, since the diameter of the laser-formed multi-stage blind / buried vias is smaller than the diameter of vias in related technologies, the space occupied by the power layer 121 can be reduced.

[0057] For example, in a multilayer circuit board, the power layer 121 is located in the middle. A signal transmission layer 122 can be disposed on top of the power layer 121. A ground layer 123 can be disposed between the power layer 121 and the signal transmission layer 122. A top layer 11 is disposed on top of the signal transmission layer 122, and a ground layer 123 is also disposed between the signal transmission layer 122 and the top layer 11. A ground layer 123, a signal transmission layer 122, a ground layer 123, and a bottom layer 13 can also be disposed on the bottom of the power layer 121. The signal transmission layer 122 located on top of the power layer 121 is closer to the load chip 3, while the signal transmission layer 122 located on the bottom of the power layer 121 is farther away from the load chip 3.

[0058] In the five side layers 1 corresponding to the top layer 11 of the multilayer circuit board and the signal transmission layer 122 located above the power layer 121, multi-level blind and buried vias 221 can be provided, so that some pins of the load chip 3 can be electrically connected to the signal transmission layer 122 located above the power layer 121 through the multi-level blind and buried vias 221. In this way, the multi-level blind and buried vias 221 that electrically connect some pins of the load chip 3 to the signal transmission layer 122 located above the power layer 121 do not occupy the space of the power layer 121.

[0059] In the side layer 1 corresponding to the signal transmission layer 122 above the power layer 121 to the signal transmission layer 0 122 below the power layer 121, multi-level blind and buried vias 221 can also be provided, so that some pins of the load chip 3 can be electrically connected to the signal transmission layer 122 below the power layer 121 through the multi-level blind and buried vias 221. In this way, since the aperture of the multi-level blind and buried vias 221 formed by laser is relatively small, the space occupied by the laser on the power layer 121 can also be reduced.

[0060] In this example, the above settings can reduce the space occupied by the power layer 121, so that the power layer 121 has more space for power vias 21, and the power layer 121 can meet the CAF test conditions, thereby enabling the multi-layer circuit board to meet the CAF test conditions.

[0061] In some examples, some of the multiple guide holes 22 are multi-stage blind holes 221, and some of the multiple guide holes 22 are mechanically drilled holes 222. The depth of the mechanically drilled holes 222 is greater than the depth of the multi-stage blind holes 221.

[0062] The signal transmission layer 122, which is relatively close to the load chip 3 at the top of the multilayer circuit board, can be electrically connected to some pins of the load chip 3 through multi-level blind vias 221. The signal transmission layer 122, which is relatively far from the load chip 3 at the top of the multilayer circuit board, can be electrically connected to some pins of the load chip 3 through mechanically drilled holes 222, or through a combination of multi-level blind vias 221 and mechanically drilled holes 222.

[0063] Where part of the signal transmission layer 122 is located below the power layer 121, the mechanically drilled vias 2225 can be disposed in a non-power layer, which refers to the layers in a multilayer circuit board other than the power layer 121. Multiple-stage blind and buried vias 221 are disposed in the power layer 121, and the signal transmission layer 122 located below the power layer 121 can be electrically connected to some pins of the load chip 3 through the mechanically drilled vias 222 and the multiple-stage blind and buried vias 221.

[0064] For example, mechanically drilled holes 222 can be provided in the side layer 1 corresponding to the ground layer 123 to the bottom layer 13, which are adjacent to and located below the power layer 121. Multi-level blind and buried vias 221 can be provided in the signal transmission layer 122 located above the power layer 121 to the ground layer 123 adjacent to and located below the power layer 121. In this way, the multi-level blind and buried vias 221 in the top layer 11 to the ground layer 123 adjacent to and located below the power layer 121, and the mechanically drilled holes 222 in the side layer 1 corresponding to the ground layer 123 adjacent to and located below the power layer 121, can electrically connect some pins of the load chip 3 to the signal transmission layer 122 located below the power layer 121.

[0065] For example, a ground layer 123, a signal transmission layer 122, a ground layer 123, a signal transmission layer 122, a ground layer 123, and a top layer 11 can be sequentially arranged on the upper side of the power layer 121. One signal transmission layer 122 is closer to the top load chip 3 and farther away from the power layer 121, while the other signal transmission layer 122 is farther away from the top load chip 3 and closer to the power layer 121.

[0066] In the side layer 1 corresponding to the signal transmission layer 122 of the top layer 11 to the load chip 3 located closer to the top, multiple-level blind vias 221 can be provided, so that some pins of the load chip 3 can be electrically connected to the load chip 3 closer to the top through the multiple-level blind vias 221. Among them, a second-level blind via is provided in the top layer 11 to the ground layer 123 adjacent to the top layer 11, and a second-level blind via is provided in the ground layer 123 adjacent to the top layer 11 to the load chip 3 closer to the top. The above-mentioned second-level blind vias can electrically connect some pins of the load chip 3 to the load chip 3 closer to the top.

[0067] Mechanical holes 222 can be provided in the top layer 11 to the side layer 1 corresponding to the signal transmission layer 122 located further away from the load chip 3, or in the layer 1 corresponding to the ground layer 123 located adjacent to the power layer 121, so as to electrically connect some pins of the load chip 3 to the signal transmission layer 122 located further away from the load chip 3 through the mechanical holes 222.

[0068] In this example, by setting a relatively deep mechanically drilled hole 222 on the non-power layer, some pins of the load chip 3 are electrically connected to the signal transmission layer 122, which is further away from the load chip 3, through the mechanically drilled hole 222. This reduces the space occupied by the power layer 121, so that the power layer 121 can meet the CAF test conditions, thereby enabling the multilayer circuit board to meet the CAF test conditions. It also reduces the number of holes and simplifies the fabrication process of the multilayer circuit board.

[0069] Of course, the arrangement of the multi-stage blind vias 221 and the mechanically drilled holes 222 is not limited to this, and this embodiment does not impose specific limitations here. In addition, the specific number of power supply vias 21, multi-stage blind vias 221 and mechanically drilled holes 222 can be set according to actual needs, and this embodiment does not impose limitations here.

[0070] The multilayer circuit board provided in this embodiment comprises multiple stacked layers 1, with a load chip 3 disposed on the top of each layer 1. The multiple layers 1 are symmetrically arranged about a central plane Z perpendicular to the stacking direction. The multilayer circuit board includes power vias 21 that penetrate the multiple layers 1. It also includes guide holes 22, which are formed on some of the layers 1. These guide holes 22 are used to electrically connect some pins of the load chip 3 to a signal transmission layer 122 in the layer 1. Multiple guide holes 22 are included, and at least some of them are multi-stage blind / buried vias 221 formed by laser engraving. Thus, some pins of the top-mounted load chip 3 can be electrically connected to the signal transmission layer 122 through the guide holes 22. The guide holes 22 do not need to occupy space in the power layer 121, or they can occupy relatively little space in the power layer 121, allowing the power layer 121 to have more space for the power vias 21. This enables the power layer 121 to meet CAF test conditions, thereby enabling the multilayer circuit board to meet CAF test conditions.

[0071] Please refer to Figure 3 As shown, in some embodiments, the multiple layers 1 of the multilayer circuit board include: a top layer 11, an intermediate layer 12, and a bottom layer 13, with the intermediate layer 12 located between the top layer 11 and the bottom layer 13. The intermediate layer 12 includes a power layer 121 and a signal transmission layer 122, wherein a ground layer 123 is disposed between two adjacent signal transmission layers 122, and a ground layer 123 or a dielectric layer 124 is disposed between the signal transmission layer 122 and its adjacent power layer 121. Some pins of the load chip 3 are electrically connected to the power layer 121 through power vias 21. There may be one or more power layers 121.

[0072] Power layer 121 includes a first power layer 121a. Mechanical bore 222 includes a first mechanical bore 222a; the first mechanical bore 222a extends from top layer 11 to ground layer 123 adjacent to and above the first power layer 121a.

[0073] Multiple signal transmission layers 122 are provided between the top layer 11 and the first power layer 121a; among the multiple signal transmission layers 122, the signal transmission layer 122 closer to the top is provided with a laser-formed multi-level blind via 221 on the corresponding layer plate 1 of the top layer 11, so that the signal transmission layer 122 closer to the top is electrically connected to the pin of the load chip 3 through the laser-formed multi-level blind via 221.

[0074] Specifically, a second-order blind via 221a is provided in the top layer 11 to the ground layer 123 adjacent to the top layer 11, and a second-order blind via 221a is provided in the ground layer 123 adjacent to the top layer 11 to the adjacent signal transmission layer 122. The second-order blind vias 221a can be electrically connected through the wiring of the ground layer 123 or are arranged vertically opposite each other and directly electrically connected. The electrically connected second-order blind vias 221a can electrically connect some pins of the load chip 3 to the signal transmission layer 122 which is closer to the top.

[0075] Among the multiple signal transmission layers 122 between the top layer 11 and the first power layer 121a, the signal transmission layer 122 closer to the first power layer 121a is electrically connected to the pins of the load chip 3 through the first mechanical drill hole 222a. In this way, the multi-stage blind buried via 221 and the first mechanical drill hole 222a do not occupy the space of the first power layer 121a.

[0076] The power layer 121 also includes a second power layer 121b spaced apart from the first power layer 121a, the second power layer 121b being located below the first power layer 121a; a dielectric layer 124 is disposed between the first power layer 121a and the second power layer 121b. The mechanical drill hole 222 also includes a second mechanical drill hole 222b; the second mechanical drill hole 222b extends from the bottom layer 13 to a ground layer 123 adjacent to and located below the second power layer 121b.

[0077] Multiple signal transmission layers 122 are provided between the bottom layer 13 and the second power layer 121b; the layer 1 located between the first mechanical drill hole 222a and the second mechanical drill hole 222b is provided with laser-formed multi-stage blind and buried vias 221 to electrically connect the first mechanical drill hole 222a and the second mechanical drill hole 222b, so that the multiple signal transmission layers 122 are electrically connected to some pins of the load chip 3 through the first mechanical drill hole 222a, the multi-stage blind and buried vias 221 and the second mechanical drill hole 222b.

[0078] For example, a ground layer 123 located above and adjacent to the first power layer 121a is provided with a second-order blind via 221a to the first power layer 121a; a second-order blind via 221a is provided below and adjacent to the first power layer 121a; two dielectric layers 124 located between the first power layer 121a and the second power layer 121b are provided with second-order blind vias 221a; a second-order blind via 221a is provided above and adjacent to the second power layer 121b; and a ground layer 123 located below and adjacent to the second power layer 121b is provided with a second-order blind via 221a to the second power layer 121b.

[0079] In this configuration, second-order blind vias 221a formed in the same layer to two adjacent layers are electrically connected via traces in that layer. Alternatively, second-order blind vias 221a formed in the same layer to two adjacent layers are arranged opposite each other along the stacking direction and are directly electrically connected. For example, second-order blind vias 221a formed in the first power layer 121a to the upper and adjacent ground layer 123, and second-order blind vias 221a formed in the first power layer 121a to the lower and adjacent dielectric layer 124, can be arranged opposite each other and directly electrically connected, or they can be electrically connected via traces in the first power layer 121a.

[0080] Thus, the first mechanical drill hole 222a and the second mechanical drill hole 222b do not require the use of space in the first power layer 121a and the second power layer 121b. The multi-stage blind buried hole 221 formed by laser has a smaller diameter, which can reduce the space occupied in the first power layer 121a and the second power layer 121b.

[0081] In this embodiment, some of the vias 22 do not need to be formed on the power layer 121 to electrically connect some pins of the load chip 3 to the signal transmission layer 122; the vias 22 that need to pass through the power layer 121 are formed by laser engraving, and their apertures are relatively small, occupying relatively little space on the power layer 121. Therefore, through the above arrangement, some space can be saved on the power layer 121, providing relatively more space for the placement of power vias 21 in the power layer 121, which can meet the CAF test conditions, thus enabling multi-layer circuit boards to meet the CAF test conditions.

[0082] In other embodiments, when only a first power layer 121a is provided in the multilayer circuit board, multiple levels of blind vias 221 are formed in the ground layer 123 adjacent to and above the first power layer 121a, and in the ground layer 123 or dielectric layer 124 located below and adjacent to the first power layer 121a. Multiple levels of blind vias 221 or mechanically drilled holes 222 can be provided in the layer 1 below and adjacent to the first power layer 121a to electrically connect the signal transmission layer 122 located below the first power layer 121a to the pins of the load chip 3. Thus, since the size of the laser-formed multiple levels of blind vias 221 is relatively small, the space occupied on the first power layer 121a can be reduced.

[0083] The implementation process of this embodiment will be illustrated below using a multilayer circuit board with 16 layers as an example.

[0084] Please refer to Figures 4 to 5 As shown, the multiple layers 1 of the multilayer circuit board are arranged from top to bottom as follows: TOP, GND02, ART03, GND04, ART05, GND06, POWER07, ART08, ART09, POWER10, GND11, ART12, GND13, ART14, GND15, BOTTOM.

[0085] TOP is the top layer 11. ART03, ART05, ART12, and ART14 are signal transmission layers 122, with ART03 being the signal transmission layer 122 closer to the top, and ART05, ART12, and ART14 being the signal transmission layers 122 further away from the top.

[0086] POWER07 and POWER10 are power layers 121. Among them, POWER07 is the first power layer 121a, ART03 and ART05 are signal transmission layers 122 located between the top layer 11 and the first power layer 121a, POWER10 is the second power layer 121, and ART12 and ART14 are signal transmission layers 122 located between the bottom layer 13 and the second power layer 121b.

[0087] GND02, GND04, GND06, GND11, GND13, and GND15 are grounding layers 123, ART08 and ART09 are dielectric layers 124, and BOTTOM is the bottom layer 13.

[0088] The TOP to BOTTOM section has a power via 21 that runs through 16 layers 1.

[0089] A first mechanical drill hole 222a is provided from TOP to GND06, and a second mechanical drill hole 222b is provided from GND11 to BOTTOM.

[0090] Second-order blind buried vias 221a are provided from TOP to GND02, GND02 to ART03, GND06 to POWER07, POWER07 to ART08, ART08 to ART09, POWER10 to ART09, and GND11 to POWER10. All second-order blind buried vias 221a are laser-drilled vias, with a finished hole diameter of 0.1mm, a laser diameter of 0.15mm, and a pad diameter of 0.25mm. The first mechanical drill hole 222a, the second mechanical drill hole 222b, and the second-order blind buried vias 221a constitute the guide hole 22.

[0091] like Figure 4 As shown, some pins of the load chip 3 can be electrically connected to ART03 through the second-order blind and buried via 221a from TOP to GND02 and the second-order blind and buried via 221a from GND02 to ART03.

[0092] like Figure 5 As shown, a portion of the pins of the load chip 3 can be electrically connected to the ART05 through the first mechanical drill hole 222a set from TOP to GND06.

[0093] A portion of the pins of the load chip 3 can be electrically connected to ART12 through the first mechanical drill hole 222a from TOP to GND06, the second-order blind buried via 221a from GND06 to POWER07, the second-order blind buried via 221a from POWER07 to ART08, the second-order blind buried via 221a from ART08 to ART09, the second-order blind buried via 221a from POWER10 to ART09, the second-order blind buried via 221a from GND11 to POWER10, and the second mechanical drill hole 222b from GND11 to BOTTOM.

[0094] A portion of the pins of the load chip 3 can be electrically connected to ART14 through the first mechanical drill hole 222a from TOP to GND06, the second-order blind buried via 221a from GND06 to POWER07, the second-order blind buried via 221a from POWER07 to ART08, the second-order blind buried via 221a from ART08 to ART09, the second-order blind buried via 221a from POWER10 to ART09, the second-order blind buried via 221a from GND11 to POWER10, and the second mechanical drill hole 222b from GND11 to BOTTOM.

[0095] Taking the load chip 3 as an example, the 0.65pitch BGA can be a 40-row x 40-column pin configuration, with the power supply pins arranged in 12 to 24 rows internally.

[0096] The six rows of pins near the edge of the 0.65pitch BGA (i.e., rows 1 to 6 and rows 40 to 35) can be electrically connected to ART03 via second-order blind / buried vias 221a from TOP to GND02 and from GND02 to ART03, thus bringing out the BGA bottleneck area. A portion of rows 7 to 12 and rows 25 to 34 are electrically connected to ART05 via the first mechanical drill hole 222a from TOP to GND06, also bringing out the BGA bottleneck area. These six layers from TOP to GND06 include two signal transmission layers 122 (Art03 and Art05), occupying 1 / 3 of the total number of inner layer routing layers on the multilayer circuit board. This saves 1 / 3 of the original via space for routing power vias 21 through POWER 07 and POWER10.

[0097] Another portion of rows 7-12 and 25-34 can be electrically connected to ART12 or ART14 via a first mechanical drill hole 222a from TOP to GND06, a second-order blind buried hole 221a from GND06 to POWER07, a second-order blind buried hole 221a from POWER07 to ART08, a second-order blind buried hole 221a from ART08 to ART09, a second-order blind buried hole 221a from POWER10 to ART09, a second-order blind buried hole 221a from GND11 to POWER10, and a second mechanical drill hole 222b from GND11 to BOTTOM, thus bringing out the BGA bottleneck area. Since laser vias are used in POWER 07 and POWER 10, and the laser via size is 5 / 8 the size of the power supply via 21, the laser vias in this embodiment can save 5 / 8 of the space in POWER 07 and POWER 10 compared to vias in related technologies.

[0098] By setting the aforementioned guide hole 22, the space for the power via 21 in POWER 07 and POWER 10 to lay out the power supply pins that are electrically connected to the load chip 3 is greatly increased, which can meet the CAF test conditions, thus enabling multi-layer circuit boards to meet the CAF test conditions.

[0099] This embodiment solves the problem of multilayer circuit boards failing to meet CAF test conditions while ensuring power integrity and signal integrity. Furthermore, the multilayer circuit board provided in this embodiment can shorten the production cycle and reduce costs during the fabrication stage.

[0100] It is understood that this embodiment is illustrated using a 16-layer multilayer circuit board as an example. In practice, this embodiment can also be applied to other multilayer circuit boards having multiple layers 1 symmetrically arranged about a central plane Z perpendicular to the stacking direction, and the implementation process is similar to that described above.

[0101] Furthermore, other configurations and functions of the multilayer circuit boards in the embodiments of this application are known to those skilled in the art, and will not be described in detail here to reduce redundancy.

[0102] Please refer to Figure 6 This embodiment also provides a method for preparing a multilayer circuit board, which is used to prepare the multilayer circuit board in the foregoing embodiment. The structure of the multilayer circuit board is described in the foregoing embodiment and will not be repeated here.

[0103] The preparation method provided in this embodiment may include the following steps:

[0104] S101. Select the symmetrical layer located on both sides of the center plane from among multiple layers.

[0105] The cost corresponding to the opening type and location is for a layer symmetrical about the center plane perpendicular to the stacking direction. Please refer to... Figure 5 For example, in a multilayer circuit board, the TOP layer and the layer adjacent to TOP are symmetrical layers to the BOTTOM layer. Therefore, we take the TOP layer and the layer adjacent to TOP, and the BOTTOM layer and the layer adjacent to BOTTOM.

[0106] S102. Place the symmetrical layers on both sides of the center plane and press them together to obtain a layer assembly.

[0107] The obtained TOP and its adjacent layer are stacked on the lamination table, and the obtained BOTTOM and its adjacent layer are stacked on the lamination table. The layers are then laminated to obtain two layer groups. In other examples, four, six, or more layer groups may be obtained after lamination.

[0108] S103. Place the shelf groups symmetrically and assemble them so that the shelves in the same layer of the two shelf groups after assembly are symmetrical.

[0109] The laminated layer groups are mirrored and then panelized, so that the layers in the two groups that are on the same layer are symmetrical. For example, after panelization, the TOP and BOTTOM layers in the multilayer circuit board correspond to each other (i.e., they are on the same layer), and the layers adjacent to the TOP and BOTTOM layers correspond to each other. The arrangement of other layers is similar.

[0110] S104. Simultaneously, guide holes are machined into the assembled layer panels.

[0111] The pilot holes include multi-stage blind vias or mechanically drilled holes. For example, for a layer that requires multi-stage blind vias, the multi-stage blind vias are formed by laser cutting; for a layer that requires mechanically drilled holes, the holes are drilled.

[0112] The layer groups can be assembled on a machining table, and guide holes can be machined on the assembled layer groups simultaneously. For example, laser engraving can be performed on the TOP layer, the layer group consisting of the layer adjacent to TOP, and the layer group consisting of BOTTOM and the layer group consisting of the layer adjacent to BOTTOM to form second-order blind buried vias.

[0113] In this embodiment, by splitting the symmetrical layer boards, placing the symmetrical layer boards located on both sides of the center plane and pressing them together, a layer board group is obtained. The layer board groups are then placed symmetrically and assembled, so that the layer boards in the same layer of the two assembled layer board groups are symmetrical. At the same time, guide holes are processed on the two assembled layer board groups, which can reduce the number of pressing and hole processing times, simplify the processing flow of multilayer circuit boards, shorten the production cycle, and reduce production costs.

[0114] In some embodiments, the multiple layers of a multilayer circuit board include a top layer, an intermediate layer, and a bottom layer, wherein the intermediate layer is located between the top layer and the bottom layer.

[0115] The intermediate power layer includes a signal transmission layer, a ground layer is provided between two adjacent signal transmission layers, and a ground layer is provided between a signal transmission layer and its adjacent power layer; the power layer has a first power layer and a second power layer that are spaced apart, a dielectric layer is provided between the first power layer and the second power layer, and the first power layer is located above the second power layer.

[0116] The top layer, which corresponds to the ground layer adjacent to and above the first power layer, is symmetrical to the bottom layer, which corresponds to the ground layer adjacent to and below the second power layer.

[0117] The ground plane to the corresponding layer of the first power layer, which is adjacent to and above the first power layer, is symmetrical with the ground plane to the corresponding layer of the second power layer, which is adjacent to and below the second power layer.

[0118] The layers corresponding to the first power layer and the dielectric layer adjacent to and below the first power layer are symmetrical with the layers corresponding to the second power layer and the dielectric layer adjacent to and above the second power layer.

[0119] The dielectric layer adjacent to the first power layer and the dielectric layer adjacent to the second power layer are symmetrical.

[0120] Please refer to Figure 5 The following explanation uses a 16-layer multilayer circuit board as an example. The layers of the multilayer circuit board, from top to bottom, are: TOP, GND02, ART03, GND04, ART05, GND06, POWER07, ART08, ART09, POWER10, GND11, ART12, GND13, ART14, GND15, BOTTOM. TOP is the top layer, ART03, ART05, ART12, and ART14 are signal transmission layers, POWER07 and POWER10 are power layers, GND02, GND04, GND06, GND11, GND13, and GND15 are ground layers, ART08 and ART09 are dielectric layers, and BOTTOM is the bottom layer.

[0121] TOP to GND06 and BOTTOM to GND11 are symmetrical layers. GND06 to POWER07 and GND11 to POWER10 are symmetrical layers. POWER07 to ART08 and POWER10 to ART09 are symmetrical layers.

[0122] During the preparation process, TOP to GND06 and BOTTOM to GND11 are taken; at the same time, TOP to GND06 and BOTTOM to GND11 are pressed together for the first time; TOP to GND06 and BOTTOM to GND11 are spliced ​​together, for example, left and right splicing; at the same time, TOP to GND06 and BOTTOM to GND11 are machined for the first time, specifically by drilling, to obtain a first mechanical drill hole in TOP to GND06 and a second mechanical drill hole in BOTTOM to GND11.

[0123] Take GND06 to POWER07 and GND11 to POWER10, and simultaneously perform a second pressing on the above-mentioned layers to assemble the panels. At the same time, perform a second drilling of the holes using laser technology to obtain second-order blind buried holes.

[0124] Take POWER07 to ART08 and POWER10 to ART09, and simultaneously perform a third pressing on the above-mentioned layers to assemble the panels. At the same time, perform a third drilling of the holes using laser technology to obtain second-order blind buried holes.

[0125] Take ART08 and ART09, assemble them, and simultaneously perform a fourth hole machining process. The fourth hole machining process uses laser technology to obtain second-order blind buried holes.

[0126] The above-mentioned layers are separated into layers, and TOP to ART08, ART08 to ART09, and ART09 to BOTTOM are stacked in sequence for the fourth pressing and the fifth hole processing to obtain the power supply via.

[0127] Thus, this embodiment involves a total of four laminations and five drillings, saving three laminations and three drillings compared to the traditional lamination and drilling process. This simplifies the processing of multilayer circuit boards, shortens the production cycle, and reduces production costs.

[0128] It is understood that this embodiment is illustrated using a 16-layer multilayer circuit board as an example. In practice, the fabrication method of this embodiment can also be applied to other multilayer circuit boards having multiple layers symmetrically arranged about the center plane perpendicular to the stacking direction, and the implementation process is similar to that of the above embodiment.

[0129] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0130] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0131] Furthermore, the terms "first," "second," etc., used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this application can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this application, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly and specifically defined in the embodiments.

[0132] In this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.

[0133] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0134] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A multilayer circuit board, characterized in that, include: Multiple stacked plates are arranged symmetrically about a central plane perpendicular to the stacking direction, and a load chip is provided on the top of each plate. The multilayer circuit board is provided with power vias, which are disposed through multiple layers. The multilayer circuit board is also provided with guide holes, which are formed on some of the multiple layers. The guide holes are used to electrically connect some pins of the load chip to the signal transmission layer in the multiple layers. The guide holes are multiple in number; at least some of the guide holes are multi-stage blind buried holes formed by laser. Some of the guide holes are mechanically drilled, and the depth of the mechanically drilled holes is greater than the depth of the multi-stage blind buried holes; The mechanically drilled hole is located in the non-power layer; some of the signal transmission layers are located below the power layer, and the signal transmission layers located below the power layer are electrically connected to some pins of the load chip through the mechanically drilled hole and the multi-stage blind and buried vias opened in the power layer.

2. The multilayer circuit board according to claim 1, characterized in that, The signal transmission layer includes multiple layers; The signal transmission layer closer to the top of the plurality of signal transmission layers is electrically connected to a portion of the pins of the load chip through the multi-stage blind via.

3. The multilayer circuit board according to claim 2, characterized in that, The signal transmission layer further away from the top of the plurality of signal transmission layers is electrically connected to a portion of the pins of the load chip through the mechanically drilled hole, or through the multi-stage blind via and the mechanically drilled hole.

4. The multilayer circuit board according to any one of claims 1 to 3, characterized in that, The plurality of layers includes: a top layer, an intermediate layer and a bottom layer, wherein the intermediate layer is located between the top layer and the bottom layer; The intermediate layer includes a power layer and a signal transmission layer. A ground layer is provided between two adjacent signal transmission layers, and a ground layer is provided between the signal transmission layer and the adjacent power layer. Some pins of the load chip are electrically connected to the power layer through the power via; The power layer includes a first power layer; the guide hole includes a first mechanical drill hole; the first mechanical drill hole extends from the top layer to a ground layer adjacent to and above the first power layer.

5. The multilayer circuit board according to claim 4, characterized in that, Multiple signal transmission layers are provided between the top layer and the first power layer; The signal transmission layer closer to the top of the multiple signal transmission layers has a multi-level blind via on the corresponding layer plate, so that the signal transmission layer closer to the top of the multiple signal transmission layers is electrically connected to the pins of the load chip through the multi-level blind via. The signal transmission layer closer to the first power layer among the multiple signal transmission layers is electrically connected to the pins of the load chip through the first mechanical drill hole.

6. The multilayer circuit board according to claim 4, characterized in that, The power layer further includes a second power layer spaced apart from the first power layer, the second power layer being located below the first power layer, and a dielectric layer being disposed between the second power layer and the first power layer. The guide hole also includes a second mechanically drilled hole; The second mechanical borehole extends from the bottom layer to the ground layer adjacent to and below the second power layer.

7. The multilayer circuit board according to claim 6, characterized in that, The signal transmission layer is provided between the bottom layer and the second power layer; The layer plate located between the first mechanical drill hole and the second mechanical drill hole is provided with the multi-stage blind and buried vias, so that the signal transmission layer is electrically connected to some pins of the load chip through the first mechanical drill hole, the multi-stage blind and buried vias and the second mechanical drill hole.

8. A method for manufacturing a multilayer circuit board according to any one of claims 1-7, characterized in that, The multilayer circuit board includes multiple stacked layers, which are symmetrically arranged about a central plane perpendicular to the stacking direction. The preparation method includes: Select the symmetrical layers located on both sides of the central plane from among multiple layers; The symmetrically placed layers on both sides of the central plane are placed and pressed together to obtain a layer assembly. The shelving units are placed symmetrically and assembled so that the two shelving units on the same layer after assembly are symmetrical. Simultaneously, guide holes are processed on the assembled layer panels; wherein, the guide holes include multi-stage blind holes formed by laser or mechanical drilling holes.

9. The preparation method according to claim 8, characterized in that, The plurality of layers includes: a top layer, an intermediate layer and a bottom layer, wherein the intermediate layer is located between the top layer and the bottom layer; The intermediate layer includes a power layer and a signal transmission layer. A ground layer is provided between two adjacent signal transmission layers, and a ground layer is provided between a signal transmission layer and its adjacent power layer. The power layer has a first power layer and a second power layer that are spaced apart. A dielectric layer is provided between the first power layer and the second power layer, and the first power layer is located above the second power layer. The top layer to the ground layer adjacent to and above the first power layer is symmetrical to the bottom layer to the ground layer adjacent to and below the second power layer. The ground layer adjacent to and above the first power layer, and the corresponding layer of the first power layer, are symmetrical with the ground layer adjacent to and below the second power layer. The first power layer to the dielectric layer adjacent to and below the first power layer are symmetrical with the second power layer to the dielectric layer adjacent to and above the second power layer.

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