Thermopile pixel array chip with integrated heat dissipation structure and driving circuit chip

Abstract

This invention provides a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure, comprising: a thermopile pixel array chip, specifically including: a first thermocouple and a second thermocouple; the first thermocouple and the second thermocouple are arranged opposite each other in a horizontal direction; a driving circuit chip, which is stacked sequentially with the first thermocouple and / or the second thermocouple in a vertical direction and electrically connected to the driving circuit chip; a first metal layer formed between the first thermocouple, the second thermocouple and the driving circuit chip; and a first heat dissipation structure forming an interconnect structure, disposed in the gap between adjacent first metal layers and isolated from each other. This technical solution solves the problem of temperature imbalance in different areas of the driving circuit chip while reducing the size of the integrated circuit of the thermopile pixel array chip and the driving circuit chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure. Background Technology

[0002] The current mainstream technology for thermopile arrays achieves thermal isolation between the thermocouple and the supporting silicon through bottom silicon etching. Specifically, the silicon beneath the thermocouple is etched away using dry or wet methods, leaving the thermocouple suspended for insulation. In this configuration, individual thermopile pixels are placed side-by-side with the IORC (In-Circuit Readout Circuit), meaning the ROIC circuit is not located beneath individual thermopile pixels; instead, only pure silicon lies beneath the thermopile pixels, resulting in a large chip area. Furthermore, because different modules within the ROIC circuit operate in different modes, the local temperature of the readout circuit chip varies. The temperature on the ROIC chip determines the temperature of the cold end of the thermopile pixel; in conventional designs, the cold end temperature of pixels is read uniformly. Therefore, temperature imbalances within the readout circuit chip lead to uneven cold end temperatures of pixels, resulting in deviations in the local thermopile pixel signals. This causes some pixel signals to "shift," leading to incorrect temperature information read and simultaneously affecting image quality.

[0003] Therefore, developing a novel integrated structure of small-sized thermopile array and readout circuit, which can quickly eliminate the temperature difference of ROIC under the pixel and make the cold end temperature of all pixels consistent, thereby eliminating the pixel signal reading deviation caused by the cold end temperature error of some pixel signals, has become a key technical focus that needs to be addressed by those skilled in the art. Summary of the Invention

[0004] This invention provides a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure, in order to solve the problem of temperature imbalance in different areas of the driving circuit chip (pixel cold end) while reducing the size of the integrated circuit of the thermopile pixel array chip and the driving circuit chip.

[0005] According to a first aspect of the present invention, a thermopile pixel array chip with an integrated heat dissipation structure and a driving circuit chip are provided, comprising:

[0006] A thermopile pixel array chip includes: a first thermocouple and a second thermocouple; the first thermocouple and the second thermocouple are arranged opposite each other in a horizontal direction;

[0007] A driving circuit chip, wherein the driving circuit chip and the first thermocouple and / or the second thermocouple are stacked sequentially in a vertical direction, and the thermopile pixel array chip is electrically connected to the driving circuit chip;

[0008] A first metal layer is formed between the first thermocouple and the second thermocouple and the driving circuit chip, for electrically connecting the thermopile pixel array chip and the driving circuit chip;

[0009] A first heat dissipation structure is formed in the gap between adjacent first metal layers; wherein the first heat dissipation structure is isolated from the first metal layers; the first heat dissipation structure forms an interconnect structure for dissipating heat from the drive circuit chip.

[0010] Optionally, the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure further include:

[0011] An insulating dielectric layer is formed between the first heat dissipation structure and the first metal layer to isolate the first heat dissipation structure from the first metal layer.

[0012] Optionally, the interconnect structure formed by the first heat dissipation structure includes a network-like interconnect structure.

[0013] Optionally, the thermopile pixel array chip with integrated heat dissipation structure and the driving circuit chip also include:

[0014] The second heat dissipation structure is formed on top of the first heat dissipation structure and the first metal layer.

[0015] Optionally, the first heat dissipation structure and / or the second heat dissipation structure may include a metal plate.

[0016] Optionally, the materials of the first heat dissipation structure and / or the second heat dissipation structure include copper or aluminum.

[0017] Optionally, the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure further include:

[0018] A plurality of first interconnect structures are formed on a first side of the driving circuit chip; the first side of the driving circuit chip represents the side of the driving circuit chip that is close to the first thermocouple or the second thermocouple.

[0019] A plurality of second interconnect structures are formed on a first side of the thermopile pixel array chip; the first side of the thermopile pixel array chip represents the side of the thermopile pixel array chip closest to the driving circuit chip; wherein, the second interconnect structure includes the first metal layer;

[0020] The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip is electrically connected to the driving circuit chip.

[0021] Optionally, the thermopile pixel array chip further includes:

[0022] A first support post is formed between the first thermocouple and the corresponding second interconnection structure to connect the first thermocouple and the corresponding second interconnection structure;

[0023] A second support post is formed between the second thermocouple and the corresponding second interconnection structure to connect the second thermocouple and the corresponding second interconnection structure;

[0024] The first metal layer is connected to the corresponding first thermocouple or the second thermocouple via the corresponding first support column or the second support column.

[0025] Optionally, the driving circuit chip further includes: a second metal layer and a third metal layer, formed on both sides away from the plurality of first interconnect structures in the horizontal direction;

[0026] The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure also include: a number of PAD holes, which are respectively formed on the top of the corresponding second metal layer and the third metal layer.

[0027] Optionally, both the first thermocouple and the second thermocouple include a heat-absorbing region;

[0028] The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure further include: a plurality of heat collection components; the plurality of heat collection components are respectively formed on the top of the corresponding first thermocouple and the second thermocouple, and the area of ​​the top of the plurality of heat collection components is larger than the area of ​​the corresponding heat absorption region; wherein, the plurality of heat collection components are used to absorb heat.

[0029] Optionally, several heat collection components specifically include:

[0030] First etch stop layer,

[0031] A heat collection layer is formed on the surface of the first etched stop layer;

[0032] The third support pillar is formed between the corresponding first etched stop layer and the corresponding first thermocouple or second thermocouple; wherein the area of ​​the heat collection layer is larger than the area of ​​the corresponding heat absorption region.

[0033] Optionally, the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure further include:

[0034] The first metal plug is formed between the corresponding first metal layer or the first heat dissipation structure and the second heat dissipation structure.

[0035] According to a second aspect of the present invention, a method for fabricating a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure is provided, for fabricating the thermopile pixel array chip and the driving circuit chip with an integrated heat dissipation structure as described in any one of the first aspects of the present invention, comprising:

[0036] Form the driving circuit chip;

[0037] The process comprises a thermopile pixel array chip, a sacrificial layer, a first substrate, a first heat dissipation structure, and a first metal layer. The thermopile pixel array chip includes a first thermocouple and a second thermocouple. The first and second thermocouples are formed above the first substrate and are positioned opposite each other in a horizontal direction. The sacrificial layer fills the gap between the first substrate and the thermopile pixel array chip. The first metal layer is formed on the surface of the sacrificial layer and connects to the corresponding first or second thermocouple. The first heat dissipation structure is formed in the gap between adjacent first metal layers. The first heat dissipation structure is isolated from the first metal layer. The first heat dissipation structure forms an interconnect structure for dissipating heat from the driving circuit chip.

[0038] The first side of the driving circuit chip is bonded to the first side of the thermopile pixel array chip structure;

[0039] Remove the first substrate;

[0040] Remove the sacrificial layer.

[0041] Optionally, after removing the first substrate, the method further includes:

[0042] A patterned sacrificial layer is formed; the patterned sacrificial layer encapsulates the first thermocouple and fills the gap between the first thermocouple, the second thermocouple and the first substrate;

[0043] The plurality of PAD holes are formed, and the plurality of PAD holes are respectively formed at the top of the corresponding second metal layer and the third metal layer.

[0044] Optionally, after forming the plurality of PAD holes, the method further includes: releasing the patterned sacrificial layer to remove the sacrificial layer.

[0045] Optionally, when forming the thermopile pixel array chip, sacrificial layer, first substrate, first heat dissipation structure and first metal layer, the method further includes: forming the second heat dissipation structure and the second interconnection structure.

[0046] Optionally, forming the thermopile pixel array chip, sacrificial layer, first substrate, first heat dissipation structure, and first metal layer specifically includes:

[0047] Provide a first substrate;

[0048] The first thermocouple, the second thermocouple, the first support column, and the second support column are formed.

[0049] The first thermocouple and the second thermocouple are formed above the first substrate and are arranged in a horizontal direction; the first support post is formed on the surface of the first thermocouple and the second support post is formed on the surface of the second thermocouple; wherein, the sacrificial layer fills the space between the surfaces of the first support post and the second support post and the surface of the first substrate.

[0050] The second interconnect structure and the first heat dissipation structure are formed; the second interconnect structure is formed on the surface of the sacrificial layer and contacts the corresponding first support post or the second support post; so that the first metal layer is connected to the corresponding first thermocouple or the second thermocouple through the corresponding first support post or the second support post; wherein, the first metal layer is connected to the corresponding first thermocouple or the second thermocouple through the corresponding first support post or the second support post.

[0051] Optionally, before forming the first thermocouple, the second thermocouple, the first support post, and the second support post, the method further includes:

[0052] The first etch stop layer and the third support pillar are formed; the first etch stop layer is formed on the surface of the first substrate and is arranged in a horizontal direction; the third support pillar is formed at the top of the corresponding first etch stop layer and is connected to the corresponding first thermocouple or second thermocouple.

[0053] Optionally, after forming the first thermocouple, the second thermocouple, the first support post, and the second support post, the method further includes:

[0054] The release barrier layer is formed at the top of the first support column, the second support column, and the sacrificial layer.

[0055] Optionally, when forming the second interconnect structure and the first heat dissipation structure, the method further includes:

[0056] The insulating dielectric layer is formed on the surface of the release barrier layer, covers the first metal layer, and fills the gaps between the second interconnect structures, between the first heat dissipation structures, and between the second interconnect structures and the first heat dissipation structure.

[0057] Optionally, when forming the second interconnect structure and the first heat dissipation structure, the method further includes: forming the second heat dissipation structure and the first metal plug; the first metal plug connects the second heat dissipation structure to the corresponding first metal layer or the first heat dissipation structure.

[0058] Optionally, forming the second heat dissipation structure and the first metal plug specifically includes:

[0059] The first metal plug is formed at the top of the corresponding first metal layer and the first heat dissipation structure.

[0060] The second heat dissipation structure is formed at the top of the corresponding first metal plug.

[0061] Optionally, before releasing the graphical sacrifice layer, the following is also included:

[0062] The heat collection layer is formed at the top of the first etched stop layer.

[0063] Optionally, the process of forming the driving circuit chip further includes forming the first interconnect structure.

[0064] According to a third aspect of the present invention, a sensor is provided, comprising a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure as described in any of the first aspects of the present invention.

[0065] According to a fourth aspect of the present invention, a method for manufacturing a sensor is provided, comprising a method for manufacturing a thermopile pixel array chip with an integrated heat dissipation structure and a driving circuit chip as described in any of the second aspects of the present invention.

[0066] This invention provides a thermopile pixel array chip and driving circuit chip with an integrated heat dissipation structure. By stacking the driving circuit chip and a first thermocouple and / or a second thermocouple vertically, and electrically connecting the thermopile pixel array chip to the driving circuit chip, a vertically stacked thermopile pixel array chip and driving circuit chip structure is formed, reducing the device size. Furthermore, a first heat dissipation structure is provided in the gap between adjacent first metal layers, wherein the first heat dissipation structure is isolated from the first metal layers and forms an interconnect structure. Because the first heat dissipation structure can disperse the temperature in different areas of the driving circuit chip, the temperature distribution in the driving circuit chip is uniform. Therefore, the technical solution provided by this invention solves the problem of uneven cold-end temperature of pixels caused by temperature imbalance in vertically stacked thermopile pixel array chips and driving circuit chips, eliminates the deviation of local thermopile pixel signals and the "offset" of some pixel signals, making the read temperature information more accurate and greatly improving the imaging quality of the thermopile pixel array chip and driving circuit chip. In addition, the design proposed in this invention is fully compatible with CMOS technology and is suitable for mass production. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 This is a schematic flowchart illustrating a method for fabricating a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure, according to an embodiment of the present invention.

[0069] Figure 2 This is a schematic diagram of the structure of a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure provided in a specific embodiment of the present invention;

[0070] Figure 3 This is a schematic diagram of the structure of a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure provided in another specific embodiment of the present invention;

[0071] Figure 4 This is a schematic diagram of the packaged structure of a thermopile pixel array chip with an integrated heat dissipation structure and a driving circuit chip, according to another specific embodiment of the present invention.

[0072] Figure 5-10 and Figure 12-17This is a schematic diagram of the device structure at different process stages of the thermopile pixel array chip and the driving circuit chip with the packaged integrated heat dissipation structure provided in another specific embodiment of the present invention.

[0073] Figure 11 This is a schematic diagram of the structure of a driving circuit chip provided in an embodiment of the present invention;

[0074] Figure 18 This is a schematic diagram of the encapsulation cover structure provided in an embodiment of the present invention;

[0075] Explanation of reference numerals in the attached figures:

[0076] 101 - First substrate;

[0077] 102 - First thermocouple;

[0078] 103 - Second thermocouple;

[0079] 104 - Sacrificial Layer;

[0080] 105 - Release the blocking layer;

[0081] 106 - First Support Column;

[0082] 107 - Second support column;

[0083] 108 - First metal layer;

[0084] 109 - Graphical insulating layer;

[0085] 110 - First metal interconnect layer;

[0086] 111 - Second metal plug;

[0087] 112 - Insulating dielectric layer;

[0088] 113 - Second substrate;

[0089] 114-CMOS device;

[0090] 115 - Third metal plug;

[0091] 116 - Fourth metal layer;

[0092] 117 - Second metal layer;

[0093] 118 - Third metal layer;

[0094] 119 - Fourth metal plug;

[0095] 120 - Second metal interconnect layer;

[0096] 121-Thermopile Pixel Array Chip;

[0097] 122 - Driver circuit chip;

[0098] 123 - Graphical sacrificial layer;

[0099] 124-getter structure;

[0100] 125 - First closed-loop bonded ring;

[0101] 126 - Capped wafer;

[0102] 127 - Second closed-loop bonding ring;

[0103] 128- Package cap structure;

[0104] 129 - First thermal film layer;

[0105] 130 - Heat collection component;

[0106] 1301 - Heat Collector Layer;

[0107] 1302 - Third Support Column;

[0108] 1303 - First etching stop layer;

[0109] 131 - First heat dissipation structure. Detailed Implementation

[0110] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0111] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0112] The current mainstream technology for thermopile arrays achieves thermal isolation between the thermocouple and the supporting silicon through bottom silicon etching. Specifically, the silicon beneath the thermocouple is etched away using dry or wet methods, leaving the bottom of the thermocouple suspended to achieve insulation. In this configuration, individual thermopile pixels are placed side-by-side with the IORC (Input / Output Circuit), meaning the IORC circuit is not located beneath any individual pixel in the thermopile; the area beneath the thermopile pixel is simply silicon. This results in a very large chip area.

[0113] Furthermore, because the different operating modes of the local modules in the ROIC circuit result in varying local temperatures of the readout circuit chip, the temperature on the ROIC chip determines the temperature of the cold end of the thermopile pixel. In conventional designs, the cold end temperature of the pixels is read uniformly. Therefore, temperature imbalances within the readout circuit chip lead to uneven cold end temperatures of the pixels, resulting in deviations in the local thermopile pixel signals. This causes some pixel signals to "shift," leading to the reading of incorrect temperature information and simultaneously affecting image quality.

[0114] As can be seen, in existing technologies, due to limitations in process and structure, the silicon substrate left by bottom silicon etching technology occupies a large area. This area is considered "ineffective" for a single thermopile pixel, severely limiting the miniaturization of thermopile array pixels. Simultaneously, because the ROIC is placed side-by-side with the thermopile pixel and cannot be located under the thermopile pixel, this also severely limits the miniaturization of the thermopile array chip. More importantly, temperature differences in the ROIC circuit under the pixel lead to inconsistent cold-end temperatures of the pixel, resulting in local thermopile pixel signal deviations. This causes some pixel signals to "shift," leading to the reading of incorrect temperature information and simultaneously affecting image quality.

[0115] In view of this, the inventors of this application propose that the thermopile pixel array and the readout ROIC circuit be designed and fabricated separately. Then, each thermopile pixel is bonded in situ to its corresponding readout circuit interface, forming a vertically stacked structure between the thermopile pixel array and the readout ROIC circuit. This effectively utilizes the space occupied by the suspended silicon at the bottom of the thermopile pixel array, maximizing the effective area of ​​the thermopile pixels and reducing their size. Simultaneously, the readout circuit is moved below the thermopile pixel array, further reducing the chip size.

[0116] Furthermore, the inventors of this application introduce a heat dissipation structure to rapidly eliminate temperature differences in the ROIC circuit under the pixel, thereby ensuring a uniform cold-end temperature for all pixels and eliminating pixel signal reading deviations caused by cold-end temperature errors in some pixels. In addition, the design proposed in this invention is fully compatible with CMOS processes and is suitable for mass production.

[0117] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0118] Please refer to Figures 1-18 According to an embodiment of the present invention, a thermopile pixel array chip with an integrated heat dissipation structure and a driving circuit chip are provided, comprising:

[0119] The thermopile pixel array chip 121 includes: a first thermocouple 102 and a second thermocouple 103; the first thermocouple 102 and the second thermocouple 103 are arranged opposite each other in a horizontal direction;

[0120] In one embodiment, the number of the second thermocouples 103 is several; the number of the second thermocouples 103 is not limited, and any implementation of the number of the second thermocouples 103 that can achieve the purpose of the present invention is within the protection scope of the present invention, and the present invention is not limited thereto.

[0121] The accompanying drawings of this application only schematically show the basic units in the thermocouple array chip and the driving circuit chip. In fact, the thermocouple array chip or the driving circuit chip is composed of several basic units shown in the drawings.

[0122] The driving circuit chip 122 is stacked vertically with the first thermocouple 102 and / or the second thermocouple 103, and the thermopile pixel array chip 121 is electrically connected to the driving circuit chip 122.

[0123] A first metal layer is formed between the first thermocouple 102 and the second thermocouple 103 and the driving circuit chip 122, for electrically connecting the thermopile pixel array chip 121 and the driving circuit chip 122.

[0124] A first heat dissipation structure 131 is formed in the gap between adjacent first metal layers; wherein the first heat dissipation structure 131 is isolated from the first metal layers; the first heat dissipation structure 131 forms an interconnect structure for dissipating heat from the driving circuit chip 122. In one specific embodiment, the structure of the thermopile pixel array chip with integrated heat dissipation structure and the driving circuit chip is as follows: Figure 2 As shown.

[0125] This invention provides a thermopile pixel array chip and driving circuit chip with an integrated heat dissipation structure. By stacking the driving circuit chip and a first thermocouple and / or a second thermocouple vertically, and electrically connecting the thermopile pixel array chip to the driving circuit chip, a vertically stacked thermopile pixel array chip and driving circuit chip structure is formed, reducing device size. Furthermore, by setting a first heat dissipation structure in the gap between adjacent first metal layers, wherein the first heat dissipation structure is isolated from the first metal layers and forms an interconnect structure to dissipate heat from the driving circuit chip, the temperature distribution in different areas of the driving circuit chip becomes uniform. This solves the problem of uneven temperature at the cold end of pixels caused by temperature imbalance in the driving circuit chip, eliminates local thermopile pixel signal deviation and partial pixel signal "offset," resulting in more accurate temperature information and significantly improving the imaging quality of the thermopile pixel array chip and driving circuit chip. In addition, the design proposed in this invention is fully compatible with CMOS technology and is suitable for mass production.

[0126] In one embodiment, the interconnect structure formed by the first heat dissipation structure 131 includes a network-like interconnect structure.

[0127] To achieve better heat dissipation, in a preferred embodiment, the thermopile pixel array chip with integrated heat dissipation structure and the driving circuit chip further include:

[0128] A second heat dissipation structure (not shown in the figure) is formed on top of the first heat dissipation structure 131 and the first metal layer 108.

[0129] In one embodiment, the first heat dissipation structure 131 and / or the second heat dissipation structure include a metal plate. Specifically, the material of the first heat dissipation structure 131 and / or the second heat dissipation structure includes copper or aluminum.

[0130] In one embodiment, the thermopile pixel array chip and the driving circuit chip with integrated heat dissipation structure further include:

[0131] The first metal plug is formed between the corresponding first metal layer 108 or the first heat dissipation structure 131 and the second heat dissipation structure to connect the first metal layer 108 and the second heat dissipation structure, or to connect the first heat dissipation structure 131 and the second heat dissipation structure.

[0132] In one embodiment, the thermopile pixel array chip and the driving circuit chip with integrated heat dissipation structure further include:

[0133] An insulating dielectric layer 112 is formed between the first heat dissipation structure 131 and the first metal layer 108 to isolate the first heat dissipation structure 131 from the first metal layer 108.

[0134] In one embodiment, the thermopile pixel array chip and the driving circuit chip with integrated heat dissipation structure further include:

[0135] A plurality of first interconnect structures are formed on a first side of the driving circuit chip 122; the first side of the driving circuit chip 122 represents the side of the driving circuit chip 122 that is close to the first thermocouple 102 or the second thermocouple 103.

[0136] A plurality of second interconnect structures are formed on a first side of the thermopile pixel array chip 121; the first side of the thermopile pixel array chip 121 represents the side of the thermopile pixel array chip 121 closest to the driving circuit chip 122; wherein, the second interconnect structure includes the first metal layer 108.

[0137] The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip 121 is electrically connected to the driving circuit chip 122.

[0138] In one embodiment, the thermopile pixel array chip 121 further includes:

[0139] A first support post 106 is formed between the first thermocouple 102 and the corresponding second interconnection structure to connect the first thermocouple 102 and the corresponding second interconnection structure.

[0140] A second support post 107 is formed between the second thermocouple 103 and the corresponding second interconnection structure to connect the second thermocouple 103 and the corresponding second interconnection structure.

[0141] The first metal layer 108 is connected to the corresponding first thermocouple 102 or the second thermocouple 103 via the corresponding first support column 106 or the second support column 107.

[0142] In one embodiment, the driving circuit chip 122 further includes a second metal layer 117 and a third metal layer 118, formed on both sides away from the plurality of first interconnect structures in the horizontal direction;

[0143] The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure also include: a plurality of PAD holes, which are respectively formed on the top of the corresponding second metal layer 117 and the third metal layer 118.

[0144] Both the first thermocouple 102 and the second thermocouple 103 include heat-absorbing regions. Since the heat-absorbing area of ​​the thermopile pixel array chip 121 and the driving circuit chip 122 is approximately 50% in the central part of the thermocouple, the low fill rate limits the device's performance. Therefore, to improve the fill rate and thus enhance the heat absorption capacity, in another specific embodiment, preferably, the thermopile pixel array chip and the driving circuit chip with integrated heat dissipation structure further include:

[0145] A plurality of heat-collecting components 130 are provided; the plurality of heat-collecting components 130 are respectively formed at the top ends of the corresponding first thermocouple 102 and second thermocouple 103, and the area of ​​the top end of the plurality of heat-collecting components 130 is larger than the area of ​​the corresponding heat-absorbing region; wherein, the plurality of heat-collecting components 130 are used to absorb heat, such as Figure 3 As shown.

[0146] The technical solution provided by this invention, by superimposing a heat-collecting component 130 on the top of the corresponding first thermocouple 102 and second thermocouple 103, can increase the fill rate to about 90% and the heat absorption area to about 90%, thus greatly improving the device performance.

[0147] In one embodiment, the plurality of heat collection components 130 specifically include:

[0148] First etch stop layer 1303

[0149] Heat collection layer 1301 is formed on the surface of the first etch stop layer 1303;

[0150] The third support post 1302 is formed between the corresponding first etched stop layer 1303 and the corresponding first thermocouple 102 or second thermocouple 103; wherein the area of ​​the heat collection layer 1301 is larger than the area of ​​the corresponding heat absorption region.

[0151] In another specific embodiment, the thermopile pixel array chip and the driving circuit chip with integrated heat dissipation structure further include:

[0152] A capping wafer 126 is provided, wherein the center of the capping wafer 126 includes a trench, the trench forming a capping window;

[0153] A plurality of getter structures 124 are sequentially distributed on the surfaces of the release barrier layer 105 on opposite sides of the first thermocouple 102 and the second thermocouple 103, as well as on the sidewalls, part of the surface, and part of the bottom of the capping window; wherein the plurality of getter structures 124 in the capping window and the plurality of getter structures 124 on the corresponding release barrier layer 105 are arranged opposite to each other along a first direction; the first direction characterizes the stacking direction of the second interconnection structure and the first interconnection structure.

[0154] A plurality of first closed-loop bonding rings 125 and a plurality of second closed-loop bonding rings; the plurality of first closed-loop bonding rings 125 are respectively formed on the surface of the release barrier layer 105 between the first thermocouple 102 and the second thermocouple 103 and the adjacent PAD opening; a plurality of second closed-loop bonding rings 127 are formed on the surface of the capping wafer 126 outside the capping window, and the second closed-loop bonding rings 127 are disposed opposite to the corresponding first closed-loop bonding rings 125, such as... Figure 4 As shown.

[0155] The encapsulated wafer 126, several getter structures 124 distributed on the sidewalls, part of the surface, and part of the bottom of the encapsulated window, and several second closed bonding rings form an encapsulation cap structure 128, such as... Figure 18 As shown.

[0156] In another specific embodiment, the second interconnect structure includes: a plurality of first metal layers 108, a plurality of second metal plugs 111, and a plurality of first metal interconnect layers 110; wherein, the plurality of first metal layers 108 are formed on the surface of the release barrier layer 105 facing away from the first thermocouple 102 or the second thermocouple 103; the plurality of first metal interconnect layers 110 are connected to corresponding third metal layers 118 through corresponding second metal plugs 111.

[0157] The first interconnect structure specifically includes: a plurality of fourth metal layers 116, a plurality of third metal plugs 115, a fourth metal plug 119, and a plurality of second metal interconnect layers 120; wherein,

[0158] The plurality of first metal layers 108 are formed on the surface of the release barrier layer 105 opposite to the first thermocouple 102 or the second thermocouple 103; the plurality of second metal interconnect layers 120 are connected to the corresponding fourth metal layer 116 through the corresponding third metal plug 115.

[0159] The driving circuit chip 122 further includes: a second substrate 113 and a plurality of CMOS devices 114; the plurality of CMOS devices 114 are formed on the second substrate 113; wherein, a third metal plug 115, a fourth metal layer 116, a fourth metal plug 119 and a second metal interconnect layer 120 are stacked sequentially in a direction away from the CMOS devices 114;

[0160] The second metal interconnect layer 120 is connected to the first metal interconnect layer 110 in the second interconnect structure.

[0161] The thermopile pixel array chip with integrated heat dissipation components and other components of the driving circuit chip are all existing publicly disclosed technologies in the field, and will not be described in detail here.

[0162] Secondly, according to an embodiment of the present invention, a method for fabricating a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure is also provided, for fabricating the thermopile pixel array chip and the driving circuit chip with an integrated heat dissipation structure as described in any of the foregoing embodiments of the present invention, comprising:

[0163] S11: Form the driving circuit chip 122, such as Figure 11 As shown;

[0164] S12: Forming the thermopile pixel array chip 121, sacrificial layer 104, first substrate 101, first heat dissipation structure 131, and first metal layer 108; wherein, the thermopile pixel array chip 121 includes: a first thermocouple 102 and a second thermocouple 103; the first thermocouple 102 and the second thermocouple 103 are formed above the first substrate 101, and the first thermocouple 102 and the second thermocouple 103 are arranged opposite each other in the horizontal direction; the sacrificial layer 104 fills the first substrate. The first metal layer 108 is formed on the surface of the sacrificial layer 104 and is respectively connected to the corresponding first thermocouple 102 or second thermocouple 103; the first heat dissipation structure 131 is formed in the gap between adjacent first metal layers 108; wherein, the first heat dissipation structure 131 and the first metal layer 108 are isolated from each other; the first heat dissipation structure 131 forms an interconnection structure for dissipating heat in the driving circuit chip 122, such as... Figure 10 As shown;

[0165] S13: Bond the first side of the driving circuit chip 122 to the first side of the thermopile pixel array chip 121 structure, such as Figure 11 As shown;

[0166] S14: Remove the first substrate 101; here, after removing the substrate, a heat-collecting layer 1301 can be formed on the surface of the release barrier layer 105; alternatively, the substrate can be thinned, and then a heat-collecting layer region can be defined to form a first heat-collecting film layer 129, which can then be patterned to form a heat-collecting layer 1301 with a nanoforest structure, such as... Figure 13 As shown;

[0167] S15: Remove the sacrificial layer 104, as follows Figure 2 As shown.

[0168] After forming the first metal layer 108 and the first heat dissipation structure 131, the method further includes: forming a patterned insulating layer 109, such as... Figure 9 As shown;

[0169] In one embodiment, step S11, which involves forming the driving circuit chip 122, further includes forming the second metal layer 117 and the third metal layer 118.

[0170] In one embodiment, forming the driving circuit chip 122 further includes forming the first interconnect structure. The specific process for forming the driving circuit chip 122 is prior art and will not be described in detail here.

[0171] In one embodiment, after removing the first substrate 101 in step S14, the method further includes:

[0172] A patterned sacrificial layer 123 is formed; the patterned sacrificial layer 123 encloses the first thermocouple 102 and fills the gap between the first thermocouple 102, the second thermocouple 103, and the first substrate 101, such as... Figure 14 As shown;

[0173] The plurality of PAD holes are formed, and the plurality of PAD holes are respectively formed at the top ends of the corresponding second metal layer 117 and the third metal layer 118, such as... Figure 15 As shown.

[0174] In one embodiment, after forming the plurality of PAD holes, the method further includes: releasing the patterned sacrificial layer 123 to remove the sacrificial layer 104.

[0175] In one embodiment, step S12, which involves forming the thermopile pixel array chip 121, the sacrificial layer 104, the first substrate 101, the first heat dissipation structure 131, and the first metal layer 108, further includes forming the second heat dissipation structure and the second interconnection structure.

[0176] In one embodiment, the formation of the thermopile pixel array chip 121, the sacrificial layer 104, the first substrate 101, the first heat dissipation structure 131, and the first metal layer 108 specifically includes:

[0177] S121: Provide a first substrate 101;

[0178] S122: Forming the first thermocouple 102, the second thermocouple 103, the first support pillar 106, and the second support pillar 107; the first thermocouple 102 and the second thermocouple 103 are formed above the first substrate 101 and arranged in a horizontal direction; the first support pillar 106 is formed on the surface of the first thermocouple 102, and the second support pillar 107 is formed on the surface of the second thermocouple 103; wherein, the sacrificial layer 104 fills the space between the surfaces of the first support pillar 106 and the second support pillar 107 and the surface of the first substrate 101. Please refer to [reference needed]. Figure 8 ;

[0179] S123: Form the second interconnect structure and the first heat dissipation structure 131; the second interconnect structure is formed on the surface of the sacrificial layer 104 and contacts the corresponding first support post 106 or the second support post 107; so that the first metal layer 108 is connected to the corresponding first thermocouple 102 or the second thermocouple 103 through the corresponding first support post 106 or the second support post 107; wherein, the first metal layer 108 is connected to the corresponding first thermocouple 102 or the second thermocouple 103 through the corresponding first support post 106 or the second support post 107.

[0180] In one embodiment, before step S122, which involves forming the first thermocouple 102, the second thermocouple 103, the first support post 106, and the second support post 107, the method further includes:

[0181] The first etching stop layer 1303 and the third support pillar 1302 are formed; the first etching stop layer 1303 is formed on the surface of the first substrate 101 and is arranged in a horizontal direction, such as... Figure 5 As shown; the third support post 1302 is formed at the top of the corresponding first etched stop layer 1303 and is connected to the corresponding first thermocouple 102 or second thermocouple 103, as shown. Figure 6 As shown and Figure 7 As shown.

[0182] In one embodiment, after forming the first thermocouple 102, the second thermocouple 103, the first support post 106, and the second support post 107 in step S122, the method further includes:

[0183] The release barrier layer 105 is formed; the release barrier layer 105 is formed at the top of the first support post 106, the second support post 107, and the sacrificial layer 104, please refer to... Figure 8 .

[0184] The first heat dissipation structure 131 is formed on the surface of the release barrier layer 105, such as... Figure 8 As shown.

[0185] In one embodiment, step S123, when forming the second interconnect structure and the first heat dissipation structure 131, further includes:

[0186] The insulating dielectric layer 112 is formed on the surface of the release barrier layer 105, covers the first metal layer 108, and fills the gaps between the second interconnect structures, between the first heat dissipation structures 131, and between the second interconnect structures and the first heat dissipation structure 131, such as... Figure 10 As shown.

[0187] To further improve the heat dissipation effect, in a preferred embodiment, step S123, when forming the second interconnect structure and the first heat dissipation structure 131, further includes: forming the second heat dissipation structure and the first metal plug; the first metal plug connects the second heat dissipation structure to the corresponding first metal layer 108 or the first heat dissipation structure 131.

[0188] In one embodiment, forming the second heat dissipation structure and the first metal plug specifically includes:

[0189] The first metal plug is formed at the top of the corresponding first metal layer 108 and the first heat dissipation structure 131;

[0190] The second heat dissipation structure is formed at the top of the corresponding first metal plug.

[0191] The second heat dissipation structure can be a single metal layer or multiple metal layers; the number of first metal plugs can be one or more; and the multiple metal layers can also be connected by the first metal plugs.

[0192] When the second heat dissipation structure is a single metal layer, the thermopile pixel array chip and the driver circuit chip of the integrated heat dissipation component contain two metal layers to achieve heat dissipation function.

[0193] When the second heat dissipation structure is a multi-layer metal layer, the thermopile pixel array chip and the driving circuit chip of the integrated heat dissipation component contain two or more metal layers, thereby achieving a better heat dissipation effect.

[0194] In one embodiment, before releasing the graphical sacrifice layer 123, the method further includes:

[0195] The heat collection layer 1301 is formed on top of the first etch stop layer 1303. Please refer to [reference needed]. Figure 17 .

[0196] A plurality of getter structures 124 and a plurality of first closed-loop bonded rings 125 (e.g., distributed on the surfaces of the release barrier layer 105 on opposite sides of the first thermocouple 102 and the second thermocouple 103) Figure 16 (As shown); the methods for fabricating the plurality of fourth metal layers 116, plurality of second metal plugs 111, plurality of third metal plugs 115 and plurality of second metal interconnect layers 120 in the first interconnect structure; the plurality of CMOS devices 114; and the other components of the thermopile pixel array chip and the driving circuit chip with integrated heat collection components are all existing publicly disclosed technologies in the art, and will not be described in detail here.

[0197] Furthermore, according to an embodiment of the present invention, a sensor is also provided, comprising a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure as described in any of the foregoing embodiments of the present invention.

[0198] According to other embodiments of the present invention, a method for manufacturing a sensor is also provided, including a method for manufacturing a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure as described in any of the foregoing embodiments of the present invention.

[0199] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure, characterized in that, include: A thermopile pixel array chip includes: a first thermocouple and a second thermocouple; the first thermocouple and the second thermocouple are arranged opposite each other in a horizontal direction; A driving circuit chip, wherein the driving circuit chip and the first thermocouple and / or the second thermocouple are stacked sequentially in a vertical direction, and the thermopile pixel array chip is electrically connected to the driving circuit chip; A first metal layer is formed between the first thermocouple and the second thermocouple and the driving circuit chip, for electrically connecting the thermopile pixel array chip and the driving circuit chip; A first heat dissipation structure is formed in the gap between adjacent first metal layers; wherein the first heat dissipation structure is isolated from the first metal layers; the first heat dissipation structure forms an interconnect structure for dissipating heat from the drive circuit chip.

2. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 1, characterized in that, The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure also include: An insulating dielectric layer is formed between the first heat dissipation structure and the first metal layer to isolate the first heat dissipation structure from the first metal layer.

3. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 2, characterized in that, The interconnect structure formed by the first heat dissipation structure includes a network-like interconnect structure.

4. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 3, characterized in that, The thermopile pixel array chip with integrated heat dissipation structure and the driving circuit chip also include: The second heat dissipation structure is formed on top of the first heat dissipation structure and the first metal layer.

5. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 4, characterized in that, The first heat dissipation structure and / or the second heat dissipation structure include a metal plate.

6. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 5, characterized in that, The materials of the first heat dissipation structure and / or the second heat dissipation structure include copper or aluminum.

7. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 6, characterized in that, The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure also include: A plurality of first interconnect structures are formed on a first side of the driving circuit chip; the first side of the driving circuit chip represents the side of the driving circuit chip that is close to the first thermocouple or the second thermocouple. A plurality of second interconnect structures are formed on a first side of the thermopile pixel array chip; the first side of the thermopile pixel array chip represents the side of the thermopile pixel array chip closest to the driving circuit chip; wherein, the second interconnect structure includes the first metal layer; The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip is electrically connected to the driving circuit chip.

8. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 7, characterized in that, The thermopile pixel array chip also includes: A first support post is formed between the first thermocouple and the corresponding second interconnection structure to connect the first thermocouple and the corresponding second interconnection structure; A second support post is formed between the second thermocouple and the corresponding second interconnection structure to connect the second thermocouple and the corresponding second interconnection structure; The first metal layer is connected to the corresponding first thermocouple or the second thermocouple via the corresponding first support column or the second support column.

9. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 8, characterized in that, The driving circuit chip further includes: a second metal layer and a third metal layer, formed on both sides away from the plurality of first interconnect structures in the horizontal direction; The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure also include: a number of PAD holes, which are respectively formed on the top of the corresponding second metal layer and the third metal layer.

10. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 9, characterized in that, Both the first thermocouple and the second thermocouple include a heat-absorbing region; The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure further include: a plurality of heat collection components; the plurality of heat collection components are respectively formed on the top of the corresponding first thermocouple and the second thermocouple, and the area of ​​the top of the plurality of heat collection components is larger than the area of ​​the corresponding heat absorption region; wherein, the plurality of heat collection components are used to absorb heat.

11. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 10, characterized in that, Several heat collection components specifically include: First etch stop layer, A heat collection layer is formed on the surface of the first etched stop layer; The third support pillar is formed between the corresponding first etched stop layer and the corresponding first thermocouple or second thermocouple; wherein the area of ​​the heat collection layer is larger than the area of ​​the corresponding heat absorption region.

12. The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 11, characterized in that, The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure also include: The first metal plug is formed between the corresponding first metal layer or the first heat dissipation structure and the second heat dissipation structure.

13. A method for fabricating a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure, used to fabricate the thermopile pixel array chip and driving circuit chip with the integrated heat dissipation structure as described in any one of claims 1-12, characterized in that, include: Form the driving circuit chip; The process comprises a thermopile pixel array chip, a sacrificial layer, a first substrate, a first heat dissipation structure, and a first metal layer. The thermopile pixel array chip includes a first thermocouple and a second thermocouple. The first and second thermocouples are formed above the first substrate and are positioned opposite each other in a horizontal direction. The sacrificial layer fills the gap between the first substrate and the thermopile pixel array chip. The first metal layer is formed on the surface of the sacrificial layer and connects to the corresponding first or second thermocouple. The first heat dissipation structure is formed in the gap between adjacent first metal layers. The first heat dissipation structure is isolated from the first metal layer. The first heat dissipation structure forms an interconnect structure for dissipating heat from the driving circuit chip. The first side of the driving circuit chip is bonded to the first side of the thermopile pixel array chip structure; Remove the first substrate; Remove the sacrificial layer.

14. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 13, characterized in that, The process of forming the driving circuit chip also includes: A plurality of first interconnect structures are formed on a first side of the driving circuit chip; the first side of the driving circuit chip represents the side of the driving circuit chip that is close to the first thermocouple or the second thermocouple. A second metal layer and a third metal layer are formed on both sides of the plurality of first interconnect structures in a horizontal direction away from each other.

15. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 14, characterized in that, After removing the first substrate, the process further includes: A patterned sacrificial layer is formed; the patterned sacrificial layer encapsulates the first thermocouple and fills the gap between the first thermocouple, the second thermocouple and the first substrate; A plurality of PAD holes are formed, wherein the plurality of PAD holes are respectively formed at the top of the corresponding second metal layer and the third metal layer.

16. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 15, characterized in that, After forming the plurality of PAD holes, the method further includes: releasing the patterned sacrificial layer to remove the sacrificial layer.

17. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 16, characterized in that, When forming the thermopile pixel array chip, sacrificial layer, first substrate, first heat dissipation structure and first metal layer, the method further includes: forming a second heat dissipation structure and a plurality of second interconnect structures, wherein the second heat dissipation structure is formed at the top of the first heat dissipation structure and the first metal layer, and the second interconnect structures are formed on the first side of the thermopile pixel array chip. The first side of the thermopile pixel array chip represents the side of the thermopile pixel array chip closest to the driving circuit chip, and the second interconnect structure includes the first metal layer. The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip is electrically connected to the driving circuit chip.

18. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 17, characterized in that, The formation of the thermopile pixel array chip, the sacrificial layer, the first substrate, the first heat dissipation structure, and the first metal layer specifically includes: Provide a first substrate; The first thermocouple, the second thermocouple, the first support column, and the second support column are formed. The first thermocouple and the second thermocouple are formed above the first substrate and are arranged in a horizontal direction; the first support post is formed on the surface of the first thermocouple and the second support post is formed on the surface of the second thermocouple; wherein, the sacrificial layer fills the space between the surfaces of the first support post and the second support post and the surface of the first substrate. The second interconnect structure and the first heat dissipation structure are formed; the second interconnect structure is formed on the surface of the sacrificial layer and contacts the corresponding first support post or the second support post; so that the first metal layer is connected to the corresponding first thermocouple or the second thermocouple through the corresponding first support post or the second support post; wherein, the first metal layer is connected to the corresponding first thermocouple or the second thermocouple through the corresponding first support post or the second support post.

19. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 18, characterized in that, Before forming the first thermocouple, the second thermocouple, the first support post, and the second support post, the method further includes: A first etch stop layer and a third support pillar are formed; the first etch stop layer is formed on the surface of the first substrate and is arranged in a horizontal direction; the third support pillar is formed at the top of the corresponding first etch stop layer and is connected to the corresponding first thermocouple or second thermocouple.

20. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 19, characterized in that, After forming the first thermocouple, the second thermocouple, the first support post, and the second support post, the method further includes: A release barrier layer is formed at the top of the first support column, the second support column, and the sacrificial layer.

21. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 20, characterized in that, When forming the second interconnect structure and the first heat dissipation structure, the method further includes: An insulating dielectric layer is formed on the surface of the release barrier layer, covering the first metal layer, and filling the gaps between a plurality of second interconnect structures, between the first heat dissipation structures, and between the second interconnect structures and the first heat dissipation structure.

22. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 21, characterized in that, When forming the second interconnect structure and the first heat dissipation structure, the method further includes: forming the second heat dissipation structure and the first metal plug; the first metal plug connects the second heat dissipation structure to the corresponding first metal layer or the first heat dissipation structure.

23. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 22, characterized in that, The formation of the second heat dissipation structure and the first metal plug specifically includes: The first metal plug is formed at the top of the corresponding first metal layer and the first heat dissipation structure. The second heat dissipation structure is formed at the top of the corresponding first metal plug.

24. The method for fabricating the thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure according to claim 23, characterized in that, Before releasing the graphical sacrifice layer, the following is also included: A heat collection layer is formed at the top of the first etched stop layer.

25. A sensor, characterized in that, The thermopile pixel array chip and driving circuit chip with integrated heat dissipation structure as described in any one of claims 1-12 are included.

26. A method for manufacturing a sensor, characterized in that, The method for fabricating a thermopile pixel array chip and a driving circuit chip with an integrated heat dissipation structure as described in any one of claims 13-24.

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