A gate-modulated SCR ESD protection device structure based on high-temperature SOI technology

Abstract

The present invention discloses a gate-modulated SCRESD protection device structure based on a high-temperature SOI process, belonging to the field of semiconductor integrated circuits, which includes a P well, a HVNMOS drift region, an N-type source / drain implantation region, a P-type source / drain implantation region, a side lead-out terminal of the PWELL implanted with P, a side lead-out terminal of the HVN implanted with N, a polysilicon gate, a device active region, and a contact hole. The present invention realizes the circuits of LNPN and LPNP transistors based on an ultra-thin silicon film SOI material. The N-type source / drain implantation region serves as the emitter of NPN, the P well simultaneously serves as the base of NPN and the collector of the PNP transistor, the HVNMOS drift region simultaneously serves as the collector of the NPN transistor and the base of the PNP transistor, the P-type source / drain implantation region serves as the emitter of the PNP transistor, and the polysilicon gate covers the P well and the HVNMOS drift region; a "king" - shaped lateral NPNP SCRESD protection device structure is designed on the layout; through TLP test evaluation, the current discharge capacity per unit area of this structure reaches more than 0.02 A / um, which is more than 3 times that of the GCDIODE protection structure of the same process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a gate modulation SCR ESD protection device structure based on high-temperature SOI process. Background Technology

[0002] At high temperatures, CMOS devices experience a sharp increase in PN junction leakage current and significant drift in threshold voltage and other electrical parameters. High-temperature SOI CMOS devices utilize ultra-thin silicon films, allowing the bottom of the PN junction to be isolated by a buried oxide layer, and the device periphery to be fully dielectrically isolated by SiO2. This significantly reduces the PN junction area and high-temperature leakage current, while effectively suppressing the drift of threshold voltage and other electrical parameters. However, for high-temperature SOI ESD protection devices, the low thermal conductivity of the buried oxide layer significantly impacts heat dissipation, resulting in ESD capabilities far inferior to thick silicon SOI and bulk silicon devices. Due to structural limitations, many structures suitable for ESD protection in bulk silicon technology, such as thick field oxide devices and vertical PN junctions, cannot be used in high-temperature SOI circuits. Therefore, ESD design for high-temperature SOI circuits is a significant and challenging problem. Summary of the Invention

[0003] The purpose of this invention is to provide a gate-modulated SCR ESD protection device structure based on high-temperature SOI technology to solve the problem of ESD protection of high-temperature SOI circuits mentioned in the background art.

[0004] To solve the above technical problems, the present invention provides a gate-modulated SCR ESD protection device structure based on high-temperature SOI process, including a P-well, an HVNMOS drift region, an N-type source-drain injection region, a P-type source-drain injection region, a P-type injected PWELL side lead-out terminal, an N-type injected HVN side lead-out terminal, a polysilicon gate, a device active region, and contact holes.

[0005] The polysilicon gate covers the P-well and the HVNMOS drift region, and serves as the gate control terminal to modulate the ESD protection performance of the SCR structure.

[0006] The active region of the device and the polygate enable precise dimensional control of the N-type source / drain injection region and the P-type source / drain injection region;

[0007] The PWELL side lead is located on the lead-out side of the P-well, and the N-type injected HVN side lead is located on the lead-out side of the HVNMOS drift region.

[0008] The contact holes are formed on the N-type source / drain injection region, the P-well, the HVNMOS drift region, and the P-type source / drain injection region.

[0009] In one embodiment, the P-well and the HVNMOS drift region are both strip-shaped, and the P-well, the side lead-out terminal of the PWELL, the HVNMOS drift region, and the side lead-out terminal of the HVN together form a cross shape.

[0010] In one embodiment, there are two N-type source / drain implantation regions, which are respectively located in front of and behind the lead-out side of the P-well; there are two P-type source / drain implantation regions, which are respectively located in front of and behind the lead-out side of the HVNMOS drift region; the N-type source / drain implantation regions, the P-well, the HVNMOS drift region, and the P-type source / drain implantation regions form a lateral NPNP structure.

[0011] In one embodiment, the side lead-out terminal of the PWELL is located in the middle of the lead-out side of the P-well, separating the two N-type source / drain implantation regions in front and behind; the side lead-out terminal of the HVN is located in the middle of the lead-out side of the HVNMOS drift region, separating the two P-type source / drain implantation regions in front and behind.

[0012] In one embodiment, 7 groups of contact holes are provided. Among them, there are 4 groups in total for the two N-type source / drain implantation regions and the two P-type source / drain implantation regions, with 25 in each group; there is 1 group each on the side lead-out terminal of the PWELL and the side lead-out terminal of the HVN, with 2 in each group; there is 1 group on the polycrystalline gate, with 2; a total of 106 contact holes.

[0013] In one embodiment, the flat side of the P-well is back-to-back with the flat side of the HVNMOS drift region, and the polycrystalline gate is covered thereon; the lateral length of the polycrystalline gate is 0.55 μm each, and the total length is 1.1 μm.

[0014] In one embodiment, the flat side of the P-well is back-to-back with the flat side of the HVNMOS drift region, and the polycrystalline gate is covered thereon; the lateral length of the P-well and the HVNMOS drift region is 0.55 μm each, and the total length of the polycrystalline gate is 1.3 μm.

[0015] In one embodiment, the side lead-out terminal of the PWELL is P-type implantation, and the side lead-out terminal of the HVN is N-type implantation.

[0016] In a grid-modulated SCR ESD protection device structure based on a high-temperature SOI process provided by the present invention, the circuits of LNPN transistors and LPNP transistors are realized based on an ultra-thin silicon film SOI material, and a "king" - shaped lateral NPNP SCR ESD protection device structure is designed and formed on the layout; through TLP test evaluation, the current discharge capacity per unit area of this structure reaches more than 0.02 A / μm, which is more than 3 times that of the GCDIODE protection structure of the same process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of a gate-modulated SCR ESD protection device based on high-temperature SOI technology provided by the present invention.

[0018] Figure 2 This is a cross-sectional view of the PN junction structure formed by the P-well, PWELL side lead, HVNMOS drift region, and HVN side lead.

[0019] Figure 3 This is a cross-sectional view of the SCR structure consisting of the N-type source / drain injection region, P-well, HVNMOS drift region, and P-type source / drain injection region.

[0020] Figure 4 This is an equivalent structure diagram of the SCR of the present invention;

[0021] Figure 5(a) shows the TLP test results of the novel SCR structure;

[0022] Figure 5(b) shows the TLP test results of the traditional GCDIODE structure. Detailed Implementation

[0023] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the gate modulation SCRESD protection device structure based on high-temperature SOI technology proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0024] This invention provides a gate-modulated SCR ESD protection device structure based on high-temperature SOI technology, such as... Figure 1 As shown, the structure includes a P-well 1 (PWELL), an HVNMOS drift region 2 (HVN), an N-type source / drain injection region 3 (SN), a P-type source / drain injection region 4 (SP), a P-type injected PWELL side lead 5, an N-type injected HVN side lead 6, a polygate 7 (GT), a device active region 8 (TO), and a contact hole 9. The polygate 7 covers the P-well 1 and the HVNMOS drift region 2 and serves as a gate control terminal to modulate the ESD protection performance of the SCR structure. In terms of manufacturing process, the device active region 8 and the polygate 7 enable precise dimensional control of the N-type source / drain injection region 3 and the P-type source / drain injection region 4.

[0025] The P-well 1 is elongated, with a PWELL side lead-out terminal 5 on its lead-out side. The flat side of the P-well 1 is back-to-back with the flat side of the HVNMOS drift region 2, and the lead-out side of the HVNMOS drift region 2 has an HVN side lead-out terminal 6. The P-well 1, the PWELL side lead-out terminal 5, the HVNMOS drift region 2, and the HVN side lead-out terminal 6 together form a cross shape, as shown in the cross-sectional view below. Figure 2 As shown.

[0026] There is an N-type source / drain injection region 3 on the front and back of the P-well 1 lead-out side; there is a P-type source / drain injection region 4 on the front and back of the HVNMOS drift region 2 lead-out side; the N-type source / drain injection region 3, the P-well 1, the HVNMOS drift region 2, and the P-type source / drain injection region 4 constitute a lateral NPNP structure, the cross-sectional view of which is shown below. Figure 3 As shown. The entire protection device structure is implanted with an active region 8; the surfaces of the P-well 1 and the HVNMOS drift region 2 are covered with a polysilicon gate 7; the N-type source / drain injection region 3, the P-well 1, the HVNMOS drift region 2 and the P-type source / drain injection region 4 are all provided with contact holes 9.

[0027] The PWELL side lead 5 is located in the middle of the P-well 1 lead-out side, separating the N-type source / drain injection regions 3 at the front and rear. The HVN side lead 6 is located in the middle of the HVNMOS drift region 2 lead-out side, separating the P-type source / drain injection regions 4 at the front and rear. The relatively small width of the PWELL side lead 5 and the HVN side lead 6 allows for a larger width between the N-type source / drain injection regions 3 and the P-type source / drain injection regions 4, resulting in lower on-resistance and lower lattice temperature when used as a discharge path. While maintaining the device width to enhance ESD discharge capability, the PWELL side lead 5 and the HVN side lead 6, located in the middle of the elongated lead-out side, allow for more uniform current flow through the device.

[0028] The contact holes 9 are provided in 7 groups, of which the N-type source / drain injection region 3 and the P-type source / drain injection region 4 are provided in 4 groups in front and behind, with 25 holes in each group; the PWELL side lead-out terminal 5 and the HVN side lead-out terminal 6 are provided in 1 group each, with 2 holes in each group; the polygate 7 is provided in 1 group, with 2 holes, for a total of 106 holes.

[0029] The P well 1 and the HVNMOS drift region 2 are juxtaposed, and a polysilicon gate 7 is covered thereon. The lateral lengths d1 of the P well 1 and the HVNMOS drift region 2 are each 0.55 μm, and the total length d2 of the polysilicon gate 7 is 1.3 μm. There are 2 N-type source / drain implantation regions 3 and 2 P-type source / drain implantation regions 4 respectively. The longitudinal widths d3 of these 4 regions are all 10 μm. The structure width of the gate-modulated SCR ESD protection device based on the high-temperature SOI process of the present invention is 20 μm, and the lateral lengths of the parts not covered by the polysilicon gate 7 are all 1.83 μm.

[0030] The equivalent structure of the SCR of the present invention is as Figure 4 shown. Based on the high-temperature SOI standard process, ultra-thin silicon film SOI materials are used to design lateral NPN transistors and lateral PNP transistors. Among them, the N-type source / drain implantation region 3 is the emitter of the NPN, the P well 1 serves as the base of the NPN and the collector of the PNP transistor at the same time, the HVNMOS drift region 2 serves as the collector of the NPN transistor and the base of the PNP transistor at the same time, the P-type source / drain implantation region 4 is the emitter of the PNP transistor, and the polysilicon gate 7 is covered on the P well 1 and the HVNMOS drift region 2 and serves as the gate control terminal to modulate the ESD protection performance of the SCR structure. In the process, precise size control of the N-type source / drain implantation region 3 and the P-type source / drain implantation region 4 is achieved through the device active region 8 and the polysilicon gate 7; on the layout, an NPNP structure is arranged up and down. Such a design巧妙地 (it is ingenious to) forms a "king" - shaped lateral NPNP SCR structure with the PWELL side lead 5 and the HVN side lead 6; as shown in Fig. 5(a) and Fig. 5(b), through TLP test evaluation, the current discharge capacity per unit area of this structure reaches more than 0.01 A / μm, which is more than 3 times that of the GCDIODE protection structure of the same process.

[0031] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims. It should be noted that there is an unclear Chinese word "巧妙地" in the original text which is translated as "it is ingenious to" tentatively. If there is a more accurate English expression for this word in the context of this patent text, it can be adjusted accordingly.​

Claims

1. A gate-modulated SCRESD protection device structure based on high-temperature SOI technology, characterized in that, It includes a P-well (1), an HVNMOS drift region (2), an N-type source / drain injection region (3), a P-type source / drain injection region (4), a P-type injected PWELL side lead-out terminal (5), an N-type injected HVN side lead-out terminal (6), a polygate (7), a device active region (8), and a contact hole (9). The polygate (7) covers the P-well (1) and the HVNMOS drift region (2) and serves as the gate control terminal to modulate the ESD protection performance of the SCR structure. The active region (8) of the device and the polygate (7) enable precise dimensional control of the N-type source / drain injection region (3) and the P-type source / drain injection region (4); The PWELL side lead (5) is located on the lead-out side of the P well (1), and the N-type injected HVN side lead (6) is located on the lead-out side of the HVNMOS drift region (2). The contact hole (9) is provided on the N-type source / drain injection region (3), the P-well (1), the HVNMOS drift region (2), and the P-type source / drain injection region (4).

2. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 1, characterized in that, The P-well (1) and the HVNMOS drift region (2) are both elongated strips. The P-well (1), the PWELL side lead-out (5), the HVNMOS drift region (2) and the HVN side lead-out (6) together form a cross shape.

3. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 1, characterized in that, There are two N-type source / drain injection regions (3), located before and after the P-well (1) lead-out side respectively; there are two P-type source / drain injection regions (4), located before and after the HVNMOS drift region (2) lead-out side respectively; the N-type source / drain injection regions (3), the P-well (1), the HVNMOS drift region (2), and the P-type source / drain injection regions (4) constitute a transverse NPNP structure.

4. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 3, characterized in that, The PWELL side lead-out terminal (5) is located in the middle of the P well (1) lead-out side, separating the two N-type source-drain injection regions (3) in front and behind; the HVN side lead-out terminal (6) is located in the middle of the HVNMOS drift region (2) lead-out side, separating the two P-type source-drain injection regions (4) in front and behind.

5. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 1, characterized in that, The contact holes (9) are provided in 7 groups, of which the two N-type source / drain injection regions (3) and the two P-type source / drain injection regions (4) are provided in a total of 4 groups, with 25 holes in each group; the PWELL side lead-out terminal (5) and the HVN side lead-out terminal (6) are provided in 1 group, with 2 holes in each group; the polygate (7) is provided in 1 group, with 2 holes; a total of 106 contact holes (9).

6. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 1, characterized in that, The flat side of the P-well (1) is back-to-back with the flat side of the HVNMOS drift region (2), and the poly gate (7) is covered thereon; the lateral lengths of the P-well (1) and the HVNMOS drift region (2) are each 0.55 μm, and the total length of the poly gate (7) is 1.3 μm.

7. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 1, characterized in that, There are two N-type source / drain injection regions (3) and two P-type source / drain injection regions (4). The vertical width of these four regions is 10 μm. The effective device width is 20 μm, and the lateral length of the portion not covered by the polygate (7) is 1.83 μm.

8. The gate modulation SCRESD protection device structure based on high-temperature SOI technology as described in claim 1, characterized in that, The PWELL side lead (5) is a P-type injection, and the HVN side lead (6) is an N-type injection.

Images