An insulated gate bipolar transistor and method of manufacture

Abstract

The application provides an insulated gate bipolar transistor and a manufacturing method, wherein the transistor comprises a substrate and an epitaxial layer; the epitaxial layer comprises a main IGBT area and a detection IGBT area; a main IGBT tube is constructed on the main IGBT area; a detection IGBT tube is constructed on the detection IGBT area; the emitter of the main IGBT tube is connected with the emitter of the detection IGBT tube through a detection resistor, and the gate of the main IGBT tube is connected with the gate of the detection IGBT tube. The back-to-back Zener diode of the application is connected between the gate of the detection IGBT and the emitter of the detection IGBT, and is used for clamping the voltage between the gate of the detection IGBT and the emitter of the detection IGBT during electrostatic discharge (ESD), and providing ESD protection for the forward and reverse currents between the gate of the detection IGBT and the emitter of the detection IGBT.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an insulated gate bipolar transistor and its manufacturing method. Background Technology

[0002] ESD (Electro-Static Discharge) is a common problem in the manufacture and use of semiconductor transistors and related devices. For example, ESD can damage or destroy the affected transistor and disrupt the operation of the connected circuitry when static charge imparted by humans or tools comes into unintentionally into contact with the conductive parts of the transistor.

[0003] ESD (Electrostatic Discharge) damage to electronic products can be categorized into two types: sudden damage and latent damage. Sudden damage refers to severe damage to components, resulting in loss of function. This type of damage is usually detectable during quality inspection in the production process, primarily incurring rework and repair costs for the factory. Latent damage, on the other hand, refers to partial damage to components, where function is not yet lost and cannot be detected during production inspection. However, it can cause instability during use, leading to intermittent malfunctions and posing a greater threat to product quality. Of these two types of damage, latent failures account for 90%, while sudden failures account for only 10%. In other words, 90% of ESD damage is undetectable and only becomes apparent when the product reaches the user. Summary of the Invention

[0004] To address the aforementioned shortcomings in the prior art, the present invention provides an insulated gate bipolar transistor and its manufacturing method, which solves the problem that existing insulated gate bipolar transistors (IGBTs) are susceptible to electrostatic damage.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows: an insulated gate bipolar transistor, comprising: a substrate and an epitaxial layer;

[0006] When a buffer layer is present, the buffer layer is disposed on the substrate, and the epitaxial layer is disposed on the buffer layer; when no buffer layer is present, the epitaxial layer is disposed on the substrate; the epitaxial layer includes a main IGBT region and a detection IGBT region; a main IGBT transistor is constructed on the main IGBT region; a detection IGBT transistor is constructed on the detection IGBT region; the emitter of the main IGBT transistor is connected to the emitter of the detection IGBT transistor through a detection resistor, and its gate is connected to the gate of the detection IGBT transistor.

[0007] Furthermore, the detection IGBT region includes: a first junction doped region, a detection IGBT emitter region, and a detection IGBT gate trench region.

[0008] Furthermore, a first insulating region is provided within the gate trench region of the detection IGBT; the first insulating region includes an n-type doped region and a p-type doped region; the n-type doped region and the p-type doped region are alternately superimposed to form a back-to-back Zener diode.

[0009] Furthermore, the gate trench region of the detection IGBT is connected to the emitter region of the detection IGBT.

[0010] Furthermore, the number of n-type doped regions is greater than or equal to 2, and the number of p-type doped regions is greater than or equal to 2.

[0011] Furthermore, the main IGBT region includes: a second junction doped region, a main IGBT gate trench region, and a main IGBT emitter region.

[0012] Furthermore, a second insulating region is provided within the gate trench region of the main IGBT.

[0013] Furthermore, the main IGBT region and the detection IGBT region do not make contact.

[0014] A method for manufacturing an insulated gate bipolar transistor includes the following steps:

[0015] S1. An epitaxial layer is formed on a substrate or buffer layer;

[0016] S2. Form the detection IGBT emitter region and the main IGBT emitter region on the epitaxial layer;

[0017] S3. A detection IGBT emitter is formed in the detection IGBT emitter region, and a detection IGBT gate trench region is formed.

[0018] S4. A main IGBT emitter is formed in the main IGBT emitter region, and a main IGBT gate trench region is formed.

[0019] S5. A detection IGBT gate is formed in the detection IGBT gate trench region, and a main IGBT gate is formed in the main IGBT gate trench region.

[0020] S6. Electrically connect the gate of the detection IGBT to the gate of the main IGBT;

[0021] S7. At the gate of the IGBT, n-type doped regions and p-type doped regions are alternately superimposed to form a back-to-back Zener diode.

[0022] S8. Connect one end of the back-to-back Zener diode to the emitter of the detection IGBT, and connect the other end to the gate of the main IGBT and the gate of the detection IGBT respectively.

[0023] Furthermore, the back-to-back Zener diodes are obtained through multiple ion implantations.

[0024] The technical solution of the present invention has at least the following advantages and beneficial effects: The back-to-back Zener diode of the present invention is connected between the gate and the emitter of the detection IGBT and is used to configure the voltage between the gate and the emitter of the detection IGBT during electrostatic discharge (ESD) and to provide ESD protection against the forward and reverse currents between the gate and the emitter of the detection IGBT. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the substrate doped junction of an insulated gate bipolar transistor.

[0026] Figure 2 This is a schematic diagram of the gate trench of an insulated gate bipolar transistor.

[0027] Figure 3 This is a schematic diagram of the internal and external electrical connections of an insulated-gate bipolar transistor.

[0028] Figure 4 This is the equivalent circuit diagram of an insulated-gate bipolar transistor;

[0029] Figure 5 This is a flowchart of a method for manufacturing an insulated-gate bipolar transistor.

[0030] Figure 6 This is a schematic diagram of the top of an insulated-gate bipolar crystal (without an external detection resistor).

[0031] Figure 7 This is a schematic diagram of the top of an insulated-gate bipolar crystal (with an external detection resistor added);

[0032] Figure 8 This is a side view of the second implementation of a back-to-back Zener diode;

[0033] Figure 9 This is a top view of the second implementation of a back-to-back Zener diode;

[0034] Figure 10 This is a side view of the third implementation of a back-to-back Zener diode.

[0035] Figure 11 This is a top view of the third implementation of a back-to-back Zener diode;

[0036] Figure 12 This is a side view of the fourth implementation of a back-to-back Zener diode.

[0037] Figure 13This is a schematic diagram of another aspect of the fourth implementation of back-to-back Zener diodes;

[0038] Figure 14 This is a top view of the fourth implementation of a back-to-back Zener diode;

[0039] Figure 15 This is a top view of the fifth implementation of a back-to-back Zener diode;

[0040] Figure 16 This is a side view of the sixth implementation of a back-to-back Zener diode.

[0041] Figure 17 This is a top view of the sixth implementation of a back-to-back Zener diode;

[0042] Figure 18 This is an equivalent circuit diagram of another insulated-gate bipolar transistor;

[0043] Figure 19 for Figure 18 Top view diagram;

[0044] Among them, 100 is the epitaxial layer; 101 is the buffer layer; 102 is the substrate; 201 is the emitter region of the detection IGBT; 202 is the p-type doped region; 203 is the n-type doped region; 204 is the gate trench region of the detection IGBT; 205 is the main IGBT emitter region; 206 is the main IGBT gate trench region; 207 is the first insulating region; 208 is the second insulating region; 209 is the isolation region; 301 is the emitter contact of the detection IGBT; 302 is the detection resistor; 303 is the common gate contact; 304 is the metal conductor; 305 is the isolation insulating region; 306 is the first n-type doped region. 307. N-type doped region; 308. First anode region; 309. First cathode region; 310. Second cathode region; 311. Second anode region; 401. Detection IGBT; 402. Main IGBT; 403. Back-to-back Zener diode; 501. Top main IGBT emitter region; 502. Top detection IGBT emitter region; 503. Top detection IGBT gate region; 504. Top main IGBT region; 505. Top detection resistor; 506. Top metal region; 507. Top isolation region; 508. Top diode region. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] like Figures 1-4 As shown, an insulated gate bipolar transistor includes: a substrate 102 and an epitaxial layer 100;

[0047] When a buffer layer 101 is present, the buffer layer 101 is disposed on the substrate 102, and the epitaxial layer 100 is disposed on the buffer layer 101; when there is no buffer layer 101, the epitaxial layer 100 is disposed on the substrate 102; the epitaxial layer 100 includes a main IGBT region and a detection IGBT region; a main IGBT transistor 402 is constructed on the main IGBT region; a detection IGBT transistor 401 is constructed on the detection IGBT region; the emitter of the main IGBT transistor 402 and the emitter of the detection IGBT transistor 401 are connected through a detection resistor 302, and its gate is connected to the gate of the detection IGBT transistor 401.

[0048] The detection IGBT region includes: a first junction doped region 103, a detection IGBT emitter region 201, and a detection IGBT gate trench region 204.

[0049] The first junction doped region 103 forms the IGBT emitter region 201 and the IGBT gate trench region 204.

[0050] The detection IGBT gate trench region 204 is provided with a first insulating region 207; the first insulating region 207 includes an n-type doped region 203 and a p-type doped region 202; the n-type doped region 203 and the p-type doped region 202 are alternately superimposed to form a back-to-back Zener diode 403, which is the first implementation of the back-to-back Zener diode 403.

[0051] The first implementation method is as follows: an n-type doped region 203 is used as the first layer, and a p-type doped region 202 is superimposed on the first layer to form the second layer. The n-type doped region 203 is then superimposed on the second layer to form the third layer, and the p-type doped region 202 is superimposed on the third layer to form the fourth layer. The n-type doped region 203 and the p-type doped region 202 are superimposed alternately and vertically until the set number of layers is reached, with the n-type doped region 203 used as the first and last layers.

[0052] In this embodiment, the material used for the n-type doped region 203 and the p-type doped region 202 is polycrystalline silicon, and multiple polycrystalline silicon layers are constructed. The polycrystalline silicon layers are deposited alternately on the first insulating region 207 according to the n-type doped region 203 and the p-type doped region 202.

[0053] During the first implantation, n-type dopant (N-type semiconductor) is implanted into the first insulating region 207 to construct the n-type doped region 203, providing the anode region of the back-to-back Zener diode 403. During the second implantation, p-type dopant (P-type semiconductor) is implanted into the first insulating region 207 to construct the p-type doped region 202, forming the cathode region of the back-to-back Zener diode 403. The first and second implantation operations are repeated sequentially to construct the back-to-back Zener diode 403. The implantation operation is ion implantation.

[0054] The detection IGBT gate trench region 204 is connected to the detection IGBT emitter region 201.

[0055] The number of n-type doped regions 203 is greater than or equal to 2, and the number of p-type doped regions 202 is greater than or equal to 2.

[0056] The main IGBT region includes: a second junction doped region 104, a main IGBT gate trench region 206, and a main IGBT emitter region 205.

[0057] The main IGBT emitter region 205 and the main IGBT gate trench region 206 are formed in the second junction doped region 104.

[0058] In this embodiment, the first junction doped region 103 and the second junction doped region 104 may be p-doped.

[0059] A second insulating region 208 is provided within the main IGBT gate trench region 206.

[0060] Figure 4 This is an equivalent circuit diagram of an insulated gate bipolar transistor. During normal operation, the main IGBT 402 may be affected by various overcurrent conditions, which may damage the main IGBT 402 or related circuits. The detection IGBT 401 can be designed to perform fast and accurate current detection relative to the main current (the current on the emitter of the main IGBT 402). The current can be measured by the sensing resistor 302. For example, the main current can be quickly shut off in response to the detection of overcurrent, minimizing the extent of damage.

[0061] The current through the sensing resistor 302 is proportional to the current through the emitter of the main IGBT 402.

[0062] exist Figure 4In the circuit shown, current can be divided between the detection current and the main current. Furthermore, since the detection IGBT 401 is much smaller than the main IGBT 402, the detection IGBT 401 is more sensitive to ESD protection requirements.

[0063] exist Figure 4 In the process, the gate of the detection IGBT 401 is connected to the gate of the main IGBT 402, corresponding to... Figure 3 In the middle, the gate of the detection IGBT 401 is electrically connected to the gate of the main IGBT 402 through the common gate contact 303.

[0064] The collector of the detection IGBT 401 is connected to the collector of the main IGBT 402. Its back-to-back Zener diode 403 is connected between the gate and emitter of the detection IGBT 401 and is used to configure the clamping voltage between the detection gate and the detection emitter during ESD.

[0065] The main IGBT region and the detection IGBT region do not contact each other. Furthermore, the non-contact region between the first junction doped region 103 and the second junction doped region 104 is defined as the isolation region 209.

[0066] like Figure 5 As shown, a method for manufacturing an insulated gate bipolar transistor includes the following steps:

[0067] S1. An epitaxial layer 100 is formed on the substrate 102 or the buffer layer 101;

[0068] S2. A detection IGBT emitter region 201 and a main IGBT emitter region 205 are formed on the epitaxial layer 100;

[0069] S3. A detection IGBT emitter is formed at the detection IGBT emitter region 201, and a detection IGBT gate trench region 204 is formed.

[0070] S4. A main IGBT emitter is formed at the main IGBT emitter region 205, and a main IGBT gate trench region 206 is formed.

[0071] S5. A detection IGBT gate is formed at the detection IGBT gate trench region 204, and a main IGBT gate is formed at the main IGBT gate trench region 206.

[0072] S6. Electrically connect the gate of the detection IGBT to the gate of the main IGBT;

[0073] S7. At the gate of the IGBT, n-type doped region 203 and p-type doped region 202 are alternately superimposed to form a back-to-back Zener diode 403.

[0074] S8. Connect one end of the back-to-back Zener diode 403 to the emitter of the detection IGBT, and connect the other end to the gate of the main IGBT and the gate of the detection IGBT respectively.

[0075] The specific process operations in steps S1 to S8 include: deposition, epitaxy, ion implantation, and etching.

[0076] The back-to-back Zener diode 403 was obtained through multiple ion implantations.

[0077] Figure 6 This is a top schematic diagram of an insulated gate bipolar transistor (IGBT) lacking a detection resistor 302, including: a top main IGBT emitter region 501, a top detection IGBT emitter region 502, a top main IGBT region 504, and a top detection IGBT gate region 503.

[0078] Figure 7 This is a top schematic diagram of an insulated gate bipolar transistor, including: a top main IGBT emitter region 501, a top detection IGBT emitter region 502, a top main IGBT region 504, a top detection IGBT gate region 503, and a top detection resistor 505. The top detection resistor 505 is the physical embodiment of the detection resistor 302, and the top detection resistor 505 connects the top detection IGBT emitter region 502 and the top main IGBT emitter region 501.

[0079] In this embodiment, the back-to-back Zener diode also includes a second implementation: such as Figure 8 As shown, the first insulating region 207 includes an n-type doped region 203 and a p-type doped region 202; the n-type doped region 203 and the p-type doped region 202 are alternately superimposed and isolated from the anode and cathode of the back-to-back Zener diode by the isolation insulating region 305. The metal conductor 304 is connected to the detection IGBT emitter region 201, the back-to-back Zener diode, and the detection resistor 302, respectively, so that the three are electrically connected.

[0080] The second implementation method is as follows: Two p-type doped regions 202 are used as the first layer. The two p-type doped regions 202 in the first layer are arranged symmetrically, and an n-type doped region 203 is provided between the two p-type doped regions 202 in the first layer. The n-type doped regions 203 are superimposed on the first layer to form the second layer. The two n-type doped regions 203 in the second layer are arranged symmetrically, and the p-type doped regions 202 are superimposed on the second layer to form the third layer. Subsequently, the n-type doped regions 203 and p-type doped regions 202 are superimposed alternately, and the superposition method is vertical superposition, until the set number of layers is reached. The n-type doped regions 203 are used as the last layer. The two n-type doped regions 203 in the last layer are arranged symmetrically. The n-type doped regions 203 and p-type doped regions 202 in the other layers except the first layer are all separated by an isolation insulating region 305.

[0081] Figure 9 for Figure 8 The top schematic diagram shows that the top metal region 506 is connected to the top detection resistor 505, the top detection IGBT emitter region 502, and the top detection IGBT gate region 503, respectively. The top isolation insulation region 507 is used to isolate the anode and cathode of the back-to-back Zener diodes.

[0082] In this embodiment, the back-to-back Zener diode also includes a third implementation: such as Figure 10 As shown, the first insulating region 207 includes an n-type doped region 203 and a p-type doped region 202; the n-type doped region 203 and the p-type doped region 202 are alternately superimposed in a lateral superposition manner. The metal conductor 304 is connected to the detection IGBT emitter region 201, the back-to-back Zener diode, and the detection resistor 302, respectively, so that the three are electrically connected.

[0083] The third implementation method is as follows: one side of the n-type doped region 203 of the first layer is connected to the inner wall of the first insulating region 207, and the other side is connected to one side of the p-type doped region 202 of the second layer. The other side of the p-type doped region 202 of the second layer is then connected to one side of the n-type doped region 203 of the third layer. This method is used to overlap the regions until the set number of layers is reached, and the n-type doped region 203 is used as the last layer.

[0084] Figure 11 for Figure 10 The top schematic diagram shows that the top metal region 506 is connected to the top detection resistor 505, the top detection IGBT emitter region 502, and the top detection IGBT gate region 503, respectively, and the top diode region 508 is located within the top detection IGBT gate region 503.

[0085] Back-to-back Zener diodes also include a fourth implementation method, such as... Figure 12 , 13As shown in Figure 14, the first layer of n-type doped region 306 is cuboid in shape. Its two sides are connected to the inner wall of the first insulating region 207, and its other two sides are surrounded by the next layer of p-type doped region 202. Together with the previous layer of n-type doped region 306, they form a new cuboid shape. The p-type doped region 202 and the n-type doped region 203 overlap. Each layer forms a cuboid shape with all the previous layers. Except for the last cuboid shape, the two sides of all the cuboid shapes are connected to the inner wall of the first insulating region 207, and the other two sides are connected to the next layer of p-type doped region 202 or n-type doped region 203. This continues until the set number of layers is reached, and ends with the last layer of n-type doped region 307. The last layer of n-type doped region 307 fills the gap between the previous layers and the first insulating region 207.

[0086] Back-to-back Zener diodes also include a fifth implementation, such as... Figure 15 As shown, the first layer of n-type doped region 203 is cuboid in shape, with one side connected to the inner wall of the first insulating region 207, and the other three sides surrounded by the next layer of p-type doped region 202, forming a new cuboid shape with the previous layer of n-type doped region 203. The p-type doped region 202 and the n-type doped region 203 overlap, and each layer forms a cuboid shape with all the previous layers. Except for the last cuboid shape, one side of the other cuboid shapes is connected to the inner wall of the first insulating region 207, and the other three sides are connected to the next layer of p-type doped region 202 or n-type doped region 203, until the set number of layers is reached, ending with p-type doped region 202. The p-type doped region 202 of the last layer fills the gap between the previous layer of n-type doped region 203 and the inner wall of the first insulating region 207. In the fifth implementation, the n-type doped region 203 of the first layer is designated as the first anode region 308, and the p-type doped region 202 of the last layer is designated as the first cathode region 309.

[0087] Back-to-back Zener diodes also include a sixth implementation, such as... Figure 16 and 17As shown, the first layer of n-type doped region 203 is cuboid in shape, with its four sides surrounded by the next layer of p-type doped region 202. The p-type doped region 202 and all the preceding layers form a new cuboid shape. The p-type doped region 202 and the n-type doped region 203 overlap. Except for the first layer, each of the other layers wraps around the previous layer until a set number of layers is reached. Each layer forms a cuboid shape with all the preceding layers. Except for the last layer, the four sides of the other cuboid shapes are connected to the adjacent p-type doped region 202 or n-type doped region 203 and end with the p-type doped region 202. The p-type doped region 202 of the last layer fills the gap between the previous layer's n-type doped region 203 and the inner wall of the first insulating region 207. In the sixth implementation, the first layer of n-type doped region 203 is named the second anode region 311, and the last layer of p-type doped region 202 is named the second cathode region 310.

[0088] In this embodiment, another equivalent circuit diagram of an insulated gate bipolar transistor is also provided, such as... Figure 18 As shown, it includes multiple detection IGBT tubes. By placing multiple detection IGBTs at different positions in the cell, ESD detection at different positions can be achieved, thereby maximizing the protection range. The purpose is to test different positions in the cell.

[0089] Figure 19 for Figure 18 The top diagram shows that implanting IGBTs at different locations can maximize the detection range.

[0090] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An insulated-gate bipolar transistor, characterized in that, include: A substrate (102) and an epitaxial layer (100); when there is a buffer layer (101), the buffer layer (101) is disposed on the substrate (102), and the epitaxial layer (100) is disposed on the buffer layer (101); when there is no buffer layer (101), the epitaxial layer (100) is disposed on the substrate (102); the epitaxial layer (100) includes: a main IGBT region and a detection IGBT region; a main IGBT transistor (402) is constructed on the main IGBT region; a detection IGBT transistor (401) is constructed on the detection IGBT region; the emitter of the main IGBT transistor (402) is connected to the emitter of the detection IGBT transistor (401) through a detection resistor (302), and its gate is connected to the gate of the detection IGBT transistor (401); The detection IGBT region includes: a first junction doped region (103), a detection IGBT emitter region (201), and a detection IGBT gate trench region (204). The detection IGBT gate trench region (204) is provided with a first insulating region (207); the first insulating region (207) includes an n-type doped region (203) and a p-type doped region (202); the n-type doped region (203) and the p-type doped region (202) are alternately superimposed to form a back-to-back Zener diode (403). The detection IGBT gate trench region (204) is connected to the detection IGBT emitter region (201); Connect one end of the back-to-back Zener diode (403) to the emitter of the detection IGBT, and connect the other end to the gate of the detection IGBT; The back-to-back Zener diode (403) is obtained through multiple ion implantations. The formation of the back-to-back Zener diode (403) includes: using two p-type doped regions (202) as the first layer, the two p-type doped regions (202) of the first layer are symmetrically arranged, and an n-type doped region (203) is provided between the two p-type doped regions (202) of the first layer. The n-type doped regions (203) are superimposed on the first layer to form the second layer. The two n-type doped regions (203) of the second layer are symmetrically arranged. The p-type doped regions (202) are superimposed on the second layer to form the third layer. Subsequently, the n-type doped regions (203) and p-type doped regions (202) are alternately superimposed in a vertical superposition manner until a set number of layers is reached. The n-type doped regions (203) are used as the last layer. The two n-type doped regions (203) of the last layer are symmetrically arranged. The n-type doped regions (203) and p-type doped regions (202) of the other layers except the first layer are all isolated by an isolation insulating region (305).

2. The insulated gate bipolar transistor according to claim 1, characterized in that, The number of n-type doped regions (203) is greater than or equal to 2, and the number of p-type doped regions (202) is greater than or equal to 2.

3. The insulated-gate bipolar transistor according to claim 1, characterized in that, The main IGBT region includes: a second junction doped region (104), a main IGBT gate trench region (206), and a main IGBT emitter region (205).

4. The insulated gate bipolar transistor according to claim 3, characterized in that, A second insulating region (208) is provided within the gate trench region (206) of the main IGBT.

5. The insulated-gate bipolar transistor according to claim 1, characterized in that, The main IGBT region and the detection IGBT region are not in contact.

6. A method for manufacturing an insulated-gate bipolar transistor according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. An epitaxial layer (100) is formed on a substrate (102) or a buffer layer (101). S2. A detection IGBT emitter region (201) and a main IGBT emitter region (205) are formed on the epitaxial layer (100). S3. A detection IGBT emitter is formed at the detection IGBT emitter region (201), and a detection IGBT gate trench region (204) is formed. S4. A main IGBT emitter is formed in the main IGBT emitter region (205), and a main IGBT gate trench region (206) is formed. S5. A detection IGBT gate is formed in the detection IGBT gate trench region (204), and a main IGBT gate is formed in the main IGBT gate trench region (206). S6. Electrically connect the gate of the detection IGBT to the gate of the main IGBT; S7. At the gate of the IGBT, n-type doped region (203) and p-type doped region (202) are alternately superimposed to form a back-to-back Zener diode (403). S8. Connect one end of the back-to-back Zener diode (403) to the emitter of the detection IGBT, and connect the other end to the gate of the main IGBT and the gate of the detection IGBT respectively.

7. The method for manufacturing an insulated-gate bipolar transistor according to claim 6, characterized in that, The back-to-back Zener diode (403) was obtained through multiple ion implantations.

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