A direct current bus voltage equalization circuit and a control method thereof

Abstract

The application belongs to the technical field of DC bus voltage equalization, and specifically discloses a DC bus voltage equalization circuit and a control method, which comprises: a capacitor voltage division circuit, which outputs an upper voltage and a lower voltage of a DC bus; a first adder, whose input is the upper voltage and the lower voltage of the DC bus, and whose output is connected to a proportional link and an integral differential link in sequence; an output of the integral differential link is connected to a first input end of a second adder, and a second input end of the second adder is connected to a zero potential; an output of the second adder is connected to a first input end of a comparator, a second output end of the comparator is connected to a set AC voltage, and an output end of the comparator is pulled up to obtain an output signal, which is used for controlling the upper voltage and the lower voltage of the DC bus to be balanced through a signal normalizing device and a signal inverting device respectively. The application keeps the DC bus voltage balanced through a negative feedback method, which is conducive to prolonging the service life of the capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of direct current bus voltage equalization technology, in particular to a direct current bus voltage equalization circuit and a control method thereof. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] With the rapid development and progress of power electronic technology, various power electronic products such as rectifiers, frequency converters, inverters, industrial power supplies, emergency power supplies, etc. have been closely related to our lives. Many fields, such as home appliances, industrial control, military field, etc., as long as they involve power conversion, power electronic products are indispensable. No matter which kind of power electronic product, its direct current bus needs to be controlled by a voltage equalization circuit to ensure that the bus voltage remains balanced.

[0004] In many AC / DC, DC / DC converters, the up and down balance of the direct current bus must be controlled. For example, a three-phase three-level inverter (which can be used in energy storage, photovoltaic products, etc.) will cause the direct current bus to be biased when the inverter output is unbalanced. In the case of light load, the circuit works in an intermittent working state, which may cause serious unbalanced voltage of the input capacitor. In severe cases, it may even appear that one side basically does not output power and the input voltage is zero, while the other side input voltage is twice the normal voltage, which is the extreme case of unbalanced voltage. Since the voltage withstand of the capacitor is limited, unbalanced voltage will cause the capacitor voltage to exceed the rated voltage, and the withstand voltage of the switch tube and output rectifier diode of the converter will not be enough, resulting in damage to the converter. Therefore, certain methods must be taken to balance the voltage on the direct current bus.

[0005] Many products use bus capacitors in parallel with resistors to divide voltage, and maintain the up and down balance of the direct current bus by controlling the duty cycle of each switch. However, in actual circuits, due to the inconsistency of drive pulse width caused by parameter dispersion, inconsistency of efficiency, etc., the output power of the two sides will not be equal. Due to the difference in parameters and the particularity of the actual application circuit structure, voltage imbalance will still occur. In a lighter degree, it will reduce the service life of the capacitor, and in a more severe degree, it will cause overvoltage and damage.

[0006] If the equivalent loads of the positive and negative bus capacitors are not equal, it will also cause unbalanced voltage of the direct current bus. For example, in some special occasions, the equivalent loads of the positive and negative bus capacitors cannot be equal, and the boost states of the positive and negative buses cannot be completely consistent, so the direct current bus voltage equalization effect cannot be guaranteed. SUMMARY

[0007] In order to solve the above problems, the application provides a DC bus voltage equalization circuit and a control method thereof, which adopts a negative feedback control method to balance the upper voltage and the lower voltage of the DC bus, and solves the technical problem of poor voltage equalization when the equivalent loads of the positive bus capacitor and the negative bus capacitor are not equal.

[0008] In some embodiments, the following technical solutions are adopted:

[0009] A DC bus voltage equalization circuit comprises:

[0010] A capacitor voltage dividing circuit is used to convert a single power supply into a positive power supply and a negative power supply, and outputs the upper voltage and the lower voltage of the DC bus.

[0011] A first adder has the upper voltage and the lower voltage of the DC bus as inputs, and has a proportional link and an integral differential link connected in sequence as outputs, the output of the integral differential link is connected to a first input terminal of a second adder, a second input terminal of the second adder is connected to a zero potential, the output of the second adder is connected to a first input terminal of a comparator, a second output terminal of the comparator is connected to a set AC voltage, the output terminal of the comparator is pulled up, and the obtained output signal is respectively sent to a signal positive device and a signal negative device, and is used to control the upper voltage and the lower voltage of the DC bus to be balanced.

[0012] As an optional solution, the capacitor voltage dividing circuit comprises:

[0013] A first IGBT is connected to the signal positive device, a second IGBT is connected to the signal negative device, the first IGBT and the second IGBT are connected in series to form a first series branch, a capacitor C1 and a capacitor C2 are connected in series to form a second series branch, and the first series branch and the second series branch are connected in parallel; an inductor L1 and a resistor R1 are connected in series between the first IGBT and the second IGBT and between the capacitor C1 and the capacitor C2, and a resistor R6 is connected in parallel across the inductor L1.

[0014] As an optional solution, the obtained output signal is respectively sent to the signal positive device and the signal negative device after being processed, and is used to control the on-off of the first IGBT and the second IGBT; when the first IGBT is turned on and the second IGBT is turned off, the difference V3 between the upper voltage and the lower voltage of the DC bus charges the capacitor C2, and the capacitor C1 is discharged through the resistor R1, the resistor R6 and the inductor L1; when the second IGBT is turned on and the first IGBT is turned off, the difference V3 between the upper voltage and the lower voltage of the DC bus charges the capacitor C1, and the capacitor C2 is discharged through the resistor R1, the resistor R6 and the inductor L1.

[0015] As an optional solution, when the upper voltage of the DC bus increases, the duty cycle of the output signal increases, the time of the first IGBT turning on increases, and the time of the second IGBT turning on decreases; the charging time of the capacitor C2 becomes longer, the charging time of the capacitor C1 becomes shorter, the voltage difference across the capacitor C2 becomes larger, and the voltage difference across the capacitor C1 becomes smaller, so that the upper voltage of the DC bus decreases and the lower voltage of the DC bus increases, achieving the balance of the upper voltage and the lower voltage of the DC bus.

[0016] As an optional solution, when the lower voltage of the DC bus increases, the duty cycle of the output signal increases, the time of the second IGBT turning on increases, and the time of the first IGBT turning on decreases; the charging time of the capacitor C1 becomes longer, the charging time of the capacitor C2 becomes shorter, the voltage difference across the capacitor C1 becomes larger, and the voltage difference across the capacitor C2 becomes smaller, so that the lower voltage of the DC bus decreases and the upper voltage of the DC bus increases, achieving the balance of the upper voltage and the lower voltage of the DC bus.

[0017] In some other embodiments, the following technical solutions are adopted:

[0018] A DC bus voltage balancing control method, comprising:

[0019] The upper voltage and the lower voltage of the DC bus output by the capacitor voltage dividing circuit are input to a first adder, and after being output through a proportional link and an integral and differential link, are added to zero potential by a second adder to obtain a signal UD1;

[0020] The obtained signal UD1 is compared with a set AC voltage UTR, and based on the sizes of the two, a voltage UTR or -UTR is output respectively; so as to obtain a PWM signal UD2 with a set duty cycle;

[0021] The signal UD2 is pulled up to obtain a signal UD3;

[0022] The signal UD3 is subjected to voltage inversion and voltage inversion respectively to control the upper voltage and the lower voltage of the DC bus, so that the upper voltage and the lower voltage of the DC bus are balanced.

[0023] As an optional solution, the signal UD3 is subjected to voltage inversion, and the signal remains unchanged, and is used to control the on-off of the first IGBT;

[0024] The signal UD3 is subjected to voltage inversion, and the signal is inverted, and is used to control the on-off of the second IGBT;

[0025] When the first IGBT is turned on and the second IGBT is turned off, the difference between the upper voltage and the lower voltage of the DC bus charges the capacitor C2, and the capacitor C1 discharges;

[0026] When the second IGBT is turned on and the first IGBT is turned off, the difference between the upper voltage and the lower voltage of the DC bus charges the capacitor C1, and the capacitor C2 discharges.

[0027] As an optional scheme, when the upper voltage and the lower voltage of the DC bus are balanced, the PWM signals with duty cycles of 50% are obtained; the first IGBT and the second IGBT have the same opening time.

[0028] As an optional scheme, when the upper voltage of the DC bus increases, the duty cycle of the output signal increases, the opening time of the first IGBT increases, and the opening time of the second IGBT decreases; the charging time of the capacitor C2 becomes longer, the charging time of the capacitor C1 becomes shorter, the voltage difference between the two ends of the capacitor C2 becomes larger, and the voltage difference between the two ends of the capacitor C1 becomes smaller, so that the upper voltage of the DC bus decreases and the lower voltage increases, and the upper voltage and the lower voltage of the DC bus are balanced.

[0029] As an optional scheme, when the lower voltage of the DC bus increases, the duty cycle of the output signal increases, the opening time of the second IGBT increases, and the opening time of the first IGBT decreases; the charging time of the capacitor C1 becomes longer, the charging time of the capacitor C2 becomes shorter, the voltage difference between the two ends of the capacitor C1 becomes larger, and the voltage difference between the two ends of the capacitor C2 becomes smaller, so that the lower voltage of the DC bus decreases and the upper voltage increases, and the upper voltage and the lower voltage of the DC bus are balanced.

[0030] Compared with the prior art, the present application has the following advantages:

[0031] (1) The present application balances the DC bus by negative feedback, has the characteristics of good voltage balancing effect, is beneficial to prolong the service life of the capacitor, and ensures the output waveform quality of the positive and negative power supplies.

[0032] Other features and advantages of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 FIG. 1 is a structure schematic diagram of a DC bus voltage balancing control circuit in an embodiment of the present application;

[0034] Figure 2 FIG. 2 is a schematic diagram of a DC bus voltage balancing control method in an embodiment of the present application;

[0035] FIG. 3(a) is a simulation waveform schematic diagram of the upper voltage UP and the lower voltage UN of the DC bus;

[0036] FIG. 3(b) is a simulation waveform schematic diagram of the output voltage Udelta of the first adder;

[0037] FIG. 3(c) is a simulation waveform schematic diagram of the voltage UTR and the voltage UD1;

[0038] FIG. 3(d) is a simulation waveform schematic diagram of the voltage UD2;

[0039] Fig. 3 (e) is a schematic diagram of the simulation waveform of the voltage UD3;

[0040] Fig. 3 (f) is a schematic diagram of the simulation waveform of the IP voltage;

[0041] Fig. 3 (g) is a schematic diagram of the simulation waveform of the IN voltage;

[0042] Fig. 3 (h) is a schematic diagram of the simulation waveform of the bus voltage IZERO. DETAILED DESCRIPTION

[0043] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0044] It should be noted that the terms used herein are merely for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should be further understood that when the terms "comprise" and / or "include" are used in the specification, there is a reference to the presence of a feature, step, operation, device, component, and / or combinations thereof.

[0045] Embodiment one

[0046] As a single device, a single power source can be split into positive and negative power sources, and in most cases, the output DC bus voltage UP of the positive power source and the output DC bus voltage UN of the negative power source. The embodiment scheme is suitable for the voltage control of the upper and lower buses in the device in which a single power source is split into positive and negative power sources with equal voltages.

[0047] Based on this, in one or more embodiments, a DC bus voltage equalization circuit is disclosed, which combines Figure 1 , specifically comprising:

[0048] a capacitor voltage dividing circuit for converting a single power source into a positive and negative power source, the capacitor voltage dividing circuit outputting an upper voltage and a lower voltage of a DC bus;

[0049] In this embodiment, the capacitor voltage dividing circuit comprises: a first IGBT Q1 connected to a signal positive device, a second IGBT connected to a signal reverse device, the first IGBT Q1 and the second IGBT Q2 connected in series to form a first series branch, the capacitor C1 and the capacitor C2 connected in series to form a second series branch, and the first series branch and the second series branch connected in parallel; the inductor L1 and the resistor R1 connected in series between the first IGBT Q1 and the second IGBT Q2 and between the capacitor C1 and the capacitor C2, and the resistor R6 connected in parallel across the inductor L1.

[0050] The first IGBT Q1, the resistor R9 and the diode D1 are connected in parallel, the R9 is the current path when the first IGBT Q1 is turned off, the D1 plays a limiting role, and is used for protecting the first IGBT, when the emitter-collector voltage of the first IGBT is too high, the diode is turned on, the first IGBT is short-circuited, and the first IGBT is protected.

[0051] Similarly, the second IGBT Q2, the resistor R10 and the diode D2 are connected in parallel, the resistor R10 and the diode D2 have the same functions as described above; and the diode D1 and the diode D2 are connected in series.

[0052] The first adder has an input of the upper voltage and the lower voltage of the DC bus, the output of the first adder is connected to a proportional link and an integral differential link in sequence, the output of the integral differential link is connected to the first input end of the second adder, the second input end of the second adder is connected to a zero potential; the output of the second adder is connected to the first input end of a comparator, the second output end of the comparator is connected to a set AC voltage, the output end of the comparator is pulled up, and the obtained output signal passes through a signal positive device and a signal reverse device respectively, and is used for controlling the upper voltage and the lower voltage of the DC bus to be balanced.

[0053] In the embodiment, the upper voltage and the lower voltage of the bus are input into the first adder to perform addition calculation, and the output is Udelata, the theoretical value of Udelata should be 0, but there is a great fluctuation, in order to improve the stability, a proportional link (E1, the coefficient is-0.05) and an integral differential link (between E1 and M2) are added, and then the zero potential is added, to obtain UD1, it can be seen from the waveform diagram that, compared with Udelata, the fluctuation of UD1 is very small, the stability is obviously improved, and UD1 is continuously and stably kept at about 0V, in order to obtain the control pulse of Q1 and Q2, and the duty ratio of the control signal is 50%, so that the charging and discharging time of C1 and C2 is the same, the AC voltage UTR of 12V is input into the comparator (LM339) together with the obtained UD1, when UTR is greater than UD1, 12V voltage is output; when UTR is less than UD1, -12V voltage is output, because UD1 is 0V, so the PWM signal UD2 with the duty ratio of 50% is obtained; in order to improve the noise tolerance of the signal and enhance the anti-interference ability, UD2 is pulled up to obtain the signal UD3, and the signal UD3 is input into the voltage positive device E1, the signal is unchanged, and is used for controlling Q1; the UD3 is input into the voltage reverse device E2, the signal is reversed, and is used for controlling Q2.

[0054] In the embodiment, UTR is an AC voltage of 12V, and is compared with UD1 to obtain a PWM waveform with the highest value of 12V and the lowest value of -12V, finally serving as the turn-on driving voltage and the reverse turn-off bias voltage of Q1 and Q2.

[0055] The greater the positive gate voltage VGE of the IGBT, the lower the conduction resistance and the smaller the loss. However, if VGE is too large, once the IGBT overflows, the static column effect of the internal parasitic thyristor will cause the IGBT to fail. On the contrary, if VGE is too small, the working point of the IGBT may fall into the linear amplification zone, eventually leading to the overheating damage of the device. In any case, the gate drive voltage at the turn-on time should be between 12-20V.

[0056] When the gate voltage is zero, the IGBT is in the off state. Because the IGBT may withstand a large dv / dt during the off process, accompanied by a turn-off surge current, the gate turn-off voltage is disturbed, which may cause the device to be mistakenly turned on. In order to ensure that the IGBT remains off when a dv / dt noise occurs on the collector-emitter voltage, a reverse turn-off bias must be applied to the gate. The use of reverse bias can also reduce the turn-off loss. The reverse bias should be between -5- -15V.

[0057] Therefore, considering the embodiment comprehensively, the UTR is selected as 12v alternating voltage.

[0058] When Q1 is turned on and Q2 is turned off, the voltage difference V3 between the upper and lower voltages of the DC bus charges the capacitor C2, and the capacitor C1 discharges through the resistor R1, the resistor R6 and the inductor L1; when Q2 is turned on and Q1 is turned off, V3 charges the capacitor C1, and the capacitor C2 discharges through the resistor R1, the resistor R6 and the inductor L1.

[0059] In this way, Q1 and Q2 can be turned on and off in segments within the entire cycle of UD3, and the time of Q1 and Q2 being turned on and off is the same.

[0060] In combination Figure 2 When the upper voltage and the lower voltage of the DC bus are balanced, PWM signals with a duty cycle of 50% are obtained; Q1 and Q2 have the same turn-on time, and the upper voltage and the lower voltage of the DC bus are balanced.

[0061] When the upper voltage of the DC bus increases, the duty cycle of the output signal increases, the turn-on time of Q1 increases, and the turn-on time of Q2 decreases; the charging time of the capacitor C2 becomes longer, the charging time of the capacitor C1 becomes shorter, the voltage difference across the capacitor C2 becomes larger, and the voltage difference across the capacitor C1 becomes smaller, so that the upper voltage of the DC bus decreases and the lower voltage of the DC bus increases, achieving the balance of the upper voltage and the lower voltage of the DC bus.

[0062] When the lower voltage of the DC bus increases, the duty cycle of the output signal increases, the turn-on time of Q2 increases, and the turn-on time of Q1 decreases; the charging time of the capacitor C1 becomes longer, the charging time of the capacitor C2 becomes shorter, the voltage difference across the capacitor C1 becomes larger, and the voltage difference across the capacitor C2 becomes smaller, so that the lower voltage of the DC bus decreases and the upper voltage of the DC bus increases, achieving the balance of the upper voltage and the lower voltage of the DC bus.

[0063] The embodiment achieves the effect of DC bus voltage equalization through the action of positive and negative feedback of the upper and lower voltages of the DC bus. When the DC bus voltage is unbalanced, the reverse control caused by the voltage change promotes the effect of DC bus voltage equalization.

[0064] In order to detect whether the control method has good bus voltage equalization effect when the upper and lower buses carry unbalanced loads, the embodiment detects by a detection circuit composed of H1, H2, H3, resistor R4 and resistor R5.

[0065] H1, H2 and H3 are current-controlled voltage sources, and the voltage generated thereby is affected by the current, which is amplified or reduced in proportion, Figure 1 The middle proportions are 0.01, 0.01 and 0.1 respectively; R4 and R5 are unbalanced loads, which are 1Ω and 10Ω respectively, and the difference is large.

[0066] The detection current of H2 is (UP-0) / R4=50A, the proportion is 0.01, and the IP voltage is (UP-0) / R4×0.01. If the bus voltage is equalized, IP should be 0.5V, i.e. 500mV.

[0067] The detection current of H1 is (0-UN) / R5=5A, the proportion is 0.01, and the IN voltage is (0-UN) / R5×0.01. If the bus voltage is equalized, IN should be 0.05V, i.e. 50mV.

[0068] The detection current of H3 is H2 current-H1 current=45A, the proportion is 0.1, and if the bus voltage is equalized, IZERO should be 4.5V.

[0069] Fig. 3(a)-(h) respectively shows the simulation waveform diagrams of the upper voltage UP and the lower voltage UN of the DC bus, the output voltage Udelta of the first adder, the voltages UTR and UD1, UD2, UD3, IP voltage, IN voltage and IZERO voltage. As can be seen from the waveforms of IP, IN and IZERO, the three have little fluctuation and are respectively stabilized at 500mV, 50mV and 4.5V. Therefore, it can be concluded that the control method described in the embodiment has very small voltage fluctuation under the condition of unequal loads, and can achieve very good voltage equalization effect.

[0070] Embodiment Two

[0071] In one or more embodiments, a DC bus voltage equalization control method is disclosed, which is based on the circuit structure described in Embodiment One and specifically includes:

[0072] The upper voltage and the lower voltage of the DC bus output by the capacitance voltage dividing circuit are input into a first adder, and after being output through a proportional link and an integral differential link, are added with zero potential in a second adder to obtain a signal UD1;

[0073] The signal UD1 is compared with a set AC voltage UTR, and based on the sizes of the two, a voltage UTR or -UTR is output respectively; thus a PWM signal UD2 with a set duty ratio is obtained;

[0074] The signal UD2 is pulled up to obtain a signal UD3;

[0075] The signal UD3 is subjected to voltage positive and voltage inversion, and is used to control the upper voltage and the lower voltage of the DC bus respectively, so that the upper voltage and the lower voltage of the DC bus are balanced.

[0076] The signal UD3 is subjected to voltage positive, and the signal remains unchanged, and is used to control the on-off of the first IGBT;

[0077] The signal UD3 is subjected to voltage inversion, and the signal is inverted, and is used to control the on-off of the second IGBT;

[0078] When the first IGBT is turned on and the second IGBT is turned off, the difference V3 between the upper voltage and the lower voltage of the DC bus charges the capacitor C2, and the capacitor C1 is discharged;

[0079] When the second IGBT is turned on and the first IGBT is turned off, the difference V3 between the upper voltage and the lower voltage of the DC bus charges the capacitor C1, and the capacitor C2 is discharged.

[0080] When the upper voltage and the lower voltage of the DC bus are balanced, the PWM signal with a duty ratio of 50% is obtained; the first IGBT and the second IGBT are turned on for the same time.

[0081] When the upper voltage of the DC bus increases, the duty ratio of the output signal increases, the time for which the first IGBT is turned on increases, and the time for which the second IGBT is turned on decreases; the charging time of the capacitor C2 becomes longer, the charging time of the capacitor C1 becomes shorter, the voltage difference between the two ends of the capacitor C2 becomes larger, and the voltage difference between the two ends of the capacitor C1 becomes smaller, so that the upper voltage of the DC bus decreases and the lower voltage of the DC bus increases, and the upper voltage and the lower voltage of the DC bus are balanced.

[0082] When the lower voltage of the DC bus increases, the duty ratio of the output signal increases, the time for which the second IGBT is turned on increases, and the time for which the first IGBT is turned on decreases; the charging time of the capacitor C1 becomes longer, the charging time of the capacitor C2 becomes shorter, the voltage difference between the two ends of the capacitor C1 becomes larger, and the voltage difference between the two ends of the capacitor C2 becomes smaller, so that the lower voltage of the DC bus decreases and the upper voltage of the DC bus increases, and the upper voltage and the lower voltage of the DC bus are balanced.

[0083] The above process is the same as the implementation manner of the first embodiment, and will not be described in detail here.

[0084] The above describes the specific embodiments of the present application in conjunction with the drawings, but is not a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications or variations made by those skilled in the art on the basis of the technical solutions of the present application without creative labor are still within the scope of protection of the present application.

Claims

1. A DC bus voltage equalization circuit, characterized in that, include: A capacitor voltage divider circuit is used to convert a single power supply into positive and negative power supplies. The capacitor voltage divider circuit outputs the upper voltage and lower voltage of the DC bus. The first adder has the inputs being the upper and lower voltages of the DC bus. The output of the first adder is connected in sequence to a proportional circuit and an integral-derivative circuit. The output of the integral-derivative circuit is connected to the first input terminal of the second adder, and the second input terminal of the second adder is connected to zero potential. The output of the second adder is connected to the first input of the comparator, and the second output of the comparator is connected to the set AC voltage. The output of the comparator is pulled up, and the resulting output signal is passed through the signal positive setting device and the signal negative setting device respectively to control the voltage balance of the DC bus. The capacitor voltage divider circuit includes: A first IGBT is connected to a signal positive inversion device, and a second IGBT is connected to a signal negative inversion device. The first IGBT and the second IGBT are connected in series to form a first series branch. Capacitors C1 and C2 are connected in series to form a second series branch. The first series branch and the second series branch are connected in parallel. An inductor L1 and a resistor R1 are connected in series between the first IGBT and the second IGBT and between capacitors C1 and C2. A resistor R6 is connected in parallel across the two ends of the inductor L1.

2. The DC bus voltage equalization circuit as described in claim 1, characterized in that, The obtained output signals are passed through a signal forwarding device and a signal reverser device, respectively, to control the on / off state of the first IGBT and the second IGBT. When the first IGBT is turned on and the second IGBT is turned off, the voltage difference between the upper and lower DC bus charges capacitor C2, and capacitor C1 discharges through resistors R1 and R6 and inductor L1. When the second IGBT is turned on and the first IGBT is turned off, the voltage difference between the upper and lower DC bus charges capacitor C1, and capacitor C2 discharges through resistors R1 and R6 and inductor L1.

3. The DC bus voltage equalization circuit as described in claim 1, characterized in that, When the voltage on the DC bus increases, the duty cycle of the output signal increases, the turn-on time of the first IGBT increases, and the turn-on time of the second IGBT decreases; the charging time of capacitor C2 becomes longer, the charging time of capacitor C1 becomes shorter, the voltage difference across capacitor C2 becomes larger, and the voltage difference across capacitor C1 becomes smaller, which causes the voltage on the DC bus to decrease and the voltage on the lower bus to increase, thus achieving a balance between the voltage on the DC bus and the voltage on the lower bus.

4. A DC bus voltage equalization circuit as described in claim 1, characterized in that, When the lower voltage of the DC bus increases, the duty cycle of the output signal increases, the turn-on time of the second IGBT increases, and the turn-on time of the first IGBT decreases; the charging time of capacitor C1 becomes longer, the charging time of capacitor C2 becomes shorter, the voltage difference across capacitor C1 becomes larger, and the voltage difference across capacitor C2 becomes smaller, which causes the lower voltage of the DC bus to decrease and the upper voltage to increase, thus achieving a balance between the upper and lower voltages of the DC bus.

5. A DC bus voltage equalization control method, characterized in that, include: The upper and lower voltages of the DC bus output by the capacitor voltage divider circuit are input to the first adder. After passing through the proportional and integral-differential stages, the output is input to the second adder and added to the zero potential to obtain the signal UD1. The obtained signal UD1 is compared with the set AC voltage UTR, and the voltage UTR or -UTR is output based on the magnitude of the two; thus, the PWM signal UD2 with the set duty cycle is obtained; Pull signal UD2 up to obtain signal UD3; Signal UD3 controls the upper and lower voltages of the DC bus by passing the voltage positive and voltage negative states respectively, so that the upper and lower voltages of the DC bus are balanced. The capacitor voltage divider circuit includes: A first IGBT is connected to a signal positive inversion device, and a second IGBT is connected to a signal negative inversion device. The first IGBT and the second IGBT are connected in series to form a first series branch. Capacitors C1 and C2 are connected in series to form a second series branch. The first series branch and the second series branch are connected in parallel. An inductor L1 and a resistor R1 are connected in series between the first IGBT and the second IGBT and between capacitors C1 and C2. A resistor R6 is connected in parallel across the two ends of the inductor L1.

6. The DC bus voltage equalization control method as described in claim 5, characterized in that, Signal UD3 is positively charged and the signal remains unchanged, which is used to control the on / off state of the first IGBT; Signal UD3 is inverted by voltage and signal inversion, and is used to control the on / off state of the second IGBT; When the first IGBT is turned on and the second IGBT is turned off, the voltage difference between the upper and lower parts of the DC bus charges capacitor C2 and discharges capacitor C1. When the second IGBT is turned on and the first IGBT is turned off, the voltage difference between the upper and lower DC bus charges capacitor C1 and discharges capacitor C2.

7. The DC bus voltage equalization control method as described in claim 6, characterized in that, When the DC bus voltage and the DC bus voltage are balanced, a PWM signal with a duty cycle of 50% is obtained; the first IGBT and the second IGBT have the same turn-on time.

8. The DC bus voltage equalization control method as described in claim 6, characterized in that, When the voltage on the DC bus increases, the duty cycle of the output signal increases, the turn-on time of the first IGBT increases, and the turn-on time of the second IGBT decreases; the charging time of capacitor C2 becomes longer, the charging time of capacitor C1 becomes shorter, the voltage difference across capacitor C2 becomes larger, and the voltage difference across capacitor C1 becomes smaller, which causes the voltage on the DC bus to decrease and the voltage on the lower bus to increase, thus achieving a balance between the voltage on the DC bus and the voltage on the lower bus.

9. The DC bus voltage equalization control method as described in claim 6, characterized in that, When the lower voltage of the DC bus increases, the duty cycle of the output signal increases, the turn-on time of the second IGBT increases, and the turn-on time of the first IGBT decreases; the charging time of capacitor C1 becomes longer, the charging time of capacitor C2 becomes shorter, the voltage difference across capacitor C1 becomes larger, and the voltage difference across capacitor C2 becomes smaller, which causes the lower voltage of the DC bus to decrease and the upper voltage to increase, thus achieving a balance between the upper and lower voltages of the DC bus.

Images