A two-stage successive approximation analog-to-digital converter based on a differential difference amplifier

Abstract

The present invention discloses a two-stage successive approximation analog-to-digital converter based on a differential difference amplifier, which includes a first-stage sub-ADC, a differential difference amplifier, and a second-stage sub-ADC connected in sequence. Both the first-stage sub-ADC and the second-stage sub-ADC are composed of a capacitor array and a comparator. The differential difference amplifier is composed of a transconductance amplifier GM1, a transconductance amplifier GM2, a resistor load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistor load R, and the transconductance amplifier GM2 form a negative feedback loop. Among them, the proportional resistors R1 and R2 are used to adjust the gain of the amplifier. This application introduces a differential difference amplifier as a residual amplifier to form a two-stage SAR ADC architecture. By using this architecture, the offset voltage can be eliminated through one-time calibration, and a stable gain can be provided by forming a negative feedback through a resistor network, enabling higher conversion accuracy.

Description

Technical Field

[0001] The present invention relates to the field of analog-to-digital converters, and in particular to a two-stage successive approximation analog-to-digital converter based on a differential difference amplifier. Background Art

[0002] Traditional single-stage successive approximation analog-to-digital converters (SAR ADCs) rely on capacitive digital-to-analog converters (CDACs) to generate residual voltages and use comparators to judge the polarity of the residual voltages. As the accuracy increases, the total capacitance of the analog-to-digital converter shows exponential growth, and the residual voltage is also reduced to sub-millivolts. The resolution is greatly affected by capacitance mismatch and comparator noise. To achieve higher-precision analog-to-digital converters, multi-stage SAR ADCs have been proposed. Different from the single-stage structure, the accuracy of multi-stage SAR ADCs is mainly limited by the gain error and offset voltage of the residue amplifier (RA). Summary of the Invention

[0003] Object of the Invention: In order to overcome the deficiencies in the prior art, the present invention provides a two-stage successive approximation analog-to-digital converter based on a differential difference amplifier. By introducing a differential difference amplifier as a residue amplifier to form a two-stage SAR ADC architecture, this architecture eliminates the offset voltage through one-time calibration and provides stable gain through a resistor network to achieve higher conversion accuracy.

[0004] Technical Solution: To achieve the above object, a two-stage successive approximation analog-to-digital converter based on a differential difference amplifier of the present invention includes a first-stage sub-ADC, a differential difference amplifier, and a second-stage sub-ADC connected in sequence. Both the first-stage sub-ADC and the second-stage sub-ADC are composed of a capacitor array and a comparator; it further includes a calibration circuit and a digital logic control circuit. The calibration circuit is used to calibrate the offset voltages of each amplifier and comparator at one time; the digital logic control circuit is used to control the working timing of the two sub-ADCs;

[0005] The differential difference amplifier is composed of a transconductance amplifier GM1, a transconductance amplifier GM2, a resistor load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistor load R, and the transconductance amplifier GM2 form a negative feedback loop; wherein, the proportional resistors R1 and R2 are used to adjust the gain of the amplifier;

[0006] The specific working steps based on the above architecture are as follows:

[0007] Step I, switch S1 is closed, and the signal voltage is stored in the capacitor array of the first-stage sub-ADC;

[0008] Step II: Switch S1 is disconnected, and the capacitor array of the first-stage sub-ADC will flip in sequence. The charges stored in the capacitor array will be redistributed, and the differential pressure at the input of the transconductance amplifier GM1 will gradually decrease.

[0009] Step III: When the flipping of the last pair of capacitors in the capacitor array of the first-stage sub-ADC is completed, switch S2 is closed, and the capacitor array of the second-stage sub-ADC will store the voltage output by the residue amplifier.

[0010] Step IV: Switch S2 is disconnected, and the capacitor array of the second-stage sub-ADC will flip in sequence, redistribute charges, and reduce the differential pressure.

[0011] Step V: Integrate the flipping conditions of the capacitor arrays of the first-stage sub-ADC and the second-stage sub-ADC, and output the finally quantized signal.

[0012] Furthermore, the working process of the two-stage successive approximation analog-to-digital converter based on the differential difference amplifier is as follows: First, the differential input signal is roughly digitized by the first-stage sub-ADC to generate a residual voltage, then the residual voltage is amplified by the differential difference amplifier, and then further digitized by the second-stage sub-ADC. Finally, the outputs of the two sub-ADCs are corrected and combined in the output circuit to generate a 16-bit digital output.

[0013] Furthermore, the specific working process of the differential difference amplifier is as follows: First, the residual voltage generated by the first-stage sub-ADC becomes a current signal Ii after passing through the transconductance amplifier GM1 P , and then the current signal Ii P outputs a voltage signal Vo after passing through the resistor load R; finally, after the voltage division of Vo by the proportional resistors R1 and R2, it is used as the input of the transconductance amplifier GM2, and Ii N is used to adjust the current passing through the resistor load, thereby adjusting the output voltage Vo.

[0014] Furthermore, the output currents of the transconductance amplifier GM1 and the transconductance amplifier GM2 are respectively:

[0015] Ii P = G m1 · (Vi p - + Vi N )

[0016]

[0017] where G m1 and G m2 respectively represent the transconductance values of the transconductance amplifier GM1 and the transconductance amplifier GM2.

[0018] Furthermore, the output voltage of the differential difference amplifier is:

[0019] Vo = R·(Ii P + Ii N )

[0020] Furthermore, the gain of the differential difference amplifier is:

[0021]

[0022] When 1 / G m1 = 1 / G m2 << R, the above formula can be simplified to:

[0023]

[0024] By adjusting the resistance ratio of R1 and R2, the gain of the amplifier can be flexibly adjusted.

[0025] Advantageous effects: A two-stage successive approximation analog-to-digital converter based on a differential difference amplifier of the present invention has at least the following advantages:

[0026] 1. By introducing a differential difference amplifier as a residual amplifier to form a two-stage SAR ADC architecture, the gain error is effectively reduced, and the accuracy of the analog-to-digital converter is improved.

[0027] 2. Compared with the traditional closed-loop amplifier structure based on capacitive feedback, it has a smaller area and lower cost.

[0028] 3. Compared with the closed-loop amplifier structure based on resistive feedback, there is no need to add a buffer stage, and charge leakage will not occur.

[0029] 4. Compared with the structure based on an open-loop G M -R amplifier, this scheme has more stable performance and can achieve higher conversion accuracy. Description of the Drawings

[0030] Att Figure 1 is a schematic diagram of an analog-to-digital converter circuit based on a differential difference amplifier;

[0031] Att Figure 2 is a structural diagram of the analog-to-digital converter architecture proposed in this application;

[0032] Att Figure 3 is a structural diagram of an existing residual amplifier structure;

[0033] Att Figure 4 is a circuit structural diagram based on a differential difference amplifier. Detailed Embodiments

[0034] The present invention will be further described below with reference to the accompanying drawings.

[0035] As attached Figure 1 A two-stage successive approximation analog-to-digital converter based on a differential difference amplifier, comprising a first-stage sub-ADC, a differential difference amplifier, and a second-stage sub-ADC connected in sequence. Both the first-stage sub-ADC and the second-stage sub-ADC are composed of a capacitor array and a comparator; it also includes a calibration circuit and a digital logic control circuit. The calibration circuit is used to calibrate the offset voltages of each amplifier and comparator at one time; the digital logic control circuit is used to control the working timing of the two sub-ADCs;

[0036] Similar to the traditional architecture, the analog-to-digital converter proposed in this application is as attached Figure 2 shown, including two sub-ADCs STGADC1 and STGADC2, a residual amplifier, a digital logic control circuit, and a calibration circuit; in order to achieve the purpose of low noise and high linearity, STGADC1 generally uses a large area and high power. On the premise of maintaining the necessary resolution, STGADC2 minimizes the area cost and capacitive load of the residual amplifier;

[0037] As attached Figure 3 shown, the existing residual amplifier structures mainly include a closed-loop amplifier based on capacitive feedback, a closed-loop amplifier based on resistive feedback, and an open-loop amplifier based on G M -R. Most two-stage SAR ADCs use a closed-loop amplifier based on capacitive feedback as the residual amplifier. Although it can achieve a constant gain, the on-chip area is large and the cost is high. The residual amplifier of a two-stage SAR ADC can also be implemented using a closed-loop amplifier based on resistive feedback. However, since the input of the residual amplifier is connected to the capacitor top plate of the digital-to-analog converter (DAC) in the first-stage sub-ADC, the charge stored in the DAC will leak along the resistive feedback network. Therefore, when applying this structure, an additional buffer stage often needs to be added. Based on G M -R open-loop amplifier avoids charge leakage by connecting the output of the digital-to-analog converter to the MOS gate, but its stability is not as good as that of the closed-loop amplifier.

[0038] The residual amplifier structure adopted in this application is implemented based on a differential difference amplifier circuit; the working process of the two-stage successive approximation analog-to-digital converter based on a differential difference amplifier: first, the differential input signal is roughly digitized by the first-stage sub-ADC to generate a residual voltage, then the residual voltage is amplified by the differential difference amplifier, and then further digitized by the second-stage sub-ADC. Finally, the outputs of the two sub-ADCs are corrected and combined in the output circuit to generate a 16-bit digital output.

[0039] As attached Figure 4As shown, the differential difference amplifier consists of a transconductance amplifier GM1, a transconductance amplifier GM2, a resistive load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistive load R, and the transconductance amplifier GM2 form a negative feedback loop. Among them, the proportional resistors R1 and R2 are used to adjust the gain of the amplifier.

[0040] The capacitor array of the first-stage sub-ADC, the transconductance amplifier GM1, the resistive load R, and the capacitor array of the second-stage sub-ADC are connected in series in turn. A switch S1 is set at the input end of the capacitor array of the first-stage sub-ADC, and a switch S2 is set at the input end of the capacitor array of the second-stage sub-ADC. The proportional resistors R1 and R2 are connected in series in the signal grounding line of the resistive load R. The voltage signal input of the transconductance amplifier GM2 is connected to the voltage across either end of the proportional resistors R1 and R2, and the current signal output of the transconductance amplifier GM2 is connected to the resistive load R.

[0041] The specific working process of the differential difference amplifier is as follows: First, the residual voltage generated by the first-stage sub-ADC becomes a current signal Ii after passing through the transconductance amplifier GM1. P , and then the current signal Ii P outputs a voltage signal Vo after passing through the resistive load R. Finally, after the voltage division of Vo by the proportional resistors R1 and R2, it is used as the input of the transconductance amplifier GM2 to output Ii N to adjust the current passing through the resistive load, thereby adjusting the output voltage Vo.

[0042] The output currents of the transconductance amplifier GM1 and the transconductance amplifier GM2 are respectively:

[0043] Ii P = G m1 · (Vi p + Vi N )

[0044]

[0045] Among them, G m1 and G m2 respectively represent the transconductance values of the transconductance amplifier GM1 and the transconductance amplifier GM2.

[0046] The output voltage of the differential difference amplifier is:

[0047] Vo = R · (Ii P + Ii N )

[0048] The gain of the differential difference amplifier is:

[0049]

[0050] When 1 / G m1 = 1 / G m2 <<R, the above formula can be simplified to:

[0051]

[0052] By adjusting the resistance ratio of R1 and R2, the gain of the amplifier can be flexibly adjusted.

[0053] The specific working steps based on the above architecture are as follows:

[0054] Step Ⅰ, switch S1 is closed, and the signal voltage is stored in the capacitor array of the first-stage sub-ADC;

[0055] Step Ⅱ, switch S1 is opened, the capacitor array of the first-stage sub-ADC will be flipped in sequence, the charges stored in the capacitor array will be redistributed, and the pressure difference at the input end of the transconductance amplifier GM1 will gradually decrease;

[0056] Step Ⅲ, when the flipping of the last pair of capacitors in the capacitor array of the first-stage sub-ADC is completed, switch S2 is closed, and the capacitor array of the second-stage sub-ADC will store the voltage output by the residue amplifier;

[0057] Step Ⅳ, switch S2 is opened, the capacitor array of the second-stage sub-ADC will be flipped in sequence, redistribute charges, and reduce the pressure difference;

[0058] Step Ⅴ, integrate the flipping conditions of the capacitor arrays of the first-stage sub-ADC and the second-stage sub-ADC, and output the finally quantized signal.

[0059] The above description is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the above principles of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A two-stage successive approximation analog-to-digital converter based on a differential difference amplifier, comprising a first-stage sub-ADC, a differential difference amplifier, and a second-stage sub-ADC connected in sequence. Both the first-stage sub-ADC and the second-stage sub-ADC are composed of a capacitor array and a comparator. It further includes a calibration circuit and a digital logic control circuit. The calibration circuit is used to calibrate the offset voltages of each amplifier and comparator at one time. The digital logic control circuit is used to control the working timing of the two sub-ADCs. The differential difference amplifier consists of a transconductance amplifier GM1, a transconductance amplifier GM2, a resistive load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistive load R, and the transconductance amplifier GM2 form a negative feedback loop. Among them, The proportional resistors R1 and R2 are used to adjust the gain of the amplifier. The specific working steps of the above analog-to-digital converter are as follows: Step I, switch S1 is closed, and the signal voltage is stored in the capacitor array of the first-stage sub-ADC. Step II, switch S1 is opened, and the capacitor array of the first-stage sub-ADC will be flipped in sequence. The charge stored in the capacitor array will be redistributed, and the pressure difference at the input end of the transconductance amplifier GM1 will gradually decrease. Step III, when the flipping of the last pair of capacitors in the capacitor array of the first-stage sub-ADC is completed, switch S2 is closed, and the capacitor array of the second-stage sub-ADC will store the voltage output by the differential difference amplifier. Step IV, switch S2 is opened, and the capacitor array of the second-stage sub-ADC will be flipped in sequence to redistribute the charge and reduce the pressure difference. Step V, integrate the flipping conditions of the capacitor arrays of the first-stage sub-ADC and the second-stage sub-ADC, and output the finally quantized signal.

2. The second-order successive approximation analog-to-digital converter based on a differential difference amplifier according to claim 1, wherein, The working process of the two-stage successive approximation analog-to-digital converter based on the differential difference amplifier: First, the differential input signal is roughly digitized by the first-stage sub-ADC to generate a residual voltage. Then, the residual voltage is amplified by the differential difference amplifier. Next, it is further digitized by the second-stage sub-ADC. Finally, the outputs of the two sub-ADCs are corrected and combined in the output circuit to generate a 16-bit digital output.

3. The second-order successive approximation analog-to-digital converter based on a differential difference amplifier according to claim 2, characterized in that, The specific working process of the differential difference amplifier is as follows: First, the residual voltage generated by the first-stage sub-ADC becomes a current signal Ii after passing through the transconductance amplifier GM1 P , and then the current signal Ii P outputs a voltage signal Vo after passing through the resistor load R; finally, Vo is divided by the proportional resistors R1 and R2 and used as the input of the transconductance amplifier GM2 to output Ii N to adjust the current passing through the resistor load, thereby adjusting the output voltage Vo.

4. A second-order successive approximation analog-to-digital converter based on a differential difference amplifier according to claim 3, characterized in that, The output currents of the transconductance amplifier GM1 and the transconductance amplifier GM2 are respectively: Ii P = G m1 ·(Vi P - Vi N ) Among them, G m1 and G m2 represent the transconductance values of the transconductance amplifiers GM1 and GM2, respectively.

5. The second-stage successive approximation analog-to-digital converter based on a differential difference amplifier according to claim 4, wherein The output voltage of the differential difference amplifier is: Vo = R·(Ii P + Ii N )。 6. The second-order successive approximation analog-to-digital converter based on a differential difference amplifier according to claim 5, characterized in that, The gain of the differential difference amplifier is: When 1 / G m1 = 1 / G m2 <<R, the above equation can be simplified to: By adjusting the resistance ratio of R1 and R2, the gain of the amplifier can be flexibly adjusted.

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