Wafer process yield analysis method, device and system

Abstract

The application discloses a wafer processing yield analysis method, device and system, which is used for quickly determining the cause of generating defective semiconductor products, thereby improving the promotion speed of the semiconductor product yield. The wafer processing yield analysis method provided by the application comprises the following steps: determining at least one failure type of a defective wafer batch, and determining a plurality of defective semiconductor products corresponding to each failure type; for each failure type, using the processing history records of the plurality of defective semiconductor products corresponding to the failure type to determine the mixed processing of the plurality of defective semiconductor products; wherein the mixed processing comprises the combination of at least two processes; and generating the cause information of the defective semiconductor products of the failure type according to the mixed processing of the plurality of defective semiconductor products.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a wafer process yield analysis method, device and system. BACKGROUND

[0002] Regarding the yield problem of semiconductor products, it is necessary to analyze and confirm the yield problem through electrical failure analysis, physical failure analysis, related possible process inference, machine operation history record query, etc. It takes a week or several weeks, months to find the key of the problem, which wastes manpower, material resources and time cost. And the advanced DRAM process has more than a thousand processes, which consumes a lot of time and manpower, and seriously delays the improvement speed of the yield of semiconductor products. SUMMARY

[0003] The embodiments of the present application provide a wafer process yield analysis method, device and system to quickly determine the cause of the defective semiconductor products, thereby improving the improvement speed of the yield of semiconductor products.

[0004] The wafer process yield analysis method provided by the embodiments of the present application comprises:

[0005] determining at least one failure type of the defective wafer batch, and determining a plurality of defective semiconductor products corresponding to each failure type;

[0006] for each failure type, determining a mixed process of the plurality of defective semiconductor products by using the process history record of the plurality of defective semiconductor products corresponding to the failure type; wherein the mixed process comprises a combination of at least two processes; and generating the cause information of the defective semiconductor products of the failure type according to the mixed process of the plurality of defective semiconductor products.

[0007] Through the method, at least one failure type of the defective semiconductor products is determined, and a plurality of defective semiconductor products corresponding to each failure type is determined. For each failure type, the mixed process of the plurality of defective semiconductor products is determined by using the process history record of the plurality of defective semiconductor products corresponding to the failure type. The mixed process comprises a combination of at least two processes. And the cause information of the defective semiconductor products of the failure type is generated according to the mixed process of the plurality of defective semiconductor products. Thus, for any failure type, the cause of the defective semiconductor products of the failure type can be quickly determined, and the improvement speed of the yield of semiconductor products can be improved.

[0008] In some embodiments, for each failure type, the cause information of the defective semiconductor products of the failure type is generated according to the mixed process of the plurality of defective semiconductor products, comprising:

[0009] For each failure type:

[0010] For any mixed process corresponding to any defective semiconductor product under the failure type, a score of the mixed process is determined according to a preset weight corresponding to a process in the mixed process.

[0011] According to the scores of the mixed processes of the plurality of defective semiconductor products, generating the cause information of the defective semiconductor products of the failure type.

[0012] In some embodiments, when there are different defective semiconductor products corresponding to the same mixed process, a common score is determined for the same mixed process corresponding to the different defective semiconductor products.

[0013] In some embodiments, the mixed process of any of the defective semiconductor products includes a first process and a second process for preparing the defective semiconductor product, wherein the first process is a preceding process of the second process.

[0014] In some embodiments, for each failure type, for any mixed process corresponding to any defective semiconductor product under the failure type, a score of the mixed process is determined using a weight corresponding to a first process in the mixed process.

[0015] In some embodiments, the weights are preset according to different failure types and / or different categories of processes.

[0016] In some embodiments, the preset weights of the same category of processes corresponding to the same failure type are the same.

[0017] In some embodiments, for each failure type, according to the scores of the mixed processes of the plurality of defective semiconductor products, generating the cause information of the defective semiconductor products of the failure type, includes:

[0018] For each failure type, the scores of the mixed processes of the plurality of defective semiconductor products are sorted from high to low, and the information of the mixed process with the highest score is taken as the cause information of the defective semiconductor products of the failure type.

[0019] In some embodiments, the method further includes:

[0020] Generating indication information for adjusting the semiconductor production equipment corresponding to the mixed process with the highest score, and / or indication information for adjusting the mixed process with the highest score.

[0021] In some embodiments, the method further includes:

[0022] a semiconductor product on which the highest-scored hybrid process has been performed is marked;

[0023] when performing yield test on a semiconductor product, for a defective semiconductor product on which the mark exists, information of the highest-scored hybrid process is provided as cause information of the defective semiconductor product on which the mark exists.

[0024] In some embodiments, the process history record includes process history records of the same machine or process history records of multiple machines.

[0025] The cause information includes hybrid process information and / or machine information corresponding to the hybrid process.

[0026] Another embodiment of the present application provides a computing device including a memory and a processor, wherein the memory is configured to store program instructions, and the processor is configured to invoke the program instructions stored in the memory to perform any of the above methods.

[0027] Another embodiment of the present application provides a wafer process yield analysis system including the computing device.

[0028] In addition, according to an embodiment, for example, a computer program product for a computer is provided, which includes software code portions for performing the steps of the above-defined method when the product is run on the computer. The computer program product can include a computer-readable medium on which the software code portions are stored. In addition, the computer program product can be loaded into the internal memory of the computer directly via a plurality of network, and / or sent by an upload process, a download process and a push process.

[0029] Another embodiment of the present application provides a computer-readable storage medium, which stores computer-executable instructions for causing a computer to perform any of the above methods. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0031] Figure 1 A flowchart of a wafer process yield analysis method provided by an embodiment of the present application is shown in FIG. 1;

[0032] Figure 2A DRAM process diagram provided by the embodiment of the present application;

[0033] Figure 3 A weight setting diagram of the process provided by the embodiment of the present application;

[0034] Figure 4 A mixed process record diagram of the defective product provided by the embodiment of the present application;

[0035] Figure 5 A score result statistical ordering diagram of the mixed process provided by the embodiment of the present application;

[0036] Figure 6 A product marking diagram provided by the embodiment of the present application;

[0037] Figure 7 A diagram of the product with the mark for yield test provided by the embodiment of the present application;

[0038] Figure 8 A wafer group level mixed process record diagram provided by the embodiment of the present application;

[0039] Figure 9 A wafer level mixed process record diagram provided by the embodiment of the present application;

[0040] Figure 10 Another wafer group level mixed process record diagram provided by the embodiment of the present application;

[0041] Figure 11 A structure diagram of a wafer process yield analysis device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0043] The embodiment of the present application provides a wafer process yield analysis method, device and system, which can quickly determine the cause of the defective semiconductor product, thereby improving the speed of improving the yield of the semiconductor product.

[0044] The method, device and system are based on the same application concept. Since the principles of the method, device and system for solving problems are similar, the implementation of the device, system and method can be mutually referred to, and the repeated parts will not be described again.

[0045] The terms "first", "second", etc. (if any) in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0046] The following examples and embodiments will only be understood as illustrative examples. Although the present specification can refer to "a", "an" or "some" example or embodiment at several places, this does not mean that each such reference relates to the same example or embodiment, nor that this feature only applies to a single example or embodiment. Individual features of different embodiments can also be combined to provide other embodiments. In addition, terms such as "include" and "contain" should be understood as not limiting the described embodiments to only those features mentioned; such examples and embodiments can also include features, structures, units, modules, etc. not specifically mentioned.

[0047] The various embodiments of the present application are described in detail below in conjunction with the accompanying drawings of the specification. It should be noted that the order of presentation of the embodiments of the present application only represents the order of the embodiments and does not represent the superiority or inferiority of the technical solutions provided by the embodiments.

[0048] Regarding the yield problem of semiconductor manufacturing, many are caused by single machine problems, but there are exceptions that cannot be found by using the common machine query system. In some cases of semiconductor product yield, it is found that the previous process of the machine will affect the following process, therefore, in the embodiments of the present application, the commonality of the combination of the previous and subsequent processes (such as the combination of process A followed by process B) is judged and detected by using data records, and the yield problem caused by which kind of machine and which kind of mixed process is queried.

[0049] In the embodiments of the present application, the cause of the yield problem in semiconductor product manufacturing is determined, and the yield loss of the semiconductor product caused by the problem from a single machine or multiple machines can be solved by querying the records of the mixed process of the machine (including at least two processes, which can be performed by the same machine or by multiple machines), to determine which special process combination causes the defective semiconductor product, thereby solving the difficult-to-solve low yield problem of the semiconductor product.

[0050] Referring toFigure 1 The wafer process yield analysis method provided by the embodiments of the present application comprises the following steps.

[0051] S101, determining at least one failure type of a defective semiconductor product, and determining a plurality of defective semiconductor products corresponding to each failure type;

[0052] S102, for each failure type, determining a mixed process of the plurality of defective semiconductor products by using the process history records of the plurality of defective semiconductor products corresponding to the failure type; wherein the mixed process comprises a combination of at least two processes; and generating the cause information of the defective semiconductor products of the failure type according to the mixed process of the plurality of defective semiconductor products.

[0053] For example, first, a list of defective semiconductor products (lot, wafer) is determined, and a failure type classification is performed, a list of defective semiconductor products corresponding to each failure type is determined, and for the list of defective semiconductor products of each failure type, a corresponding mixed process record is generated, wherein the mixed process record can be further used to find the mixed process common to the plurality of defective semiconductor products. For each failure type, the mixed process record is used to generate the cause information of the defective semiconductor products of the failure type. Subsequently, the problem of yield can be solved by prohibiting the combination of problematic mixed processes, and the occurrence of such problems can be continuously detected.

[0054] Therefore, by the method, the cause of the defective semiconductor products of any failure type can be quickly determined by using the mixed process of the plurality of defective semiconductor products determined by the process history record, and the speed of improving the yield of semiconductor products can be improved. The same mixed process can come from the same machine or from different machines.

[0055] For example, by the method, it is determined that after a previous process m is performed, the next process n will be affected, resulting in the generation of defective semiconductor products, and the machines corresponding to the processes m and n can be respectively determined to further analyze whether the problem is caused by the machine.

[0056] In some embodiments, for each failure type, the cause information of the defective semiconductor products of the failure type is generated according to the mixed process of the plurality of defective semiconductor products, comprising:

[0057] For each failure type:

[0058] For any mixed process corresponding to any defective semiconductor product under the failure type, the score of the mixed process is determined according to the preset weight corresponding to the process in the mixed process;

[0059] According to the scores of the multiple mixed processes of the multiple defective semiconductor products, the cause information of the defective semiconductor products of the failure type is generated.

[0060] Wherein, one product can correspond to multiple process combinations, for example, for defective semiconductor product lot A, it can correspond to the combination of process 1 and previous process process 2, and also correspond to the combination of process 3 and previous process process 10.

[0061] In some embodiments, when different defective semiconductor products correspond to the same mixed process, a common score is determined for the different defective semiconductor products corresponding to the same mixed process.

[0062] In some embodiments, the mixed process of any of the defective semiconductor products includes a first process and a second process for preparing the defective semiconductor product, wherein the first process is a previous process of the second process. For example, the first process and the second process for preparing defective semiconductor product lot B are process 1 and process 2, respectively.

[0063] In some embodiments, for each failure type, the score of any mixed process corresponding to any defective semiconductor product of the failure type is determined using the weight corresponding to the first process in the mixed process.

[0064] In some embodiments, the weights are pre-set according to different failure types, and / or different categories of processes.

[0065] That is, the embodiments of the present application can set corresponding weights for processes according to any one or more factors such as the failure type of the semiconductor product, the process classification, etc.

[0066] In some embodiments, the pre-set weights of the same category of processes corresponding to the same failure type are the same. For example, the pre-set weights of AA processes corresponding to failure type BL are all the same value, where the AA processes include the 1st to i th processes, such as the 1st to 30 th processes, i.e., the weights of the 1st to 30 th processes are all the same.

[0067] In some embodiments, for each failure type, the cause information of the defective semiconductor products of the failure type is generated according to the scores of the multiple mixed processes of the multiple defective semiconductor products, including:

[0068] For each failure type, the scores of the multiple mixed processes of the multiple defective semiconductor products are sorted from high to low, and the information of the mixed process with the highest score is taken as the cause information of the defective semiconductor products of the failure type.

[0069] In some embodiments, the method further includes:

[0070] Generate instructions to adjust the semiconductor manufacturing equipment corresponding to the highest-scoring hybrid process, and / or, instructions to adjust the highest-scoring hybrid process.

[0071] In some embodiments, the method further includes:

[0072] The semiconductor products that have undergone the highest-scoring hybrid process are marked;

[0073] When performing yield testing on semiconductor products, for defective semiconductor products with the marked defects, the information of the mixed process with the highest score is used as the cause information for the defective semiconductor product with the marked defects.

[0074] In some implementations, the process history includes the process history of the same machine or the process history of multiple machines.

[0075] The information regarding the cause of the occurrence includes hybrid process information and / or machine information corresponding to the hybrid process.

[0076] This allows us to identify which type of machine and which hybrid process caused the yield problem in the semiconductor products.

[0077] The following is an example of a specific embodiment.

[0078] For example, an embodiment of this application provides a wafer fabrication process yield analysis method, which includes the following steps:

[0079] Step 1: Comprehensive analysis of DRAM manufacturing process and model combination.

[0080] For example: Figure 2 As shown, the etching machine can perform etching processes such as the first process, the second process, the third process, the fourth process, etc., and these processes are random. For example, the machine may perform the first etching process first, then the second process, then the third process, and so on. In practice, each machine may have 500 to 7000 possible combinations of processes. Therefore, it is necessary to first determine the possible process combinations for each machine in the entire process.

[0081] Step 2: There are many DRAM failure mechanisms, such as failure type A, failure type B, failure type C, failure type D, failure type E, and failure type F. Different process types and failure types have different weights, allowing us to determine the weight percentage of relevant processes based on the failure type and the process category. For example...Figure 3 As shown.

[0082] Different byte failure types correspond to different possible processes. As can be seen, the embodiments of the present application can use weights to exclude some completely impossible processes. Figure 3 In some embodiments, the same process can correspond to multiple sub-processes. For example, the first process can include the first process to the thirtieth process; the second process can include the thirty-first process to the seventieth process, and so on. That is, under the same failure type, multiple processes can correspond to the same weight. For example, for failure type A, the first process to the thirtieth process correspond to the same weight a1.

[0083] Step three, determine the list of defective products according to the failure type.

[0084] For example, the list of defective products under one failure type includes: Lot A, Lot B, Lot C, Lot D, and Lot E.

[0085] Step four, use the machine process history record (Launcher run sheet) to generate the process history record of the defective products, and further generate the mixed process record of the defective products. For example Figure 4 As shown, for the defective products Lot A, Lot B, Lot C, Lot D, and Lot E, the mixed process record of each process and the previous process is generated.

[0086] In addition, using the mixed process record, the previous process analysis is performed. Specifically, for example, the COUNTIF function can be used to combine the weight proportion of the previous process to calculate the score of each mixed process (i.e., process combination).

[0087] For example, referring to Figure 4 For a product of one failure type, the process for preparing the product of the failure type includes n processes. Then, the score of each mixed process (a combination of one process and its previous process) corresponding to the product of the failure type is sorted out.

[0088] In some embodiments, for the same mixed process of different semiconductor products, the same mixed process can generate a common score. For example, as shown Figure 4 For example, the pre-process of process 2 has two batches of lots (Lot B and Lot C, respectively), and before process 2, the machine performed process 1. It is assumed that processes 1-30 all belong to Figure 3As shown in the first process in the middle, the sub-process of process 1, so the weight of process 1 is a1, then the score of the mixed process (the combination of process 2 and process 1 as the previous process of process 2) is 2*a1, where 2 represents 2 batches of lot products, indicating that the machine first performs process 1 and then performs process 2. The score of this combination is 3*a1, and the higher the score, the higher the possibility of problems.

[0089] Step five, score the results of the mixed process.

[0090] The sorting result is, for example Figure 5 As shown, process n and the previous process of process n, process m, for example, process m is a sub-process under the first process, for example, process 10, so the score of this combination is the highest, that is, 5*a1 points, which means that this mixed process is most likely to cause the existence of defective products. Where n is an integer greater than 1. Of course, process m can also belong to a certain sub-process under the second process, the third process, the fourth process, etc. The score of the combination can be calculated according to the specific weight.

[0091] It should be noted that the highest scoring mixed process in the embodiments of the present application can be output as the analysis result, or the highest scoring multiple mixed processes (for example, the top three combinations) can be output as the analysis result.

[0092] Step six, draw conclusions and find the cause of the yield problem.

[0093] For example Figure 5 As shown, a certain machine will have an adverse effect on the next process n after performing process m in the previous process, causing a yield problem of producing defective products. In the subsequent production process, process n after process m can be prohibited, replaced by other processes, or the corresponding machine of process m and / or process n is replaced, etc. to solve such yield problems.

[0094] Step seven, monitor similar problems on future yield based on the conclusion.

[0095] For example, according to the above process analysis, a certain machine will have an adverse effect on the next process n after performing process m (for example, process 10 as simulated in Figure 5 ), causing such a yield problem. After such a combination, the lot is marked, as shown in Figure 6 When these lots are tested for yield, if the same defective product problem occurs, it can be determined to be a known problem, and the product failure cause (information of the mixed process, machine information involved in the mixed process), failure type, etc. are generated, as shown in Figure 7 .

[0096] The following gives several specific examples.

[0097] Example 1, low yield problem of single wafer, for example, 1 lot (wafer group), there are 25 pieces of wafer, only 1 piece of low yield, that is, only 1 piece of wafer is defective product.

[0098] Then the method in this embodiment includes:

[0099] Step 1, determine the bad product (Bad lot / bad wafer).

[0100] For each wafer group, the bad wafer is single and random, and it is not fixed which wafer has the problem.

[0101] Through physical failure analysis (PFA), it is determined that there is a problem of bit line and bit line short circuit.

[0102] Step 2, sort the process history record of the bad wafer group.

[0103] Step 3, system analysis of the front process:

[0104] This embodiment has PFA results, which can lock the bit line related process according to the PFA results.

[0105] Step 4, perform score statistics and sorting.

[0106] For example, in this embodiment, the mixed process score statistics and sorting are performed for the bad wafer group and the bad wafer respectively. Moreover, the mixed process score of the wafer group level is the highest, which is 3 points.

[0107] For example, Figure 8 The mixed process record of the wafer group level is shown. The first table shows that the machine 101 first performs the first process on lot G, and then immediately performs the second process on lot A on the 101 machine. Figure 8 The mixed process of other products is the same, which will not be repeated.

[0108] For example, Figure 9 The mixed process record of the wafer level is shown. The first table shows that the machine cavity 101G first performs the third process on wafer G, and then immediately performs the second process on wafer A on the 101A cavity. Figure 9 The mixed process of other products is the same, which will not be repeated.

[0109] Step 5, get the conclusion and find the cause of the yield problem.

[0110] In this step, it is found that the machine performs the third process before the second process of the defective product.

[0111] Embodiment two,

[0112] This embodiment assumes that the cause determination method for failure type C includes the following steps:

[0113] Step one, determine the bad lot / bad wafer.

[0114] For example, the first six or the first four wafers in a wafer group are bad.

[0115] Step two, organize the process history records of the bad wafer group.

[0116] Step three, the system performs front-end process analysis.

[0117] This embodiment has PFA that cannot be cut, i.e., no result of physical property failure analysis, and the actual physical property failure analysis cannot be found.

[0118] Step four, perform fraction statistics sorting of mixed processes.

[0119] For example, the mixed process records of the bad wafer group in this embodiment are shown in Table 1. Figure 10 The first table shows that the lot G is used in the fourth process on the machine 104, and then the lot A is used in the fifth process on the machine 104. Figure 10 The mixed processes of other products are the same as described above, and will not be described again.

[0120] Step five, draw conclusions and find the cause of the yield problem.

[0121] This embodiment finds that after a certain machine model performs the fourth process, the fifth process is performed, which causes the problem of failure type C.

[0122] Therefore, for example, the fifth process can be performed separately on a machine, and not mixed with other processes, to solve this problem.

[0123] The following describes the device or apparatus provided by the embodiments of the present application, and the explanations or examples of the same or corresponding technical features described in the above method will not be described again.

[0124] Referring to Figure 11 Another embodiment of the present application provides a computing device, which includes:

[0125] The processor 600 is configured to read the program in the memory 620 and perform the following processes:

[0126] Determine at least one failure type of the defective wafer batch, and determine a plurality of defective semiconductor products corresponding to each failure type.

[0127] For each failure type, a mixed process of the plurality of defective semiconductor products is determined by using process history records of the plurality of defective semiconductor products corresponding to the failure type, wherein the mixed process comprises a combination of at least two processes; and generation cause information of the defective semiconductor products of the failure type is generated according to the mixed process of the plurality of defective semiconductor products.

[0128] In some embodiments, for each failure type, generating the generation cause information of the defective semiconductor products of the failure type according to the mixed process of the plurality of defective semiconductor products comprises:

[0129] For each failure type:

[0130] For any mixed process corresponding to any defective semiconductor product under the failure type, a score of the mixed process is determined according to a preset weight corresponding to a process in the mixed process;

[0131] The generation cause information of the defective semiconductor products of the failure type is generated according to the scores of the mixed processes of the plurality of defective semiconductor products.

[0132] In some embodiments, when there are different defective semiconductor products corresponding to the same mixed process, a common score is determined for the same mixed process corresponding to the different defective semiconductor products.

[0133] In some embodiments, the mixed process of any defective semiconductor product comprises a first process and a second process which are continuous in preparing the defective semiconductor product, wherein the first process is a preceding process of the second process.

[0134] In some embodiments, for each failure type, for any mixed process corresponding to any defective semiconductor product under the failure type, a score of the mixed process is determined by using a weight corresponding to a first process in the mixed process.

[0135] In some embodiments, the weights are preset according to different failure types, and / or different categories of processes.

[0136] In some embodiments, the preset weights of the same category of processes corresponding to the same failure type are the same.

[0137] In some embodiments, for each failure type, the generation cause information of the defective semiconductor products of the failure type is generated according to the scores of the mixed processes of the plurality of defective semiconductor products, comprising:

[0138] For each failure type, scores of the plurality of mixed processes of the plurality of defective semiconductor products are sorted from high to low, and information of a mixed process with the highest score is taken as the cause information of the defective semiconductor product of the failure type.

[0139] In some embodiments, the processor 600 is further configured to read a program in the memory 620 and perform the following processes:

[0140] Generate instruction information for adjusting the semiconductor production equipment corresponding to the mixed process with the highest score, and / or instruction information for adjusting the mixed process with the highest score.

[0141] In some embodiments, the processor 600 is further configured to read a program in the memory 620 and perform the following processes:

[0142] Set a mark on the semiconductor product that has undergone the mixed process with the highest score;

[0143] When performing yield testing on the semiconductor product, for the defective semiconductor product with the mark, take the information of the mixed process with the highest score as the cause information of the defective semiconductor product with the mark.

[0144] In some embodiments, the computing device further includes a transceiver 610 for receiving and sending data under the control of the processor 600.

[0145] Wherein, in Figure 11 The bus architecture can include any number of interconnected buses and bridges, which are collectively represented by the processor 600 and the various circuits of the memory 620 linked together by the processor 600. The bus architecture can also link various other circuits such as peripheral devices, voltage regulators and power management circuits, which are well known in the art, and therefore, will not be further described herein. The bus interface provides an interface. The transceiver 610 can be a plurality of elements, i.e., including a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium.

[0146] In some embodiments, the computing device further includes a user interface 630, which can be an interface that can be externally connected to the device as needed, including but not limited to a keypad, a display, a speaker, a microphone, a joystick, etc.

[0147] The processor 600 is responsible for managing the bus architecture and general processing, and the memory 620 can store data used by the processor 600 when performing operations.

[0148] In some embodiments, the processor 600 can be a CPU (Central Processor Unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a CPLD (Complex Programmable Logic Device).

[0149] The computing device provided by the embodiments of the present application can be a desktop computer, a portable computer, a smart phone, a tablet computer, a personal digital assistant (PDA), etc. The computing device can include a central processing unit (CPU), a memory, an input / output device, etc. The input device can include a keyboard, a mouse, a touch screen, etc. The output device can include a display device, such as a liquid crystal display (LCD), a cathode ray tube (CRT), etc.

[0150] The memory can include a read-only memory (ROM) and a random access memory (RAM), and provide the processor with program instructions and data stored in the memory. In the embodiments of the present application, the memory can be used to store the programs of any of the methods provided by the embodiments of the present application.

[0151] The processor calls the program instructions stored in the memory, and the processor is used to execute any of the methods provided by the embodiments of the present application according to the obtained program instructions.

[0152] Another embodiment of the present application provides a wafer process yield analysis system, which includes the computing device.

[0153] The embodiments of the present application further provide a computer program product or computer program, which comprises computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform any of the methods described in the above embodiments. The program product can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium may, for example, be but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0154] The embodiments of the present application provide a computer readable storage medium for storing computer program instructions for the apparatus provided in the above embodiments of the present application, which contains programs for executing any of the methods provided in the above embodiments of the present application. The computer readable storage medium can be a non-transitory computer readable medium.

[0155] The computer readable storage medium can be any available medium or data storage device that can be accessed by a computer, including but not limited to a magnetic storage (such as a floppy disk, a hard disk, a magnetic tape, a magneto-optical disk (MO), etc.), an optical storage (such as a CD, a DVD, a BD, a HVD, etc.), and a semiconductor storage (such as a ROM, an EPROM, an EEPROM, a non-volatile memory (NAND FLASH), a solid state disk (SSD)), etc.

[0156] It should be understood that:

[0157] The access technology via which entities in a communication network communicate traffic to and from each other can be any suitable current or future technology, such as WLAN (Wireless Local Access Network), WiMAX (Worldwide Interoperability for Microwave Access), LTE, LTE-A, 5G, Bluetooth, infrared, etc. can be used; in addition, embodiments can also apply wired technologies, for example, IP-based access technologies, such as wired networks or fixed lines.

[0158] Embodiments suitable for being implemented as software code or part of it and being run using a processor or processing functionality are independent of the software code and can be specified using any known or future developed programming language, such as a high-level programming language, such as objective-C, C, C++, C#, Java, Python, Javascript, other scripting languages, etc., or a low-level programming language, such as a machine language or assembler.

[0159] Embodiments are independent of hardware and can be implemented using any known or future developed hardware technology or any hybrid of these, such as a microprocessor or CPU (Central Processing Unit), MOS (Metal Oxide Semiconductor), CMOS (Complementary Metal-Oxide Semiconductor), BiMOS (Bipolar MOS), BiCMOS (Bipolar CMOS), ECL (Emitter Coupled Logic), and / or TTL (Transistor-Transistor Logic).

[0160] Embodiments can be implemented as a single device, apparatus, unit, component, or function, or in a distributed manner, e.g., using or sharing one or more processors or processing functionality in the processing, or using and sharing one or more processing segments or processing portions, wherein one physical processor or more than one physical processor can be used to implement one or more processing portions dedicated to a specific processing as described.

[0161] The apparatus can be implemented by a semiconductor chip, a chipset, or a (hardware) module including such chip or chipset.

[0162] Embodiments can also be implemented as any combination of hardware and software, such as an ASIC (Application Specific IC (Integrated Circuit)) component, a FPGA (Field-Programmable Gate Array) or CPLD (Complex Programmable Logic Device) component, or a DSP (Digital Signal Processor) component.

[0163] Embodiments can also be implemented as a computer program product comprising a computer-readable storage medium having stored thereon a computer readable program code which adapts a processor to carry out the processes as described in embodiments, wherein the computer-readable storage medium can be a non-transitory medium.

[0164] Those skilled in the art will appreciate that embodiments of the present application can be supplied as a method, a system, or a computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, magnetic, optical, or other storage media) embodying computer program code adapted to carry out the processes of the present application.

[0165] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or blocks of the flowcharts. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or blocks of the flowcharts.

[0166] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or blocks of the flowcharts. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or blocks of the flowcharts.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or blocks of the flowcharts. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or blocks of the flowcharts.

[0168] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method for rapidly improving yield of wafer processing, characterized in that, The method comprises: determining wafer group defective products, determining failure types of the defective products through physical property failure analysis, and determining a plurality of defective semiconductor products corresponding to each failure type; classifying the failure types, for each failure type, generating a corresponding hybrid process record using process history records of the plurality of defective semiconductor products corresponding to the failure type, the hybrid process comprising a combination of at least two processes in the process of preparing the defective semiconductor products, and any hybrid process of any wafer group defective product comprising a first process and a second process in series for preparing the wafer group defective product, wherein the first process is a preceding process of the second process; for each failure type, generating cause information of the wafer group defective products of the failure type using the hybrid process record, the cause information comprising hybrid process information and / or machine information corresponding to the hybrid process, specifically comprising: for each failure type: for any hybrid process corresponding to any defective product under the failure type, determining a score of the hybrid process according to a preset weight corresponding to the process in the hybrid process, wherein the preset weight is set in advance according to different failure types and / or different categories of processes, and the preset weight of the same category of processes corresponding to the same failure type is the same; generating cause information of the wafer group defective products of the failure type according to the scores of the plurality of hybrid processes of the defective product, the hybrid process comprising a combination of at least two processes; generating indication information for adjusting the cause of the wafer group defective products of the failure type.

2. The method of claim 1, wherein, When there are different wafer group defective products corresponding to the same hybrid process, a common score is determined for the same hybrid process corresponding to the different wafer group defective products.

3. The method of claim 1, wherein, for each failure type, for any hybrid process corresponding to any wafer group defective product under the failure type, determining a score of the hybrid process using a weight corresponding to the first process in the hybrid process.

4. The method of claim 1, wherein, According to the scores of the plurality of hybrid processes of the defective product, generating cause information of the wafer group defective products of the failure type, comprising: for each failure type, sorting the scores of the plurality of hybrid processes of the plurality of wafer group defective products from high to low, and taking information of the hybrid process with the highest score as the cause information of the wafer group defective products of the failure type.

5. The method of claim 4, wherein, The method further comprises: setting a mark for the wafer group defective product with the highest score of the hybrid process; when testing the yield of the wafer group product, for the wafer group defective product with the mark, taking the information of the hybrid process with the highest score as the cause information of the wafer group defective product with the mark.

6. The method of claim 1, wherein, The process history record comprises process history records of the same machine or process history records of a plurality of machines.

7. A computing device, comprising: comprising: a memory for storing program instructions; a processor for calling the program instructions stored in the memory to execute the method according to any one of claims 1 to 6.

8. A wafer process yield analysis system, comprising: The computing device according to claim 7. The computing device according to claim 7.

9. A computer program product for a computer, characterized in that comprising software code portions being adapted, when run on the computer, to perform the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing the computer to perform the method according to any one of claims 1 to 6.

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