Super junction mos device and method of manufacturing the same
By setting asymmetrical deep well and normal well structures in superjunction MOS devices, the equivalent resistance of parasitic transistors is reduced, UIS capability and device robustness are improved, and the problem of insufficient reliability of superjunction MOS devices in the switching process of non-clamped inductive loads is solved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI CHINA RESOURCES HUAJING MICROELECTRONICS
- Filing Date
- 2021-10-11
- Publication Date
- 2026-05-29
AI Technical Summary
Existing superjunction MOS devices have insufficient UIS capability during non-clamped inductive load switching, and the high equivalent resistance of parasitic transistors leads to insufficient device reliability.
In a superjunction MOS device, one side of the gate is a deep well with a large vertical depth, and the other side is a normal well with a shallow vertical depth, forming an asymmetrical well structure. This reduces the equivalent resistance of the parasitic transistor and transfers the high electric field region to the deep well side, protecting the gate dielectric layer.
It effectively reduces the equivalent resistance of parasitic transistors, improves the UIS capability and robustness of devices, reduces gate dielectric layer damage, and optimizes the switching process of devices.
Smart Images
Figure CN115966591B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a superjunction MOS device and its manufacturing method. Background Technology
[0002] In a conventional VDMOS (vertical double-diffused metal oxide semiconductor) transistor, as the breakdown voltage increases, the resistivity and thickness of the epitaxial layer need to increase, resulting in a very high on-resistance. The on-resistance Rdson is related to the breakdown voltage BV as follows: Rdson ∝ BV 2.5 This is what is commonly referred to as the 'silicon limit'. To reduce on-resistance or overcome the silicon limit, the mainstream technology now is to use superjunction technology. Its basic principle is the charge balance principle. By introducing a superjunction structure with spaced P-pillars and N-pillars into the drift region of a regular power MOS transistor, the trade-off between the on-resistance and breakdown voltage of a regular MOS transistor is greatly improved.
[0003] The UIS (Unclamped Inductive Switching) capability of superjunction MOS devices is an important indicator of their reliability. Currently, how to improve the UIS capability of superjunction MOS devices is one of the hot research topics in the field. Summary of the Invention
[0004] The purpose of this invention is to provide a superjunction MOS device and its manufacturing method, which can improve the UIS capability of the superjunction MOS device.
[0005] To achieve the above objectives, the present invention provides a superjunction MOS device having at least one cell structure, the cell structure including a first conductivity type pillar formed in a substrate, a second conductivity type pillar formed in the substrate on both sides of the first conductivity type pillar, a gate formed on the top surface of the substrate, a second conductivity type well formed on the top of the second conductivity type pillars on both sides of the gate, and a first conductivity type source region formed on both sides of the gate and located on the top of the second conductivity type well, wherein the second conductivity type well on one side of the gate is a deep well with a large longitudinal extension depth, and the second conductivity type well on the other side of the gate is a normal well with a shallower longitudinal extension depth than the deep well.
[0006] Optionally, the doping concentration of the second conductivity type ions in the deep well is higher than the doping concentration of the second conductivity type ions in the normal well.
[0007] Optionally, the lateral extension width of the deep well below the bottom of the gate is greater than that of the normal well.
[0008] Optionally, the difference in longitudinal extension depth between the deep trap and the normal trap is 1 μm to 3 μm.
[0009] Optionally, the substrate has a core region and a terminal region located around the core region, the cell structure is formed in the core region, and a main junction of a second conductivity type is formed in the substrate in the region where the terminal region and the core region meet, the main junction having the same longitudinal depth as the deep well.
[0010] Based on the same inventive concept, the present invention also provides a method for manufacturing a superjunction MOS device, comprising:
[0011] A substrate having at least one cell region is provided, wherein a first conductivity type pillar and a second conductivity type pillar located on both sides of the first conductivity type pillar are formed in the substrate having the cell region;
[0012] A second conductive type well is formed at the top of the second conductive type pillars on both sides of the first conductive type pillar. The second conductive type well on one side of the first conductive type pillar is a deep well with a large longitudinal extension depth and a high doping concentration of the second conductive type ions. The second conductive type well on the other side of the first conductive type pillar is a normal well with a shallower longitudinal extension depth than the deep well and a lower doping concentration of the second conductive type ions than the deep well.
[0013] A gate dielectric layer and a gate are formed on the substrate surface of the cell region. The gate is located above the first conductivity type pillar and extends laterally to a portion of the top surface of the deep well and a portion of the top surface of the normal well, respectively.
[0014] A first conductivity type source region is formed in the deep well and the normal well, located on both sides of the gate.
[0015] Optionally, the lateral extension width of the deep well below the bottom of the gate is greater than that of the normal well.
[0016] Optionally, the step of forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar includes:
[0017] First trap ion implantation is performed on the top of the second conductivity type pillars on both sides of the first conductivity type pillar using second conductivity type ions;
[0018] The top of the second conductive type pillar on one side of the first conductive type pillar is masked, and second-conductive type ions are used to implant second-trap ions into the top of the second conductive type pillar on the other side of the first conductive type pillar. The longitudinal depth of the second-trap ion implantation and the lateral extension width at the top of the first conductive type pillar are both greater than the first-trap ion implantation.
[0019] An annealing process is performed to push the well, thereby forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar;
[0020] Alternatively, the step of forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar includes:
[0021] The top of the second conductive type pillar on one side of the first conductive type pillar is masked, and second trap ion implantation is performed on the top of the second conductive type pillar on the other side of the first conductive type pillar using second conductive type ions;
[0022] First-well ion implantation is performed on the top of the second-well ion implantation on both sides of the first-well ion implantation using second-conductivity type ions, and the longitudinal depth of the second-well ion implantation is greater than the longitudinal depth of the first-well ion implantation.
[0023] An annealing process is performed to push the wells, thereby forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar.
[0024] Optionally, the doping concentration of the second conductivity type ions in the deep well is higher than the doping concentration of the second conductivity type ions in the normal well.
[0025] Optionally, the parameters for ion implantation in the second trap include: an ion implantation dose of 2E13 / cm². 2 ~1E14 / cm 2 The injected energy is 50 keV to 300 keV.
[0026] Optionally, the substrate has a core region and a terminal region located around the core region, the cell region is located in the core region, and the region where the terminal region and the core region meet is the region where the main junction is to be formed; during the first well ion implantation, a mask is applied to the terminal region including the region where the main junction is to be formed; during the second well ion implantation on the top of the second conductivity type pillar on the other side of the first conductivity type pillar, a second well ion implantation is applied to the top of the substrate of the region where the main junction is to be formed, so that after the annealing process pushes the well, a main junction is formed in the terminal region.
[0027] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0028] 1. A deep well with a large vertical depth is formed in the substrate on one side of the gate, and a normal well with a shallow vertical depth is formed in the substrate on the other side of the gate. When holes are conducted away during the switching process of the device, more of them are directed to the deep well side, which can reduce the equivalent resistance of the parasitic transistor, effectively suppress the turn-on of the parasitic transistor, and thus improve the UIS capability.
[0029] 2. The presence of the deep well allows the high electric field region at the gate dielectric layer (i.e., the surface electric field intensity of the substrate) to shift to the deep well side, thereby reducing the surface electric field intensity at the interface between the gate dielectric layer and the substrate. This effectively protects the gate dielectric layer, making the device less susceptible to damage and improving its robustness.
[0030] 3. The presence of the deep well also shifts the ionization collision point to the deep well side, which can optimize the current of the device when it is turned off, thereby improving the overshoot phenomenon.
[0031] 4. During the manufacturing process, the mask used to form the main junction and ion implantation can be used to form the deep trap, so there is no need to add a mask and there will be no significant increase in additional process costs. Attached Figure Description
[0032] Figure 1 This is a schematic cross-sectional view of a cell structure of a conventional superjunction MOS device.
[0033] Figure 2 This is a cross-sectional schematic diagram of a cell structure of a superjunction MOS device according to a specific embodiment of the present invention.
[0034] Figure 3 This is an electric field distribution diagram of a superjunction MOS device according to a specific embodiment of the present invention and a superjunction MOS device in the prior art.
[0035] Figure 4 These are hole concentration distribution curves of a superjunction MOS device according to a specific embodiment of the present invention and a superjunction MOS device in the prior art.
[0036] Figure 5 This is a flowchart of a manufacturing method for a superjunction MOS device according to a specific embodiment of the present invention.
[0037] Figures 6 to 10 This is a schematic cross-sectional view of the device structure in the manufacturing process of a superjunction MOS device according to an embodiment of the present invention.
[0038] Figures 11 to 13 This is a schematic diagram of the cross-sectional structure of a superjunction MOS device in the manufacturing process of another embodiment of the present invention.
[0039] The specific reference numerals in each figure are as follows:
[0040] 100, 200 - Substrate; 101, 201 - First conductivity type pillars; 102, 202 - Second conductivity type pillars; 103, 203a - Normal wells; 104, 204 - Source regions; 105, 205 - Gates; 200a - Semiconductor substrate; 200b - Semiconductor epitaxial layer; 200c - Deep trench; 202a - Ion implantation region; 203b - Deep well; 203 - First well ion implantation region; 203' - Second well ion implantation region; 206 - Gate dielectric layer; 207 - Field oxide layer; 301 - First patterned photoresist layer; 301a - First well opening; 302 - Second patterned photoresist layer; 302a - Second well opening; 302b - Main junction opening; I - Core region; II - Termination region. Detailed Implementation
[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as "on" or "connected to" other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" or "directly connected to" other elements or layers, there are no intervening elements or layers. Although terms such as first, second, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion. Spatial relation terms such as “below,” “under,” “below,” “above,” “on top,” “above,” etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as “below,” “under,” “below” will be oriented “on top” of other elements or features. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptions used herein will be interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms of "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0042] As described in the background section, the UIS (Unclamped Inductive Switching) capability of superjunction MOS devices is an important indicator of their reliability. Currently, how to improve the UIS capability of superjunction MOS devices is one of the hot research topics for those skilled in the art.
[0043] Taking an example where the first conductivity type is N-type and the second conductivity type is P-type, please refer to... Figure 1 The cell structure of conventional superjunction MOS devices typically includes: N-pillars 101 formed in a substrate 100, P-pillars 102 formed in the substrate on both sides of the N-pillars 101, P-wells 103 formed at the top of the two P-pillars 102 respectively, a gate 105 formed on the substrate surface, and source regions 104 formed in the P-wells 103 on both sides of the gate 105. The gate 105 overlaps with the P-wells 103 and the source regions 104, and the two P-wells 103 are axially symmetrical about the central axis of the gate 105.
[0044] For the aforementioned superjunction MOS device, a bipolar junction transistor (BJT) inevitably parasitizes near the P-well 103. The P-well 103 forms the base region of the parasitic BJT, and the collector and emitter regions of the parasitic BJT are also the drain and source regions of the superjunction MOS transistor, respectively. Furthermore, the parasitic BJT has an equivalent resistance RB from the source region to the P-well 103. When the superjunction MOS device is in the off state, as the drain-source voltage increases, the internal electric field gradually increases, and the leakage current also increases. When part of the leakage current flows through the parasitic BJT, a voltage drop is generated across the equivalent resistance RB. This voltage drop is equal to the voltage across the parasitic BJT. BE When a superjunction MOS device approaches avalanche breakdown, the leakage current increases sharply. If the voltage drop across the RB is sufficient to turn on the parasitic BJT, the parasitic BJT will cause a secondary breakdown effect. Therefore, the equivalent resistance RB is also one of the key factors determining the UIS (Unclamped Inductive Switching) capability of a superjunction MOS device.
[0045] Based on this, the present invention provides a superjunction MOS device and its manufacturing method, which improves the UIS capability of the superjunction MOS device by reducing the equivalent resistance (IR) of the parasitic transistor. Specifically, one side of the gate is configured as a deep well and the other side as a normal well, thereby forming an asymmetrical well structure design about the central axis of the gate. This allows more holes to be conducted to the deep well side, thus reducing the IRS of the parasitic transistor and improving the UIS capability. At the same time, the presence of the deep well transfers the high electric field region at the gate dielectric layer to the deep well, thereby effectively protecting the gate dielectric layer and improving the robustness of the device.
[0046] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0047] Please refer to Figure 2 An embodiment of the present invention provides a superjunction MOS device, which is formed on a substrate 200 and has at least one cell structure. Each cell structure includes: a first conductivity type pillar 201 formed in the substrate 200, a second conductivity type pillar 202 formed in the substrate 200 on both sides of the first conductivity type pillar 201, a gate 205 formed on the top surface of the substrate 200, second conductivity type wells 203a and 203b formed on the top of the second conductivity type pillars 202 on both sides of the gate 205, and a first conductivity type source region 204 formed on both sides of the gate 205 and located on the top of the second conductivity type wells 203a and 203b.
[0048] The substrate 200 can be any suitable substrate material, such as bulk silicon, or a substrate comprising a semiconductor substrate (not shown) and a first conductivity type semiconductor epitaxial layer (not shown) formed on the semiconductor substrate. The semiconductor substrate can be any suitable semiconductor material, such as silicon, germanium, silicon carbide, gallium arsenide, etc. Multiple first conductivity type pillars 201 and multiple second conductivity type pillars 202 are alternately arranged in the substrate 200, forming multiple cell structures arranged side-by-side, with adjacent cell structures sharing the second conductivity type pillars 202 at their boundaries.
[0049] Taking an example where the first conductivity type is N-type and the second conductivity type is P-type, the semiconductor epitaxial layer of the first conductivity type can be a semiconductor layer doped with N-type ions such as phosphorus or arsenic, such as silicon, germanium, or silicon carbide. The first conductivity type pillar 201 is an N-pillar, and the second conductivity type pillar 202 is a P-pillar.
[0050] The gate 205 is a polysilicon gate or a metal gate, and a gate dielectric layer 206 is sandwiched between it and the substrate 200 (i.e., the first conductivity type pillar 201 and the second conductivity type pillar 202). The gate dielectric layer 206 can be silicon oxide or a high-k dielectric, etc.
[0051] Second conductivity type wells 203a and 203b are respectively disposed on both sides of the gate 205, and the second conductivity type wells 203a and 203b are asymmetrically distributed about the central axis of the gate 205. The second conductivity type well 203b on one side of the gate 205 is a deep well with a larger longitudinal extension depth and a higher doping concentration of the second conductivity type ions. The second conductivity type well 203a on the other side of the gate 205 is a normal well with a shallower longitudinal extension depth and a lower doping concentration of the second conductivity type ions than the second conductivity type well 203b. Optionally, the doping concentration of the second conductivity type ions in the second conductivity type well 203b (i.e., the deep well) is 2E13 / cm² higher than the doping concentration of the second conductivity type ions in the second conductivity type well 203a (i.e., the normal well). 2 ~1E14 / cm 2 .
[0052] Furthermore, the lateral extension width W2 of the second conductivity type well 203b (i.e., deep well) at the bottom of the gate 205 is greater than the lateral extension width W1 of the second conductivity type well 203a (i.e., normal well) at the bottom of the gate 205.
[0053] Figure 2 As shown, the second conductivity type well 203b is a deep well, and the second conductivity type well 203a is a normal well. The longitudinal depth H2 of the second conductivity type well 203b is greater than the longitudinal depth H1 of the second conductivity type well 203a, and the lateral extension width W2 of the second conductivity type well 203b at the bottom of the gate 205 is greater than the lateral extension width W1 of the second conductivity type well 203a at the bottom of the gate 205. Optionally, H2-H1 = 1μm to 3μm, for example, 2μm.
[0054] However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the second conductivity type well 203b may be a normal well and the second conductivity type well 203a may be a deep well.
[0055] Furthermore, the "asymmetrical distribution of the second conductivity type traps on both sides of the gate about the central axis of the gate" described in this invention is reflected in the fact that the longitudinal depth of the second conductivity type traps on one side of the gate, the lateral extension width at the bottom of the gate, and the doping concentration of the second conductivity type ions are all greater than those on the other side of the gate.
[0056] Optionally, the substrate 200 has a core region (e.g., Figure 6 (as shown in I) and the terminal area located outside the core area (such as Figure 6 As shown in II), each cell structure is formed in the core region, and a main junction of a second conductivity type (such as...) is formed in the substrate 200 at the boundary between the terminal region and the core region. Figure 10 As shown in 203c, the main junction has the same longitudinal depth H2 as the deep well.
[0057] Testing revealed that, when comparing the superjunction MOS device of the present invention obtained under otherwise identical conditions with existing superjunction MOS devices, it was found that, firstly, please refer to... Figure 3 As shown, in existing superjunction MOS devices, the well depths on both sides of the gate are the same and axially symmetrical about the central axis of the gate. A high electric field region exists at the interface between the gate dielectric layer and the substrate, and the electric field distribution in the wells on both sides of the gate is essentially axially symmetrical about the central axis of the gate. In contrast, in the superjunction MOS device of this invention, one side of the gate is a deep well with a large vertical depth, a large lateral extension width at the bottom of the gate, and a high doping concentration of the second conductivity type ions. The other side of the gate is a normal well with a smaller vertical depth, a smaller lateral extension width at the bottom of the gate, and a lower doping concentration of the second conductivity type ions. Furthermore, the presence of the deep well in this invention allows the high electric field region at the gate dielectric layer to shift to the deep well side, thereby reducing the surface electric field intensity at the interface between the gate dielectric layer and the substrate, effectively protecting the gate dielectric layer, making the device less prone to damage, and improving the device's robustness. Secondly, as... Figure 4 As shown, during the switching process of the device, when holes are conducted away, the holes in the wells on both sides of the gate of the existing superjunction MOS device are basically the same. However, in the superjunction MOS device of the present invention, more holes are conducted to the deep well side, and the doping concentration of the second conductivity type ions in the deep well is relatively high. This can reduce the equivalent resistance of the parasitic transistor in the device, effectively suppress the turn-on of the parasitic transistor, and thus improve the UIS capability of the device. Furthermore, in the superjunction MOS device of the present invention, when holes are conducted away during the switching process, the presence of the deep well allows more holes to be conducted to the deep well side, thereby shifting the ionization collision point to the deep well side. This optimizes the current during device turn-off and improves overshoot.
[0058] Based on the same inventive concept, please refer to Figure 5 An embodiment of the present invention also provides a method for manufacturing the superjunction MOS device as described above, comprising:
[0059] S1, providing a substrate having at least one cell region, wherein a first conductivity type pillar and a second conductivity type pillar located on both sides of the first conductivity type pillar are formed in the substrate of the cell region;
[0060] S2, a second conductive type well is formed at the top of the second conductive type pillars on both sides of the first conductive type pillar, and the second conductive type well on one side of the first conductive type pillar is a deep well with a large longitudinal extension depth and a high doping concentration of the second conductive type ions, and the second conductive type well on the other side of the first conductive type pillar is a normal well with a shallower longitudinal extension depth than the deep well and a lower doping concentration of the second conductive type ions than the deep well.
[0061] S3, a gate dielectric layer and a gate are formed on the substrate surface of the cell region, the gate being located above the first conductivity type pillar and extending laterally to a portion of the top surface of the deep well and a portion of the top surface of the normal well, respectively;
[0062] S4, forming a first conductivity type source region located on both sides of the gate in the deep well and the normal well.
[0063] Please refer to Figure 6 and Figure 7 In step S1, firstly, a semiconductor epitaxial layer 200b having a first conductivity type is grown on a semiconductor substrate 200a having a core region I and a terminal region II. The semiconductor epitaxial layer 200a having the first conductivity type can be formed by multiple epitaxial layer deposition processes. The semiconductor epitaxial layer 200b and the semiconductor substrate 200a constitute the substrate of the present invention. Then, the semiconductor epitaxial layer 200a is photolithographically etched and etched to form a plurality of deep trenches 200c in the core region I and the terminal region II, respectively. Subsequently, through processes such as epitaxial growth, in-situ doping, and chemical mechanical polishing, a semiconductor epitaxial layer of a second conductivity type is filled in the deep trenches 200c to form alternating second conductivity type pillars 202 and first conductivity type pillars 201. At this time, the semiconductor epitaxial layer 200b between adjacent second conductivity type pillars 202 is a first conductivity type pillar 201. In the core region I, each pair of adjacent second conductive type pillars 202 and the first conductive type pillar 201 sandwiched between them constitute a cell region. In this invention, two adjacent cells share the same second conductive type pillar 202.
[0064] Please refer to Figure 8 and Figure 9In step S2, firstly, a photolithography process is performed using an existing mask for fabricating the normal wells of the core region to form a first patterned photoresist layer 301 on the top surface of the semiconductor epitaxial layer 200b. This first patterned photoresist layer 301 masks the terminal region II and has first well openings 301a that correspond to the respective second conductive type pillars 202 in the core region I. The first well openings 301a can expose the tops of the aligned second conductive type pillars 202. The linewidth of the first well openings 301a can be slightly larger than the top width of the second conductive type pillars 202 to expose portions of the tops of the first conductive type pillars 201 on both sides of the second conductive type pillars 202. Then, the first patterned photoresist layer is formed... Using the photoresist layer 301 as a mask, first well ion implantation is performed on the top of each second conductivity type pillar 202 in the core region I to form a first well ion implantation region 203. This first well ion implantation process is a conventional process used to form a normal well of the second conductivity type at a normal depth in the core region. Then, the first patterned photoresist layer 301 is removed, and a photolithography process is performed using an improved main junction mask (i.e., this mask adds a deep well pattern to the core region compared to the existing main junction mask) to form a second patterned photoresist layer 302 on the top surface of the semiconductor epitaxial layer 200b, which masks the first conductivity type pillars 202 in each cell region of the core region I. The first well ion implantation region 203 on one side of the electrical type pillar 201 has a second well opening 302a that exposes the top of the first well ion implantation region 203 on the other side of the core region I, and a main junction opening 302b that exposes the top of the main junction region to be formed in the terminal region II. The linewidth of the second well opening 302a can be slightly larger than the top width of the first well ion implantation region 203 to expose part of the top of the corresponding first well ion implantation region 203 and the surrounding first electrical type pillar 201. Then, using the second patterned photoresist layer 302 as a mask, the core region I and the terminal region II are then... A second well ion implantation is performed to form a second well ion implantation region 203'. This second well ion implantation process is a prior art ion implantation process used to form the main junction, and its implantation depth and implantation dose are greater than those of the first well ion implantation. Finally, high-temperature annealing is performed to push the ions in the second well ion implantation region 203', the first well ion implantation region 203, and the ion implantation region in the terminal region II are activated and diffused. Ultimately, a second conductivity type well 203a (i.e., a normal well) and a second conductivity type well 203b (i.e., a deep well) are formed on both sides of the first conductivity type pillar 201 in each cell region of the core region I, and a main junction 203c is formed in the terminal region II. The depth to which the second conductivity type well 203b (i.e., the deep well) extends longitudinally toward the semiconductor substrate 200a is greater than the depth to which the second conductivity type well 203a (i.e., the normal well) extends longitudinally toward the semiconductor substrate 200a.
[0065] In this embodiment, conventional Pbody implantation (i.e., first well ion implantation) is performed first in the core region, followed by deep well implantation (i.e., second well ion implantation) in the main junction and core region. The implantation energy (or implantation depth) of the first well ion implantation is less than the implantation energy (or implantation depth) of the second well ion implantation. In other embodiments of the invention, deep well implantation (i.e., second well ion implantation) in the main junction and core region can be performed first, followed by conventional Pbody implantation (i.e., first well ion implantation) in the core region. Specifically, the step of forming a deep well 203b and a normal well 203a in the top of the second conductive type pillars 203 on both sides of each first conductive type pillar 201 includes:
[0066] The top of the second conductive type pillar 203 on one side of the first conductive type pillar 201 is masked, and second trap ion implantation is performed on the top of the second conductive type pillar 203 on the other side of the first conductive type pillar 201 and the area where the main junction is to be formed.
[0067] First-well ion implantation is performed on the top of the second-well ion implantation on both sides of the first-well ion implantation using second-conductivity type ions, and the longitudinal depth of the second-well ion implantation is greater than the longitudinal depth of the first-well ion implantation.
[0068] An annealing process is performed to push the wells, so as to form a deep well 203b and a normal well 203a in the top of the second conductive type pillars 203 on both sides of the first conductive type pillar 201.
[0069] It should be noted that the second well ion implantation is the implantation of the terminal main junction (Pring), while the first well ion implantation is the traditional Pbody implantation. The process parameters for the first and second well ion implantations are set reasonably according to the device performance requirements.
[0070] Please refer to Figure 9 In step S3, the field oxide layer 207 can be covered by processes such as thermal oxidation or chemical vapor deposition, and the field oxide layer 207 can be photolithographically and etched to remove the portion of the field oxide layer 207 located in the core region I and expose the edge region of the main junction 203c adjacent to the core region I in the terminal region II; then, the gate dielectric layer 206 is formed by thermal oxidation, and the gate 205 is formed by polysilicon deposition, photolithography and etching. The gate in each cell region of the core region I is located above its first conductivity type pillar 201 and extends laterally to the top surface of a portion of the second conductivity type well 203b (i.e., deep well) and a portion of the top surface of the second conductivity type well 203a (i.e., normal well), and the width of the second conductivity type well 203b (i.e., deep well) extending laterally below the bottom of the gate 205 is greater than the width of the second conductivity type well 203a (i.e., normal well) extending laterally below the bottom of the gate 205.
[0071] Please continue to refer to this. Figure 9 In step S4, using the gate 205 and the field oxide layer 207 as masks, first conductivity type ion implantation is performed on regions such as the main junction 203c, the second conductivity type well 203b (i.e., deep well), and the second conductivity type well 203a (i.e., normal well) to form the source region 204.
[0072] Furthermore, ion implantation of a first conductivity type can be performed from the side of the semiconductor substrate 200 facing away from the semiconductor epitaxial layer 200b to form a drain region (not shown).
[0073] It should be noted that, in other embodiments of the present invention, in step S1, alternating first and second conductivity type pillars can be fabricated by repeatedly performing epitaxial growth and ion implantation processes. Specifically, please refer to... Figure 11 In step S1, firstly, a semiconductor substrate 200a having a core region I and a terminal region II is provided; then, the following steps (a) to (c) are performed repeatedly: (a) a semiconductor epitaxial layer 200b of a first conductivity type (e.g., N-type) is formed, and a patterned photoresist layer is formed by a series of photolithography processes such as photoresist coating, exposure, and development. The patterned photoresist layer has ion implantation openings for forming pillars of a second conductivity type; (b) using the patterned photoresist layer as a mask, ion implantation of the top layer of the semiconductor epitaxial layer 200b is performed using ions of the second conductivity type along the direction of perpendicular incidence to form multiple ion implantation regions 202a of the same depth of the second conductivity type; (c) the patterned photoresist layer is removed. In step S2, a semiconductor epitaxial layer 200b of a first conductivity type is first formed. Then, a first patterned photoresist layer 301 with a first well opening 301a is formed using the same method as step S2 in the above embodiment. Using the first patterned photoresist layer 301 as a mask, first well ion implantation is performed on the top layer of the semiconductor epitaxial layer 200b using ions of a second conductivity type along the perpendicular incident direction to form multiple first well ion implantation regions 203 of the same depth. Afterwards, please refer to... Figure 12 The first patterned photoresist layer 301 is removed, and a second patterned photoresist layer 302 with a second well opening 302a and a main junction opening 302b is formed. Using the second patterned photoresist layer 302 as a mask, second well ion implantation is performed on the top layer of the semiconductor epitaxial layer 200b using ions of the second conductivity type along the perpendicular incident direction to form multiple second well ion implantation regions 203' of the same depth and ion-doped regions for forming the main junction. Afterwards, please refer to... Figure 13The second patterned photoresist layer 302 is removed, and high-temperature annealing is performed to push the wells, thereby activating and diffusing the implanted ions in the second well ion implantation region 203', the first well ion implantation region 203, and the ion implantation region in the terminal region II. This forms a second conductivity type well 203a (i.e., a normal well) and a second conductivity type well 203b (i.e., a deep well) on both sides of the first conductivity type pillar 201 in each cell region of the core region I, and forms a main junction 203c in the terminal region II. The depth of the second conductivity type well 203b (i.e., the deep well) extending longitudinally toward the semiconductor substrate 200a is greater than the depth of the second conductivity type well 203a (i.e., the normal well) extending longitudinally toward the semiconductor substrate 200a. In this process, ions in the respective second conductivity type ion implantation regions 202a used to form a second conductivity type column 202 in the core region I and terminal region II undergo longitudinal and lateral diffusion, and eventually connect sequentially in the longitudinal direction to form the corresponding second conductivity type column 202. The second conductivity type trap 203b (i.e., deep trap) and the second conductivity type trap 203a (i.e., normal trap) are also connected to the top of the corresponding second conductivity type column 202.
[0074] Optionally, in the above embodiments, the implantation dose of second-conductivity type ions in the formed second-conductivity type well 203b (i.e., deep well) is, for example, 2E13 / cm higher than the implantation dose of second-conductivity type ions in the formed second-conductivity type well 203a (i.e., normal well). 2 ~1E14 / cm 2 .
[0075] Optionally, the lateral extension width of the deep well below the bottom of the gate is greater than that of the normal well.
[0076] Optionally, in the above embodiments, the parameters for ion implantation in the first well include: an ion implantation dose of 2E13 / cm². 2 ~1E14 / cm 2 The injected energy is 50 keV to 100 keV.
[0077] The manufacturing method of the superjunction MOS device of this invention is simple and easy to implement. It can utilize existing main junction processes to form the required deep well in the core region in one step, thus benefiting from the high-temperature push-well process of the main junction. This allows for a better gradient between the deep well and the normal well without adding additional thermal processes, maintaining the on-resistance of the device at the level of existing technologies. Compared to existing technologies, only the main junction layout design needs to be modified, without changing the process. It has no significant impact on the overall process technology of the superjunction MOS device, while effectively improving UIS capability and device robustness, making the device less prone to damage.
[0078] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.
Claims
1. A superjunction MOS device having at least one cell structure, the cell structure comprising a first conductivity type pillar formed in a substrate, a second conductivity type pillar formed in the substrate on both sides of the first conductivity type pillar, a gate formed on the top surface of the substrate, a second conductivity type well formed on the top of the second conductivity type pillars on both sides of the gate, and a first conductivity type source region formed on both sides of the gate and located on the top of the second conductivity type well, characterized in that, The second conductivity type well on one side of the gate is a deep well with a large longitudinal extension depth, and the second conductivity type well on the other side of the gate is a normal well with a shallower longitudinal extension depth than the deep well; wherein, the substrate has a core region and a terminal region located outside the core region, the cell structure is formed in the core region, and a main junction of the second conductivity type is formed in the substrate in the region where the terminal region and the core region meet, and the main junction has the same longitudinal depth as the deep well.
2. The superjunction MOS device as described in claim 1, characterized in that, The doping concentration of the second conductivity type ions in the deep well is higher than that in the normal well.
3. The superjunction MOS device as described in claim 1, characterized in that, The deep well has a wider lateral extension below the bottom of the gate than the normal well.
4. The superjunction MOS device as described in claim 3, characterized in that, The difference in longitudinal depth between the deep well and the normal well is 1 μm to 3 μm.
5. A method for manufacturing a superjunction MOS device, characterized in that, include: A substrate is provided having at least one cell region, the substrate having a core region and a terminal region located outside the core region, the cell region being located within the core region; A first type of conductive pillar and a second type of conductive pillar located on both sides of the first type of conductive pillar are formed in the substrate of the cell region; A second conductive type well is formed at the top of the second conductive type pillars on both sides of the first conductive type pillar. The second conductive type well on one side of the first conductive type pillar is a deep well with a large longitudinal extension depth, and the second conductive type well on the other side of the first conductive type pillar is a normal well with a longitudinal extension depth shallower than the deep well. A main junction of the second conductive type is formed in the substrate of the region where the terminal region and the core region meet. The main junction has the same longitudinal depth as the deep well. A gate dielectric layer and a gate are formed on the substrate surface of the cell region. The gate is located above the first conductivity type pillar and extends laterally to a portion of the top surface of the deep well and a portion of the top surface of the normal well, respectively. A first conductivity type source region is formed in the deep well and the normal well, located on both sides of the gate.
6. The method for manufacturing a superjunction MOS device as described in claim 5, characterized in that, The deep well has a wider lateral extension below the bottom of the gate than the normal well.
7. The method for manufacturing a superjunction MOS device as described in claim 5 or 6, characterized in that, The step of forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar includes: First trap ion implantation is performed on the top of the second conductivity type pillars on both sides of the first conductivity type pillar using second conductivity type ions; The top of the second conductive type pillar on one side of the first conductive type pillar is masked, and second-conductive type ions are used to implant second-trap ions into the top of the second conductive type pillar on the other side of the first conductive type pillar, and the longitudinal depth of the second-trap ion implantation is greater than the longitudinal depth of the first-trap ion implantation. An annealing process is performed to push the well, thereby forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar; Alternatively, the step of forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar includes: The top of the second conductive type pillar on one side of the first conductive type pillar is masked, and second trap ion implantation is performed on the top of the second conductive type pillar on the other side of the first conductive type pillar using second conductive type ions; First-well ion implantation is performed on the top of the second-well ion implantation on both sides of the first-well ion implantation using second-conductivity type ions, and the longitudinal depth of the second-well ion implantation is greater than the longitudinal depth of the first-well ion implantation. An annealing process is performed to push the wells, thereby forming the deep well and the normal well at the top of the second conductive type pillars on both sides of the first conductive type pillar.
8. The method for manufacturing a superjunction MOS device as described in claim 7, characterized in that, The doping concentration of the second conductivity type ions in the deep well is higher than that in the normal well.
9. The method for manufacturing a superjunction MOS device as described in claim 7, characterized in that, During the first well ion implantation, a terminal region including the area where the main junction is to be formed is masked; during the second well ion implantation on the top of the second conductivity type pillar on the other side of the first conductivity type pillar, a second well ion implantation is performed on the top of the substrate of the area where the main junction is to be formed, so that after the well is pushed out by the annealing process, a main junction is formed in the terminal region.