ARM and FPGA Based High-Speed Buffered CAN Bus Communication System and Method

Abstract

The present invention relates to a high-speed buffered CAN bus communication system and method based on ARM and FPGA. All components are designed using domestic chips. A dual-port RAM is established in the FPGA and connected to two ARM processors. Two circular buffer queues, Queue-Tx1, Queue-Tx2, Queue-Rx1, and Queue-Rx2, are established in the two ARM chips. Queue-Tx1 and Queue-Rx1 are used as buffers for exchanging data with the FPGA chip, and Queue-Tx2 and Queue-Rx2 are used as buffers for receiving and transmitting data on the CAN bus. Since the dual-buffer queue method is adopted to process the large-volume CAN bus transmission, the data reception capacity and data transceiver capacity of the computer CAN bus are greatly improved. The data transmission capacity reaches 11,000 frames per second, and the data reception capacity reaches 14,000 frames per second. The data transmission and reception capabilities are significantly improved. When sending 10,000 frames at a time, no data is lost, meeting the requirement of the user's cache of 100 frames.

Description

Technical Field

[0001] The present invention belongs to the field of CAN bus communication, and relates to a high-speed buffered CAN bus communication system and method based on ARM and FPGA, aiming to solve the problems that in the process of large data volume transmission, the CAN bus may have too long transmission time, low efficiency, and even data loss, and a dual-buffered CAN bus communication method is proposed accordingly. Background Art

[0002] CAN bus technology has the characteristics of automatic message filtering and retransmission, extremely low bit error rate, and high communication rate, and is widely used in industrial and military fields. Currently, the CAN bus interface card based on PCIe interface has a relatively low data throughput rate. In the case of sudden transmission of a large amount of data, problems such as too long transmission time and even data loss occur. In a certain type of reconnaissance vehicle, various equipments are connected through the CAN bus, and the load rate of CAN bus communication and the amount of transmitted frame data are both large. Therefore, it is necessary to implement a high-speed large data volume CAN bus communication design.

[0003] In order to ensure the smooth research, development and production of equipments, and to ensure the information security, autonomy and controllability of equipments, the localization of equipments is imperative. And due to factors such as high-tech sanctions and the shrinking production capacity of foreign chips, it is no longer appropriate to use foreign chips for design. Existing equipments or newly developed equipments need to be transformed or redesigned domestically to achieve the purpose of not being restricted. Summary of the Invention

[0004] Technical Problems to be Solved

[0005] In order to avoid the deficiencies of the prior art, the present invention proposes a high-speed buffered CAN bus communication system and method based on ARM and FPGA. All components are designed with domestic chips, and combined with common solutions for optimization and improvement to solve the problems of equipment localization and data transmission stability and reliability in the case of sudden transmission of a large amount of data. The hardware design is a communication board card with a PCIe dual-channel CAN bus. The board card is installed in a domestic chassis and interacts with the computer through the PCIe interface.

[0006] Technical Solutions

[0007] A high-speed buffered CAN bus communication system based on ARM and FPGA, characterized in that: it includes a PCIe bus to parallel local bus chip, a programmable gate array chip FPGA, and two ARM processors based on the Cortex-M3 architecture; a dual-port RAM is established in the FPGA and connected to the two ARM processors. One port is connected to the PSMC bus port of ARM-1 to transmit the address bus and MEM data, and the other port is connected to the PSMC bus port of ARM-2 to transmit the address bus and MEM data; the connection ports between the FPGA and the PCIe bridge chip are the address bus, MEM data, and I / O data lines, and the connection ports to the two ARM processors also include I / O data lines; the two ARM processors are respectively connected to two CAN transceiver modules; four DPRAMs are established in the FPGA, where DPRAM-1 is allocated for the host computer to write, DPRAM-2 is allocated for the host computer to read, DPRAM-3 is allocated for the lower computer to write, and DPRAM-4 is allocated for the lower computer to read.

[0008] A communication method using the above-mentioned high-speed buffered CAN bus communication system based on ARM and FPGA, characterized in that: two circular buffer queues Queue-Tx1, Queue-Tx2 and Queue-Rx1, Queue-Rx2 are established in the two ARM chips; Queue-Tx1 and Queue-Rx1 are used as buffers for exchanging data with the FPGA chip, and Queue-Tx2 and Queue-Rx2 are used as buffers for receiving and transmitting data on the CAN bus; the communication steps are as follows:

[0009] When the host computer sends data, the data is sequentially sent from the FPGA dual-port RAM to the first-level buffer Queue-Tx1 and the second-level buffer Queue-Tx2 of the ARM chip, and the CAN controller fetches the data frame by frame from the second-level buffer Queue-Tx2 and sends it to the CAN bus;

[0010] When the CAN bus receives data, after judging the legality of the data, the data is sequentially input into the FPGA dual-port RAM through the second-level buffer Queue-Rx2 and the first-level buffer Queue-Tx1 of the ARM, and the host computer reads the data from the dual-port RAM to the CPU memory unit through DMA for processing.

[0011] The process of the host computer sending data: 1) The host computer writes the data to be sent into DPRAM-1 through the DMA method, and the FPGA notifies the ARM to read the data in the form of an external interrupt; 2) After receiving the interrupt signal, the ARM temporarily stores the data in the first-level buffer Queue-Tx1 through the FSMC bus. In the main processing process, the ARM checks whether there is still unread data in the first-level buffer Queue-Tx1 in each loop. If there is, it transfers the data from the first-level buffer Queue-Tx1 to the second-level buffer Queue-Tx2, and takes out the data from the second-level buffer Queue-Tx2 frame by frame during idle time, and calls the CAN bus controller to send the data to the CAN bus in sequence.

[0012] The process of the host computer receiving data: 1) When there is data coming on the CAN bus, the data is stored in the second-level buffer Queue-Rx2 through the CAN interrupt. A 5ms timer is set in the program. When the 5ms timing arrives, the buffered data in the second-level buffer Queue-Rx2 is transferred to the first-level buffer Queue-Rx1, and an interrupt signal is generated through the I / O and sent to the FPGA; 2) After receiving the interrupt signal, the FPGA transfers the data in Queue-Rx1 to DPRAM-2 through the FSMC bus, and at the same time generates a PCIe interrupt to notify the host computer to read.

[0013] Beneficial effects

[0014] A high-speed buffered CAN bus communication system and method based on ARM and FPGA proposed by the present invention uses a method of high-speed CAN bus communication implemented by two-level buffer queues. In the CAN bus data processing, the data sent by the computer and the data received by the CAN bus are stored through the dual-port RAM in the FPGA and cached through the double-buffer queue in the ARM. In the process of processing during the idle time of the ARM, the situation of data loss in the case of large data volume transmission on the CAN bus is greatly improved.

[0015] After experimental verification, using the same hardware ARM chip, without any buffer processing in the software and caching data through the internal buffer unit of the hardware, when the computer sends 100 frames of data at a time, the CAN bus device can only receive 17 frames of data, and the remaining 83 frames of data are lost.

[0016] Since the present invention adopts the method of double-buffer queue to process the CAN bus transmission of large data volume, the data receiving ability and data sending and receiving ability of the computer CAN bus are greatly improved. The data sending ability reaches 11,000 frames / second; the data receiving ability reaches 14,000 frames / second. The data sending and receiving ability is significantly improved, and 10,000 frames are sent at a time without data loss, meeting the requirement of the user's cache of 100 frames. The comparison between this board and similar devices is shown in Table 1.

[0017] Table 1 Comparison of parameters between the present invention and similar devices

[0018] Brief Description of the Drawings

[0019] Figure 1 : Block diagram of the principle of the present invention Detailed Description of the Preferred Embodiment

[0020] The present invention will be further described below in conjunction with the embodiments and the drawings:

[0021] The core idea of the present invention is:

[0022] The main processing chips adopted by the present invention are CH368 (PCIe bus to parallel local bus), FMK50T4 (FPGA field programmable gate array chip), GD32F103VET6 (ARM processor chip based on Cortex-M3 architecture) and peripheral interface chips, etc.

[0023] A dual-port RAM is established in the FPGA, and two-level circular buffer queues are established in the ARM. When the host computer sends data, the data is sequentially stored in the dual-port RAM, the ARM first-level buffer, and the ARM second-level buffer. Finally, the CAN controller fetches the data from the second-level buffer frame by frame and sends it to the CAN bus; when the CAN bus receives data, after judging the legality of the data, the data is sequentially stored in the ARM second-level buffer, the ARM first-level buffer, and the dual-port RAM. The host computer reads the data from the dual-port RAM to the CPU memory unit through the DMA method for processing.

[0024] The communication block diagram of the CAN bus is shown in the attached drawings.

[0025] The method of the present invention includes the following steps:

[0026] The communication methods of the two channels are the same. Therefore, the following will be introduced according to the method of single-channel communication.

[0027] [1] Establish 2 independent dual-port RAM block storage spaces in the FPGA. The dual-port RAM (DPRAM) space is set with both read and write bandwidths of 32 bits and a depth of 8KB. One of the RAM blocks is allocated for the host computer to write, defined as DPRAM-1; the other RAM block is allocated for the host computer to read, defined as DPRAM-2.

[0028] [2] Establish four circular buffer queues, Queue-Tx1, Queue-Tx2, Queue-Rx1, and Queue-Rx2, in the ARM chip. Among them, Queue-Tx1 and Queue-Tx2 are buffers for the host computer to send data; Queue-Rx1 and Queue-Rx2 are buffers for the host computer to receive data. Queue-Tx1 and Queue-Rx1 are used as buffers for exchanging data with the FPGA chip, and Queue-Tx2 and Queue-Rx2 are used as buffers for sending and receiving data on the CAN bus.

[0029] [3] Process of the host computer sending data: The host computer software writes the data to be sent into DPRAM-1 through the DMA method. The FPGA uses the external interrupt method to notify the ARM to read the data. After receiving the interrupt, the ARM temporarily stores the data in Queue-Tx1 through the FSMC bus. In the main processing process, the ARM checks whether there is unread data in Queue-Tx1 in each loop. If there is, it transfers the data from Queue-Tx1 to Queue-Tx2, and in the idle time, it takes out the data from Queue-Tx2 frame by frame and calls the CAN bus controller to send the data to the CAN bus in sequence.

[0030] [4] Process of the host computer receiving data: When there is data coming on the CAN bus, the data is stored in Queue-Rx2 through the CAN interrupt. Set a 5ms timer in the program. When the 5ms timer arrives, transfer the buffered data in Queue-Rx2 to Queue-Rx1, and generate an interrupt signal through I / O. After receiving the interrupt signal, the FPGA transfers the data in Queue-Rx1 to DPRAM-2 through the FSMC bus, and at the same time generates a PCIe interrupt to notify the host computer to read.

Claims

1. A high-speed buffered CAN bus communication system based on ARM and FPGA, characterized in that: It includes a PCIe bus to parallel local bus chip, a field-programmable gate array chip FPGA, and two ARM processors based on the Cortex-M3 architecture; In the FPGA, a dual-port RAM is established and connected to the two ARM processors. One port is connected to the FSMC bus port of ARM-1 to transmit the address bus and MEM data, and the other port is connected to the FSMC bus port of ARM-2 to transmit the address bus and MEM data; The connection ports between the FPGA and the PCIe bridge chip are the address bus, MEM data, and I / O data lines. The connection ports with the two ARM processors also include I / O data lines; the two ARM processors are respectively connected to two CAN transceiver modules; four dual-port RAMs (DPRAMs) are established in the FPGA. Among them, DPRAM-1 is allocated for the host computer to write, DPRAM-2 is allocated for the host computer to read, DPRAM-3 is allocated for the lower computer to write, and DPRAM-4 is allocated for the lower computer to read; four circular buffer queues Queue-Tx1, Queue-Tx2, Queue-Rx1, and Queue-Rx2 are established in the two ARM chips; Queue-Tx1 and Queue-Rx1 are used as buffers for exchanging data with the FPGA chip, and Queue-Tx2 and Queue-Rx2 are used as buffers for receiving and transmitting data on the CAN bus.

2. A communication method using the high-speed buffered CAN bus communication system based on ARM and FPGA according to claim 1, characterized in that: The communication steps of the four circular buffer queues are as follows: When the host computer sends data, the data is sequentially sent from the FPGA dual-port RAM to the first-level buffer Queue-Tx1 and the second-level buffer Queue-Tx2 of the ARM chip, and the CAN controller fetches the data frame by frame from the second-level buffer Queue-Tx2 and sends it to the CAN bus; When the CAN bus receives data, after judging the legality of the data, the data is sequentially input into the FPGA dual-port RAM through the second-level buffer Queue-Rx2 and the first-level buffer Queue-Tx1 of the ARM. The host computer reads the data from the dual-port RAM to the CPU memory unit through the DMA method for processing.

3. The method according to claim 2, characterized in that: The process of the host computer sending data: 1) The host computer writes the data to be sent into DPRAM-1 through the DMA method, and the FPGA notifies the ARM to read the data in the form of an external interrupt; 2) After receiving the interrupt signal, the ARM temporarily stores the data in the first-level buffer Queue-Tx1 through the FSMC bus. During the main processing process, the ARM checks whether there is still unread data in the first-level buffer Queue-Tx1 in each loop. If there is, the data is transferred from the first-level buffer Queue-Tx1 to the second-level buffer Queue-Tx2, and the data is fetched frame by frame from the second-level buffer Queue-Tx2 during the idle time, and the CAN bus controller is called to send the data to the CAN bus in sequence.

4. The method according to claim 2, characterized in that: The process of the host computer receiving data: 1) When data arrives on the CAN bus, the data is stored in the secondary buffer Queue-Rx2 through the CAN interrupt. A 5ms timer is set in the program. When the 5ms timer expires, the buffered data in the secondary buffer Queue-Rx2 is transferred to the primary buffer Queue-Rx1, and an interrupt signal is generated through the I / O to send to the FPGA; 2) After receiving the interrupt signal, the FPGA transfers the data in Queue-Rx1 to DPRAM-2 through the FSMC bus, and at the same time generates a PCIe interrupt to notify the host computer to read.

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