A self-testing method and circuit for chip stability

Abstract

This invention discloses a self-testing method and circuit for chip stability. The method is automatically executed before the chip begins operation and includes: sampling the output of the LDO circuit inside the chip, and obtaining the pulse response of the LDO circuit based on the sampled LDO circuit output; calculating the damping ratio of the LDO circuit based on the pulse response, and calculating the phase margin of the LDO circuit based on the damping ratio; determining that the LDO circuit is in a stable state when the phase margin is greater than a preset angle; and determining that the LDO circuit is in an unstable state when the phase margin is less than or equal to the preset angle. This invention addresses the technical problems of low chip power supply reliability, high chip testing cost, and low chip testing efficiency and accuracy in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to a chip stability self-detection method and circuit thereof. BACKGROUND

[0002] With the development of analog circuit technology, it is very important to detect the stability of an LDO (low drop-out linear regulator) circuit. Since the LDO is a closed-loop system, the stability of the output voltage is a crucial parameter. Usually, to test the performance parameters of the internal power supply circuit (such as the LDO) of a chip, a designer needs to design an additional auxiliary circuit to lead the signal of the internal power supply circuit out of the chip pin for testing. Since the pins of the chip are usually very limited, a pin will not be specially used to test the output signal of the LDO, so a pin multiplexing method (i.e., the chip pin normally outputs in the working state of the chip, and outputs the output signal of the LDO in the testing state) needs to be used. However, how to ensure that the chip pin normally outputs in the working state of the chip and outputs the output signal of the LDO in the testing state without chaotic output is one of the difficulties that designers need to face.

[0003] For mass-produced chips, an ATE (Automatic Test Equipment) tester needs to be used to measure the pin signals of each chip to judge the performance indicators of the internal power supply circuit. If the ATE tester is used, the LDO output voltage led out of the chip needs to be measured and sampled multiple times through programming to judge whether the output value is within an acceptable range. However, the above method is inefficient and has a long testing period, which greatly increases the testing cost.

[0004] Secondly, whether the chip is tested by the ATE tester or by a laboratory tester, the chip can only be tested once after it is produced. However, as the working time of the chip increases and the service life of the chip extends, the electromigration in the chip will change the parameters of the internal circuit of the chip, which may again cause the internal LDO system to be unstable and the chip to be unable to work normally. For products with high reliability requirements such as automotive chips and military chips, this may cause irreparable losses. At this time, the ATE tester cannot be used to ensure that the LDO system is stable.

[0005] Therefore, there is an urgent need for a method that can ensure the high reliability of a chip, reduce the testing cost of the chip, improve the testing efficiency and accuracy of the chip. SUMMARY

[0006] The application provides a chip stability self-detection circuit and a circuit thereof, to solve the technical problems of low reliability of chip power supply, high chip testing cost, and low chip testing efficiency and accuracy in the prior art.

[0007] To solve the above technical problems, the application provides a chip stability self-detection method, which is spontaneously performed before the chip works, and includes the following steps:

[0008] sampling an output end of an LDO circuit inside the chip, and obtaining a pulse response of the LDO circuit according to an LDO circuit output obtained through the sampling;

[0009] calculating a damping ratio of the LDO circuit according to the pulse response, and calculating a phase margin of the LDO circuit according to the damping ratio;

[0010] when the phase margin is greater than a preset angle, determining that the LDO circuit is in a stable state;

[0011] when the phase margin is less than or equal to the preset angle, determining that the LDO circuit is in a non-stable state.

[0012] As a preferred scheme, before the sampling of the output end of the LDO circuit inside the chip, the method further includes the following steps:

[0013] inputting an output value of a linear feedback shift register inside the chip into the LDO circuit;

[0014] when the output value of the linear feedback shift register is a high level, an input voltage of the LDO circuit is a first reference voltage, and a pseudo-random sequence generated by the linear feedback shift register is inputted into the LDO circuit;

[0015] when the output value of the linear feedback shift register is a low level, the input voltage of the LDO circuit is a second reference voltage, and the pseudo-random sequence generated by the linear feedback shift register is inputted into the LDO circuit.

[0016] As a preferred scheme, a ratio of the second reference voltage to the first reference voltage is R2 / R1+R2.

[0017] wherein R1 is a first resistance in the LDO circuit, R2 is a second resistance in the LDO circuit, and the first reference voltage and the second reference voltage are both within a preset voltage range inputted for normal working of the LDO circuit.

[0018] As a preferred scheme, the sampling of the output end of the LDO circuit inside the chip and the obtaining of the pulse response of the LDO circuit according to the LDO circuit output obtained through the sampling are specifically as follows:

[0019] The input signal of the LDO circuit is obtained by combining the reference voltage input by the LDO circuit and the pseudo-random sequence, and the pseudo-random sequence is used as a white noise signal of the input end of the LDO circuit; wherein the reference voltage is a first reference voltage or a second reference voltage;

[0020] The output voltage of the LDO circuit inside the chip is sampled by the ADC sampling circuit output;

[0021] According to the input signal, the sampled LDO circuit output signal and the white noise signal, a signal correlation result is calculated;

[0022] According to the signal correlation result, the impulse response of the LDO circuit is calculated.

[0023] As a preferred solution, the calculation method of the signal correlation result is:

[0024]

[0025]

[0026] R yu (m)=h(n)+C

[0027] Wherein h(n) is the impulse response of the LDO circuit, C is a constant, V ref is the reference voltage, V LFSR (n) is a pseudo-random sequence, u(n) is the input signal of the LDO circuit, y(n) is the output signal of the LDO circuit, and h(k) is the impulse response when the independent variable is k.

[0028] As a preferred solution, before calculating the damping ratio of the LDO circuit according to the impulse response, it further includes:

[0029] The operational amplifier, PMOS switch tube and feedback circuit in the LDO circuit are subjected to small signal analysis, and small signal models of the operational amplifier and PMOS switch tube are obtained respectively; wherein the feedback circuit is a third resistor and a fourth resistor component;

[0030] According to the small signal model of the operational amplifier, a first pole of the transmission signal is obtained;

[0031] According to the small signal model of the PMOS switch tube, a second pole and a zero point of the transmission signal are obtained;

[0032] According to the small signal model of the feedback circuit, a third pole of the transmission signal is obtained;

[0033] According to the first pole, the second pole, the third pole and the zero point, the LDO circuit is approximated as a second-order system, and a category of the second-order system is determined; the category of the second-order system includes an under-damped system and an over-damped system.

[0034] As a preferred solution, the damping ratio of the LDO circuit is calculated according to the impulse response, specifically:

[0035] If the second-order system is an under-damped system, a first unit impulse response function is calculated through a transfer function of the second-order system and the impulse response, and a damping ratio of the LDO circuit when the LDO circuit is an under-damped system is calculated according to a preset function abscissa position; wherein the damping ratio of the LDO circuit when the LDO circuit is an under-damped system ranges from (0, 1).

[0036] If the second-order system is an over-damped system, a second unit impulse response function is calculated through a second-order differential equation of the second-order system and according to the impulse response, so as to obtain an inflection point abscissa position and an intersection of a tangent and an abscissa through a derivative of the second unit impulse response function, and further calculate a damping ratio of the LDO circuit when the LDO circuit is an over-damped system; wherein the damping ratio of the LDO circuit when the LDO circuit is an over-damped system ranges from (1, +∞).

[0037] As a preferred solution, the damping ratio of the LDO circuit when the LDO circuit is an under-damped system is calculated in the following manner:

[0038]

[0039]

[0040] Wherein ζ is the damping ratio, h(n1 / 6) and h(n1 / 2) are respectively the first unit impulse response function at two preset function abscissa positions.

[0041] As a preferred solution, the damping ratio of the LDO circuit when the LDO circuit is an over-damped system is calculated in the following manner:

[0042]

[0043]

[0044] Wherein ζ is the damping ratio, t i and t T are respectively the point of the inflection point abscissa position and the intersection of the tangent and the abscissa, t A and t B are respectively any two points in the second unit impulse response function, x(t A ) and x(t B ) are respectively the point t Aand point t B A corresponding second unit impulse response function.

[0045] As a preferred solution, the phase margin of the LDO circuit is calculated according to the damping ratio, specifically:

[0046] The phase margin of the LDO circuit is calculated according to the damping ratio by defining the second-order system and the amplitude:

[0047]

[0048] Where PM is the phase margin, and ζ is the damping ratio.

[0049] Correspondingly, the application also provides a chip stability self-detection circuit, comprising: an LDO circuit, a linear feedback shift register, an ADC sampling circuit, a register conversion stage module, a damping ratio calculation module, a phase margin calculation module, and a stability judgment module.

[0050] The output end of the linear feedback shift register is connected to the input end of the LDO circuit, the input end of the LDO circuit is also connected to a reference voltage, and the output end of the LDO circuit is connected to the input end of the ADC sampling circuit.

[0051] The output end of the ADC sampling circuit is connected to the first input end of the register conversion stage module, the second input end of the register conversion stage module is connected to the input end of the LDO circuit, the output end of the register conversion stage module is connected to the input end of the damping ratio calculation module, the output end of the damping ratio calculation module is connected to the input end of the phase margin calculation module, and the output end of the phase margin calculation module is connected to the stability judgment module.

[0052] As a preferred solution, the LDO circuit comprises a transmission gate circuit, an operational amplifier, a PMOS switch tube, a third resistor, and a fourth resistor.

[0053] The gate of the PMOS switch tube is connected to the output end of the operational amplifier, the source of the PMOS switch tube is connected to a source voltage, and the drain of the PMOS switch tube is connected to the input end of the ADC sampling circuit and the third resistor; the second input end of the operational amplifier is connected to the third resistor, and the third resistor is also connected to the fourth resistor.

[0054] The first input end of the transmission gate circuit is connected to the reference voltage, the second input end of the transmission gate circuit is connected to the output end of the linear feedback shift register, the output end of the transmission gate circuit is connected to the first input end of the operational amplifier, and the second input end of the register conversion stage module is connected to the first input end of the operational amplifier.

[0055] As a preferred solution, the transmission gate circuit comprises a first transmission gate, a second transmission gate, an inverter, a first resistor and a second resistor;

[0056] The first input end of the first transmission gate is connected to the reference voltage, the second input end of the first transmission gate is connected to the output end of the linear feedback shift register, the third input end of the first transmission gate is connected to the output end of the inverter, the input end of the inverter is connected to the output end of the linear feedback shift register, and the output end of the first transmission gate is connected to the first input end of the operational amplifier;

[0057] The first input end of the second transmission gate is connected to the reference voltage through the first resistor, and the first resistor is also connected with the second resistor;

[0058] The second input end of the second transmission gate is connected to the output end of the inverter, the third input end of the second transmission gate is connected to the output end of the linear feedback shift register, and the output end of the second transmission gate is connected to the first input end of the operational amplifier.

[0059] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0060] The technical scheme of the present application can quickly and simply test the LDO stability of the chip through the self-detection method executed by the chip, improves the chip test efficiency, and does not need to use the ATE test equipment to test the power supply stability of the chip, and further obtains the phase margin through the damping coefficient calculation, improves the accuracy of the existing chip LDO stability test, and makes the chip have high reliability.

[0061] Further, the technical scheme of the present application improves the LDO circuit, sets up a self-test circuit in the chip, adds a linear feedback shift register, an ADC sampling circuit, a register conversion stage module, a damping ratio calculation module, a phase margin calculation module and a stability judgment module, tests the stability of the internal power supply of the chip before the chip works, does not need to test on the ATE machine as in the prior art, reduces the test cost, improves the actual benefit of the chip product, improves the chip test efficiency and accuracy, and avoids that the stability of the LDO circuit after the chip works cannot be accurately tested with the prolongation of the working time of the chip, the present application enables the chip to self-detect the stability of the LDO before each work, which can greatly ensure the reliability of the chip to avoid disastrous losses. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 It is a structure schematic view of a chip stability self-detection circuit provided by the embodiment of the present application.

[0063] Figure 2 Figure 1 is a structural diagram of a linear feedback shift register provided by an embodiment of the present application;

[0064] Figure 3 Figure 2 is a diagram of a pseudo-random sequence generated by the LFSR output provided by an embodiment of the present application;

[0065] Figure 4 Figure 3 is a structural diagram of an LDO circuit in a chip stability self-detection circuit provided by an embodiment of the present application;

[0066] Figure 5 Figure 4 is a step flowchart of a chip stability self-detection method provided by an embodiment of the present application;

[0067] Figure 6 Figure 5 is a diagram of an LFSR autocorrelation result provided by an embodiment of the present application;

[0068] Figure 7 Figure 6 is a diagram of a small signal equivalent circuit of an operational amplifier provided by an embodiment of the present application;

[0069] Figure 8 Figure 7 is a diagram of a small signal equivalent circuit of a PMOS switch provided by an embodiment of the present application;

[0070] Figure 9 Figure 8 is a diagram of a small signal equivalent circuit of a feedback circuit provided by an embodiment of the present application;

[0071] Figure 10 Figure 9 is a diagram of an under-damped system impulse response waveform provided by an embodiment of the present application;

[0072] Figure 11 Figure 10 is a diagram of an over-damped system impulse response waveform provided by an embodiment of the present application. DETAILED DESCRIPTION

[0073] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0074] Embodiment One

[0075] Please refer to Figure 1The self-detection circuit for chip stability provided by the embodiment of the present application comprises: an LDO circuit 01, a linear feedback shift register 02, an ADC sampling circuit 03, a register conversion stage module 04, a damping ratio calculation module 05, a phase margin calculation module 06, and a stability judgment module 07.

[0076] It should be noted that the ADC sampling circuit 03, the register conversion stage module 04, the damping ratio calculation module 05, the phase margin calculation module 06, and the stability judgment module 07 are circuit sub-modules in the embodiment of the present application. The output of the LDO is sampled by the ADC sampling circuit 03, and is input into the register conversion stage module 04 to perform a correlation operation on the input and output of the LDO. The result obtained is the impulse response of the LDO circuit 01 system. The damping ratio of the LDO system is calculated through the impulse response function. Finally, the phase margin of the LDO system is calculated through the damping ratio, so as to judge the stability of the LDO system through the phase margin.

[0077] Further, the register conversion stage module 04 is configured to calculate the impulse response of the LDO circuit 01 according to the sampled output of the LDO circuit 01. The damping ratio calculation module 05 is configured to calculate the damping ratio of the LDO circuit 01 according to the impulse response. The phase margin calculation module 06 is configured to calculate the phase margin of the LDO circuit 01 according to the damping ratio of the LDO circuit 01. The stability judgment module 07 is configured to judge whether the LDO circuit 01 is in a stable state according to the phase margin.

[0078] The output end of the linear feedback shift register 02 is connected with the input end of the LDO circuit 01. The input end of the LDO circuit 01 is also connected with a reference voltage. The output end of the LDO circuit 01 is connected with the input end of the ADC sampling circuit 03.

[0079] In the embodiment, preferably, the linear feedback shift register is a 10-bit LFSR. Please refer to Figure 2 which is a structural schematic diagram of the 10-bit LFSR in the embodiment of the present application. The 10-bit linear feedback shift register can generate a 1023-bit pseudo-random sequence. Further, in the embodiment, any n-bit LFSR can be used, and the larger n is, the better the effect is. For the n-bit LFSR, a 2 n bit pseudo-random sequence can be generated. Please refer to Figure 3 which is a pseudo-random sequence generated by the output of the 10-bit LFSR.

[0080] The output end of the ADC sampling circuit is connected to the first input end of the register conversion stage module 04, the second input end of the register conversion stage module 04 is connected to the input end of the LDO circuit 01, the output end of the register conversion stage module 04 is connected to the input end of the damping ratio calculation module 05, the output end of the damping ratio calculation module 05 is connected to the input end of the phase margin calculation module 06, and the output end of the phase margin calculation module 06 is connected to the stability judgment module 07.

[0081] It should be noted that the second input end of the register conversion stage module 04 is connected to the input end of the LDO circuit 01, which is mainly for signal sampling of the input end of the LDO circuit 01, that is, collecting the input of the LDO circuit 01, so as to perform signal correlation operation with the output of the LDO circuit 01, so as to obtain the impulse response of the LDO circuit 01 system. The correlation operation is realized by a series of simple adders and multipliers, that is, the register conversion stage module 04 can be realized by a digital RTL circuit.

[0082] As a preferred scheme of the embodiment, please refer to Figure 4 , the LDO circuit 01 includes a transmission gate circuit, an operational amplifier AMP, a PMOS switch tube, a third resistor R3 and a fourth resistor R4.

[0083] The gate of the PMOS switch tube is connected to the output end of the operational amplifier AMP, the source of the PMOS switch tube is connected to a source voltage, the drain of the PMOS switch tube is connected to the input end of the ADC sampling circuit 03 and the third resistor R3, the second input end of the operational amplifier AMP is connected to the third resistor R3, and the third resistor R3 is also connected to the fourth resistor R4.

[0084] The first input end of the transmission gate circuit is connected to the reference voltage, the second input end of the transmission gate circuit is connected to the output end of the linear feedback shift register 02, the output end of the transmission gate circuit is connected to the first input end of the operational amplifier AMP, and the second input end of the register conversion stage module 04 is connected to the first input end of the operational amplifier AMP.

[0085] As a preferred scheme of the embodiment, please refer to Figure 4 , the transmission gate circuit includes a first transmission gate TG1, a second transmission gate TG2, an inverter INV, a first resistor R1 and a second resistor R2.

[0086] The first input end of the first transfer gate TG1 is connected to the reference voltage, the second input end of the first transfer gate TG1 is connected to the output end of the linear feedback shift register 02, the third input end of the first transfer gate TG1 is connected to the output end of the inverter INV, the input end of the inverter INV is connected to the output end of the linear feedback shift register 02, and the output end of the first transfer gate TG1 is connected to the first input end of the operational amplifier AMP.

[0087] The first input end of the second transfer gate TG2 is connected to the reference voltage through the first resistor, and the first resistor R1 is also connected with the second resistor R2.

[0088] The second input end of the second transfer gate TG2 is connected to the output end of the inverter INV, the third input end of the second transfer gate TG2 is connected to the output end of the linear feedback shift register 02, and the output end of the second transfer gate TG2 is connected to the first input end of the operational amplifier AMP.

[0089] In the embodiment, when the LFSR output OUT is high, the first transfer gate TG1 is opened, the second transfer gate TG2 is closed, and the input voltage of the LDO is Vref (the first reference voltage). When the LFSR output OUT is low, the second transfer gate TG2 is opened, the first transfer gate TG1 is closed, and the input voltage of the LDO is Vref (R2 / R1+R2) (the second reference voltage). Further, the second reference voltage Vref (R2 / R1+R2) is large enough to keep the normal operation of the LDO circuit 01.

[0090] The above embodiment has the following effects:

[0091] The technical scheme of the present application improves the LDO circuit, sets up a self-test circuit in the chip, adds a linear feedback shift register, an ADC sampling circuit, a register conversion stage module, a damping ratio calculation module, a phase margin calculation module and a stability judgment module, tests the stability of the internal power supply of the chip before the chip works, does not need to test on the ATE machine as in the prior art, reduces the test cost, improves the actual benefit of the chip product, avoids the situation that the stability of the LDO circuit after the chip works cannot be accurately tested with the extension of the working time of the chip, the present application enables the chip to self-test the stability of the LDO before each work, which can greatly ensure the reliability of the chip to avoid disastrous losses, and is used for realizing the self-detection of the chip.

[0092] Embodiment two

[0093] Please refer to Figure 5The application further provides a self-detection method for chip stability, which is automatically performed before the chip works, and comprises the following steps S101-S104:

[0094] Step S101: sampling an output end of an LDO circuit inside the chip, and obtaining a pulse response of the LDO circuit according to the LDO circuit output obtained by sampling.

[0095] As a preferred scheme of the embodiment, before the sampling of the output end of the LDO circuit inside the chip, the method further comprises:

[0096] The output value of a linear feedback shift register inside the chip is input into the LDO circuit; when the output value of the linear feedback shift register is high, the input voltage of the LDO circuit is a first reference voltage, and a pseudo-random sequence generated by the linear feedback shift register is input into the LDO circuit; when the output value of the linear feedback shift register is low, the input voltage of the LDO circuit is a second reference voltage, and the pseudo-random sequence generated by the linear feedback shift register is input into the LDO circuit.

[0097] In the embodiment, when the output OUT of the linear feedback shift register LFSR is high, the first transmission gate TG1 is opened, the transmission gate TG2 is closed, and the input voltage of the LDO is the first reference voltage Vref. When the output OUT of the LFSR is low, the second transmission gate TG2 is opened, the first transmission gate TG1 is closed, and the input voltage of the LDO is the second reference voltage Vref(R2 / R1+R2). The size of the second reference voltage Vref(R2 / R1+R2) should be able to maintain the normal work of the LDO circuit. At the same time, the pseudo-random sequence output by the LFSR is added to the input end of the LDO circuit. Preferably, the 10bit LFSR in the embodiment can generate a 1023bit pseudo-random sequence.

[0098] As a preferred scheme of the embodiment, the ratio of the second reference voltage to the first reference voltage is R2 / R1+R2; wherein R1 is a first resistance in the LDO circuit, R2 is a second resistance in the LDO circuit, and the first reference voltage and the second reference voltage are both within a preset voltage range input for the normal work of the LDO circuit.

[0099] As a preferred scheme of the embodiment, the sampling of the output end of the LDO circuit inside the chip and the obtaining of the pulse response of the LDO circuit according to the LDO circuit output obtained by sampling are specifically:

[0100] The input signal of the LDO circuit is obtained by combining the reference voltage input by the LDO circuit and the pseudo-random sequence, and the pseudo-random sequence is taken as a white noise signal of the input end of the LDO circuit; wherein the reference voltage is a first reference voltage or a second reference voltage; the output voltage of the LDO circuit in the chip is sampled through the ADC sampling circuit output; the signal correlation result is calculated according to the input signal, the sampled LDO circuit output signal and the white noise signal; and the impulse response of the LDO circuit is calculated according to the signal correlation result.

[0101] In the embodiment, the LDO output value and the pseudo-random sequence of the LFSR are obtained through ADC sampling, and the signal correlation result operation is performed on the LDO circuit output value and the set input voltage value (reference voltage V ref ), so as to calculate the impulse response function of the LDO circuit system.

[0102] As a preferred scheme of the embodiment, the calculation manner of the signal correlation result is:

[0103]

[0104]

[0105] R yu (m)=h(n)+C

[0106] Wherein, h(n) is the impulse response of the LDO circuit, C is a constant, V ref is the reference voltage, V LFSR (n) is the pseudo-random sequence, u(n) is the input signal of the LDO circuit, y(n) is the output signal of the LDO circuit, and h(k) is the impulse response when the independent variable is k.

[0107] In the embodiment, the signal correlation result operation is realized by a series of simple adders and multipliers, and can be realized by a digital RTL circuit. The result of the correlation operation between the LDO output value and the LDO input value is the system impulse response h(n), and the specific theoretical derivation is as follows:

[0108] u(n)=V ref +V LFSR (n)

[0109]

[0110] h(n) is the impulse response function of the LDO, u(n) is the input of the LDO, that is, the pseudo-random sequence V LFSR (n) output by the LFSR plus the reference voltage V ref, v(n) is the white noise signal of the LDO output end, and N is the length of the pseudo-random sequence output by the LFSR. The convolution result of u(n) and h(n) is the output voltage y(n) of the LDO. Then, the correlation operation is performed on the LDO output y(n) and the LDO input u(n), and the signal correlation result R yu (n) is obtained.

[0111] Further, since the autocorrelation function of the white noise signal is an impulse signal δ(n), and the correlation result with other signals is 0, the embodiment uses the pseudo-random sequence V LFSR (n) output by the LFSR to simulate the white noise. The R uv (n) = 0, R yu (m) = h(n) + C (C is a constant, which does not affect the stability of the system, and can be ignored for convenience of analysis) can be calculated by the above formula. Therefore, the impulse response can be obtained by performing the correlation operation on the value output by the LDO and the value input by the LDO.

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120] In the embodiment, please refer to Figure 6 , which is the autocorrelation result of the 10-bit LFSR. It can be seen that the pseudo-random sequence output by the LFSR has very similar characteristics to the white noise, and therefore the pseudo-random sequence V LFSR (n) output by the LFSR can be used to simulate the white noise.

[0121] Step S102: According to the impulse response, the damping ratio of the LDO circuit is calculated, and according to the damping ratio, the phase margin of the LDO circuit is calculated.

[0122] As a preferred scheme of the embodiment, before the damping ratio of the LDO circuit is calculated according to the impulse response, the method further includes:

[0123] Small signal analysis is performed on the operational amplifier, the PMOS switch tube and the feedback circuit in the LDO circuit to obtain a small signal model of the operational amplifier and the PMOS switch tube respectively; wherein the feedback circuit is a third resistor and a fourth resistor; a first pole of a transmission signal is obtained according to the small signal model of the operational amplifier; a second pole and a zero of the transmission signal are obtained according to the small signal model of the PMOS switch tube; a third pole of the transmission signal is obtained according to the small signal model of the feedback circuit; the LDO circuit is approximated as a second order system according to the first pole, the second pole, the third pole and the zero, and a category of the second order system is determined; the category of the second order system includes an under-damped system and an over-damped system.

[0124] It should be noted that, before solving the damping ratio of the LDO system, signal analysis needs to be performed on the LDO circuit system. In the embodiment, the signal analysis of the LDO system mainly consists of three parts: 1, the operational amplifier; 2, the PMOS switch tube; 3, the feedback circuit (the feedback circuit composed of the third resistor and the fourth resistor). First, small signal analysis is performed on the operational amplifier, and the small signal model thereof is Figure 7 The equivalent circuit composed of the input voltage, the resistor, the capacitor and the input voltage of gm1 can obtain a transmission function thereof as formula:

[0125] H(s)=Vout / Vin=g m1 R1 / (1+sR1C1)

[0126] The first pole can be obtained based on the above formula.

[0127] Secondly, small signal analysis is performed on the PMOS switch tube, and the small signal model thereof is Figure 8 The equivalent circuit composed of the input voltage, the input voltage resistor, the gate-source capacitor, the gate-drain capacitor, the gate-source voltage of gm1, the resistor and the capacitor can obtain a transmission function thereof as formula:

[0128] (sC gd -g m )Vgs=(1 / R out +sC out +sC gd )Vout

[0129] H(s)=Vout / Vgs=(-g m1 R1)(1-s(C gd / g m )) / (1+s(C out +C gd )*R out )

[0130] The second pole and a zero can be obtained based on the above formula.

[0131] Finally, the feedback circuit is analyzed in small signal, and the small signal model is Figure 9 The equivalent circuit composed of CF1 capacitor and RF1 resistor, RF2 resistor can be obtained, and its transfer function is formula:

[0132] H(s) = V F / V out = 1 / (sC F1 +1 / R F2 ) / (1 / (sC F1 +1 / R F2 )+R F1 )

[0133] H(s) = 1 / (1+R F1 (sC F1 +1 / R F2 ))

[0134] H(s) = R F2 / (R F2 +R F1 )*(R F2 +R F1 ) / (R F1 (sC F1 R F2 +1)+R F2 )

[0135] H(s) = R F2 / (R F2 +R F1 )*1 / (1+sC F1 (R F2 / / R F2 ))

[0136] Based on the above formula, the third pole point can be obtained. Therefore, the LDO circuit system in the embodiment roughly exists three pole points and one zero point.

[0137] Further, please refer to Table 1, which is a summary table of zero pole distribution of each module in the LDO circuit system:

[0138] LDO module transfer function and zero pole

[0139]

[0140] Table 1 Summary table of zero pole distribution of each module in the LDO circuit system

[0141] In the embodiment, it is known from the above analysis of the LDO circuit that the LDO can be represented by a second-order system. The second-order system includes an over-damped system and an under-damped system, but the method for solving the damping ratio of the over-damped system and the under-damped system through the impulse response is different.

[0142] As a preferred scheme of the embodiment, the damping ratio of the LDO circuit is calculated according to the impulse response, and specifically:

[0143] If the second-order system is an under-damped system, a first unit impulse response function is calculated through the transfer function of the second-order system and the impulse response, and the damping ratio of the LDO circuit when the LDO circuit is an under-damped system is calculated according to a preset function abscissa position; wherein the damping ratio of the LDO circuit when the LDO circuit is an under-damped system ranges from 0 to 1.

[0144] As a preferred scheme of the embodiment, the damping ratio of the LDO circuit when the LDO circuit is an under-damped system is calculated in the following manner:

[0145]

[0146]

[0147] wherein ζ is the damping ratio, h(n1 / 6) and h(n1 / 2) are the first unit impulse response functions at two preset function abscissa positions.

[0148] In the embodiment, for the LDO of the under-damped system (0 < damping ratio < 1), a typical second-order system is represented by the following formula: wherein ζ is the damping ratio, w n is the undamped natural frequency. The transfer function of the system should be:

[0149] H(s) = G(s) / (1+G(s))

[0150]

[0151] The inverse Laplace transform of the above formula is performed to obtain the unit impulse response function h(t) of the system:

[0152]

[0153]

[0154] Let

[0155]

[0156] wherein the waveform is as shown in Figure 10The second horizontal coordinate value n1 crossing 0 is recorded, and n1 is For convenience of calculation, preferably, 1 / 2 and 1 / 6 of n1 are taken, h(n1 / 2) and h(n1 / 6) are obtained by bringing the impulse response, and the damping ratio can be calculated by the following formula:

[0157]

[0158]

[0159] Let M = 3 / π*ln(2h(n1 / 6) / h(n1 / 2))

[0160]

[0161]

[0162] The advantage of taking 1 / 2 and 1 / 6 of n1 is that sin(π / 2) = 1 and sin(π / 6) = 0.5 are rational numbers, the circuit implementation is simple, and the calculation accuracy of h(n1 / 2) and h(n1 / 6) is high. Other points are irrational numbers and can only be approximated, and the circuit implementation is troublesome.

[0163] Further, if the second-order system is an over-damped system, the second-order differential equation of the second-order system is defined, and the second unit impulse response function is calculated according to the impulse response, so as to obtain the inflection point horizontal coordinate position and the intersection point of the tangent line and the horizontal coordinate through the derivative of the second unit impulse response function, and then the damping ratio of the LDO circuit when the LDO circuit is an over-damped system is calculated; wherein the damping ratio of the LDO circuit when the LDO circuit is an over-damped system ranges from (1, +∞).

[0164] As a preferred scheme of the embodiment, the calculation method of the damping ratio of the LDO circuit when the LDO circuit is an over-damped system is:

[0165]

[0166]

[0167] Wherein, ζ is the damping ratio, t i and t T are the point of the inflection point horizontal coordinate position and the intersection point of the tangent line and the horizontal coordinate, respectively, t A and t B are any two points in the second unit impulse response function, x(t A ) and x(t B ) are the second unit impulse response functions corresponding to the point t A and the point t B .

[0168] In this embodiment, for LDO of over-damped system (damping ratio > 1). With the standard form of second-order differential equation, the unit impulse response h(t) of the system can be obtained by the following formula:

[0169] ζ: damping ratio w n : undamped natural frequency

[0170] (characteristic variance)

[0171]

[0172]

[0173] Further, since the LDO circuit system is a causal system, x(0) = 0, set the derivative of the impulse response x(t) at 0 time as v, and bring it into h(t) to get the result as shown below, the waveform is approximately as Figure 11 :

[0174]

[0175] sinh w d t (where )

[0176] Preferably, take the value of the time when the maximum value of the impulse response as t m , take twice t m as t i , calculate t i as the abscissa of the inflection point by the following formula:

[0177] Stationary point:

[0178] Inflection point:

[0179]

[0180] tanh(2*w d t m ) = tanh(w d t i )

[0181] 2t m = t i

[0182] At the same time, the intersection of the tangent line and the abscissa of the inflection point t i is t T , let T = t T - t i , as shown in the following formula:

[0183]

[0184]

[0185] 2ζ / w n =t T -t i (Let T = t) T -t i )

[0186] Choose any two larger points t A t B The damping ratio can be calculated using the following formula.

[0187] because sinh w d t( Damped vibration angular frequency)

[0188]

[0189] make (where w2>w1>0)

[0190] (Ignore w2 item)

[0191] When the selected t A t B When larger:

[0192]

[0193]

[0194] because

[0195]

[0196]

[0197] In a preferred embodiment, the step of calculating the phase margin of the LDO circuit based on the damping ratio specifically involves:

[0198] By defining the second-order system and its amplitude, and based on the damping ratio, the phase margin of the LDO circuit is calculated: Where PM is the phase margin and ζ is the damping ratio.

[0199] In this embodiment, the phase margin can be calculated using the damping ratio of the LDO circuit system, thereby determining the system's stability. A typical second-order system is assumed to be: ξ is the damping ratio, w n is the undamped natural frequency. Its magnitude is:

[0200] Further, since the phase margin is defined as the difference between the phase value of the LDO circuit system and 180° when the amplitude gain is 1. Therefore, by letting the amplitude gain be 1, W c :

[0201]

[0202]

[0203] W c is brought into the following formula, the phase margin of the LDO circuit system can be obtained:

[0204] ∠G(jw c ) = arctan(2ζw n / w c )

[0205]

[0206] Further, through simulation test of the LDO stability self-detection circuit, the following experimental data is obtained:

[0207]

[0208] Table 2: Experimental data of under-damped system

[0209]

[0210] Table 3: Experimental data of over-damped system

[0211] It can be understood that the phase margin of the LDO circuit system is determined by the damping ratio, and has nothing to do with the undamped natural frequency. The estimated value of the experimental result is affected to some extent by the undamped natural frequency, because the error in the taking point and the measurement leads to it. According to the experimental results, the error value of both the over-damped system and the under-damped system is within 2°, so the above errors are all within an acceptable range.

[0212] Step S103: When the phase margin is greater than the preset angle, it is judged that the LDO circuit is in a stable state.

[0213] It should be noted that generally the phase margin is greater than 45° before the system is considered to be stable, and if the phase margin is less than 45°, the system is considered to be unstable. Preferably, the preset angle in the embodiment is 45°; when the phase margin is greater than 45°, the chip is allowed to work and run normally.

[0214] Step S104: When the phase margin is less than or equal to the preset angle, it is determined that the LDO circuit is in an unstable state.

[0215] It should be noted that, since the phase margin is less than 45°, it indicates that the LDO circuit system of the chip is unstable, which is easy to cause operation error, so as to cause the chip function to be blocked, unable to realize normal chip operation and running operation, and the reliability of the chip is low, thereby generating a chip fault signal to warn.

[0216] It can be understood that, in the embodiment, the self-detection method of the stability of the chip is executed before each running and working of the chip through the self-detection circuit of the embodiment, so as to avoid the prior LDO stability test which can only be performed when the chip is taped out, and the embodiment can greatly ensure the reliability of the chip to avoid disastrous loss.

[0217] The above embodiments have the following effects:

[0218] At present, the test cost of most chips accounts for more than 20% of the chip production cost, and if the test cost can be reduced, the product revenue can be greatly improved. Since the present application is an LDO system self-test circuit, the chip can automatically detect the stability of the internal LDO system of the chip. Therefore, it is not necessary to test the stability of the LDO on the ATE machine, which will reduce the test cost. At the same time, the chip can self-detect the stability of the LDO before each working, so as to greatly ensure the reliability of the chip to avoid disastrous loss.

[0219] Further, the self-detection method performed by the chip can quickly and simply test the LDO stability of the chip, improve the chip test efficiency, calculate the corresponding damping ratio and phase margin through the over-damped and under-damped systems, improve the accuracy of the prior chip LDO stability test, and make the chip have high reliability.

[0220] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only for specific embodiments of the present application and is not used to limit the protection scope of the present application. It is particularly pointed out that, for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of self-checking of chip stability, characterized in that, The chip is automatically executed before working, including: sampling the output end of the LDO circuit inside the chip, and obtaining the impulse response of the LDO circuit according to the LDO circuit output obtained by sampling; calculating the damping ratio of the LDO circuit according to the impulse response, and calculating the phase margin of the LDO circuit according to the damping ratio; when the phase margin is greater than a preset angle, it is judged that the LDO circuit is in a stable state; when the phase margin is less than or equal to the preset angle, it is judged that the LDO circuit is in an unstable state; wherein, before the sampling of the output end of the LDO circuit inside the chip, it further includes: inputting the output value of the linear feedback shift register inside the chip into the LDO circuit; when the output value of the linear feedback shift register is high, the input voltage of the LDO circuit is a first reference voltage, and the pseudo-random sequence generated by the linear feedback shift register is input into the LDO circuit; when the output value of the linear feedback shift register is low, the input voltage of the LDO circuit is a second reference voltage, and the pseudo-random sequence generated by the linear feedback shift register is input into the LDO circuit.

2. The method of claim 1, wherein the step of detecting the chip stability comprises the steps of: determining whether the chip stability is maintained; and if the chip stability is not maintained, then outputting a chip stability failure signal. The ratio of the second reference voltage to the first reference voltage is R2 / R1+R2; wherein, R1 is a first resistance in the LDO circuit, R2 is a second resistance in the LDO circuit, and the first reference voltage and the second reference voltage are both within the preset voltage range input by the normal working of the LDO circuit.

3. A method of self-testing the stability of a chip as claimed in claim 1 or 2, characterized in that, The sampling of the output end of the LDO circuit inside the chip and the obtaining of the impulse response of the LDO circuit according to the LDO circuit output obtained by sampling are specifically: combining the reference voltage input by the LDO circuit and the pseudo-random sequence to obtain the input signal of the LDO circuit, and taking the pseudo-random sequence as the white noise signal of the input end of the LDO circuit; wherein the reference voltage is a first reference voltage or a second reference voltage; sampling the output voltage of the LDO circuit inside the chip through the ADC sampling circuit output; calculating the signal correlation result according to the input signal, the sampled LDO circuit output signal and the white noise signal; calculating the impulse response of the LDO circuit according to the signal correlation result.

4. The method of claim 3, wherein the step of determining the stability of the chip is performed by the steps of: The calculation method of the signal correlation result is: ​ wherein, is the impulse response of the LDO circuit, is a constant, is a reference voltage, is a pseudo-random sequence, is the input signal of the LDO circuit, is the output signal of the LDO circuit, is the impulse response when the argument is k.

5. The method of claim 1, wherein the step of detecting the stability of the chip is characterized by, before the calculation of the damping ratio of the LDO circuit according to the impulse response, it further includes: small signal analysis is performed on the operational amplifier, PMOS switch tube and feedback circuit in the LDO circuit to obtain small signal models of the operational amplifier and PMOS switch tube respectively; wherein the feedback circuit is a third resistance and a fourth resistance component; according to the small signal model of the operational amplifier, a first pole of the transmission signal is obtained; according to the small signal model of the PMOS switch tube, a second pole and a zero point of the transmission signal are obtained; according to the small signal model of the feedback circuit, a third pole of the transmission signal is obtained; According to the first pole, the second pole, the third pole and the zero point, the LDO circuit is approximated as a second-order system, and a category of the second-order system is determined; the category of the second-order system includes an under-damped system and an over-damped system.

6. A method of self-testing the stability of a chip as claimed in claim 5, characterized in that, The damping ratio of the LDO circuit is calculated according to the impulse response, specifically as follows: If the second-order system is an under-damped system, a first unit impulse response function is calculated through a transfer function of the second-order system and the impulse response, and the damping ratio of the LDO circuit when the LDO circuit is an under-damped system is calculated according to a preset function horizontal coordinate position; wherein the damping ratio of the LDO circuit when the LDO circuit is an under-damped system ranges from (0, 1); If the second-order system is an over-damped system, a second unit impulse response function is calculated through a second-order differential equation of the second-order system and according to the impulse response, so as to obtain an inflection point horizontal coordinate position and a tangent horizontal coordinate intersection through a derivative of the second unit impulse response function, and then the damping ratio of the LDO circuit when the LDO circuit is an over-damped system is calculated; wherein the damping ratio of the LDO circuit when the LDO circuit is an over-damped system ranges from (1, +∞).

7. A method for self-testing of chip stability as claimed in claim 6, wherein, The calculation method of the damping ratio of the LDO circuit when the LDO circuit is an under-damped system is as follows: wherein, is the damping ratio, and are the first unit impulse response functions at the preset function abscissa positions, respectively.

8. The method of claim 6, wherein the step of determining the stability of the chip is performed by the steps of: The calculation method of the damping ratio of the LDO circuit when the LDO circuit is an over-damped system is as follows: ​ wherein, is the damping ratio, and are the point of the inflection abscissa position and the intersection of the tangent and the abscissa, respectively, and are any two points in the second unit impulse response function, respectively, and are the points and corresponding second unit impulse response function.

9. A method of self-testing the stability of a chip as claimed in any one of claims 5 to 8, wherein, The phase margin of the LDO circuit is calculated according to the damping ratio, specifically as follows: The phase margin of the LDO circuit is calculated according to the damping ratio and through definition of the second-order system and amplitude: wherein is the phase margin, is the damping ratio.

10. A self-checking circuit for chip stability, characterized by It comprises: An LDO circuit, a linear feedback shift register, an ADC sampling circuit, a register conversion stage module, a damping ratio calculation module, a phase margin calculation module and a stability determination module. An output end of the linear feedback shift register is connected with an input end of the LDO circuit, the input end of the LDO circuit is also connected with a reference voltage, and an output end of the LDO circuit is connected with an input end of the ADC sampling circuit. An output end of the ADC sampling circuit is connected with a first input end of the register conversion stage module, a second input end of the register conversion stage module is connected with an input end of the LDO circuit, an output end of the register conversion stage module is connected with an input end of the damping ratio calculation module, an output end of the damping ratio calculation module is connected with an input end of the phase margin calculation module, and an output end of the phase margin calculation module is connected into the stability determination module.

11. A self-test circuit for chip stability as defined in claim 10, wherein, The LDO circuit comprises a transmission gate circuit, an operational amplifier, a PMOS switch tube, a third resistor and a fourth resistor. A gate of the PMOS switch tube is connected with an output end of the operational amplifier, a source of the PMOS switch tube is connected with a source voltage, a drain of the PMOS switch tube is connected with an input end of the ADC sampling circuit and the third resistor, a second input end of the operational amplifier is connected with the third resistor, and the third resistor is also connected with the fourth resistor. The first input end of the transmission gate circuit is connected to the reference voltage, the second input end of the transmission gate circuit is connected to the output end of the linear feedback shift register, the output end of the transmission gate circuit is connected to the first input end of the operational amplifier, and the second input end of the register conversion stage module is connected to the first input end of the operational amplifier.

12. A self-test circuit for chip stability as defined in claim 11, wherein, The transmission gate circuit comprises a first transmission gate, a second transmission gate, an inverter, a first resistor and a second resistor. The first input end of the first transmission gate is connected to the reference voltage, the second input end of the first transmission gate is connected to the output end of the linear feedback shift register, the third input end of the first transmission gate is connected to the output end of the inverter, the input end of the inverter is connected to the output end of the linear feedback shift register, and the output end of the first transmission gate is connected to the first input end of the operational amplifier. The first input end of the second transmission gate is connected to the reference voltage through the first resistor, and the first resistor is also connected with the second resistor. The second input end of the second transmission gate is connected to the output end of the inverter, the third input end of the second transmission gate is connected to the output end of the linear feedback shift register, and the output end of the second transmission gate is connected to the first input end of the operational amplifier.

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