A chip testing system and method

Abstract

The application discloses a chip testing system, and relates to the chip detection field.The system comprises a host computer, a program-controlled power supply, a real installation test board, a ZYNQ master control chip, a chip to be tested, a power supply chip module and a communication serial port module.The ZYNQ master control chip and the chip to be tested are connected through a first bus and a second bus, and the ZYNQ master control chip is connected with the host computer through the communication serial port module.The power supply chip module is connected with the host computer through the program-controlled power supply, and is connected with the ZYNQ master control chip and the chip to be tested respectively.The host computer is used for sending a test instruction to the ZYNQ master control chip through the communication serial port module, controlling the system to enter a DFT mode or a real installation mode, and testing the chip to be tested.The system utilizes the parallel capability of a PL / FPGA and the real installation function of a PS / ARM in the ZYNQ chip, integrates the functions of an ATE test board and the real installation test board, does not need to repeatedly load in the testing process, reduces the testing period, and greatly improves the testing efficiency.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to a chip testing system and method. Background Technology

[0002] In the chip manufacturing process, after chip production is complete, the chips need to undergo pre-shipment testing by the testing department to ensure that all modules and functions of the chip operate normally. The tests include at least interrupt, serial port, reset, GPIO, and memory functions.

[0003] Currently, chip testing mainly consists of two parts: 1. Functional and performance testing on an ATE (Automatic Test Equipment) machine using an ATE test board; 2. Functional testing on an actual functional testing system. In other words, completing a full chip testing process requires at least two test systems. This necessitates loading and unloading the chip between two machines, and the intermediate loading, unloading, and restarting processes prolong the entire testing cycle. The process is cumbersome, and the test programs required for the ATE machines are difficult to develop and time-consuming, making it unsuitable for testing large quantities of chips. Summary of the Invention

[0004] This application provides a chip testing system that solves the problems of long testing cycles and cumbersome testing processes. The system includes a host computer, a programmable power supply, a test board, a ZYNQ main control chip mounted on the test board, a chip under test, a power supply chip module, and a communication serial port module.

[0005] The ZYNQ main control chip and the chip under test are interconnected via a first bus and a second bus. The ZYNQ main control chip communicates with the host computer via the communication serial port module. The power chip module is connected to the host computer via the programmable power supply, and the power chip module is connected to both the ZYNQ main control chip and the chip under test for system power supply.

[0006] The host computer is used to send test commands to the ZYNQ main control chip through the communication serial port module, control the system to enter scan chain DFT mode or physical mode, and test the chip under test;

[0007] The first bus is used for data interaction in DFT mode, and the second bus is used for data interaction in physical mode.

[0008] Specifically, the test board also has onboard DDR memory, a first flash memory, a second flash memory, and two reset circuit modules;

[0009] The DDR memory and the first flash memory are respectively connected to the ZYNQ main control chip, the second flash memory and the chip under test, and the chip under test and the ZYNQ main control chip are respectively connected to a reset circuit module for chip initialization;

[0010] The first flash memory stores programs for DFT mode and physical mode, while the second flash memory stores programs that the chip under test needs to run in physical mode.

[0011] Specifically, the ZYNQ main control chip is also connected to a first JTAG interface, and the chip under test is also connected to a second JTAG interface, which are used to burn test programs to the corresponding flash memory of their respective chips.

[0012] Specifically, the power chip module is also connected to a current limiting and overvoltage protection module, and the programmable power supply is connected to the power chip module via a GPIB interface.

[0013] Specifically, in the system test mode, the host computer issues DFT and implementation commands. In DFT mode, the ZYNQ main control chip initiates a parallel scan of several circuits in the chip under test through the parallel function of its PL / FPGA. In implementation mode, the ZYNQ main control chip performs implementation function tests on the chip under test by running the implementation function test program in its PS / ARM and the chip under test.

[0014] Specifically, when the system enters DFT mode, the ZYNQ main control chip reads the DFT scan chain program in the first flash memory, moves it to the DDR memory connected to it for execution, and performs DFT scan on the chip under test through the first bus.

[0015] The ZYNQ main control chip applies test excitation signals from each functional module to the output pins of the chip under test, and receives feedback signals output by the chip under test;

[0016] The ZYNQ main control chip collects and compares the test excitation signal and feedback signal, counts the number of errors and the error rate, and reports the statistical results to the host computer for data processing and display of test data.

[0017] Specifically, when the system enters the implementation mode, the ZYNQ main control chip reads the implementation test program from the first flash memory, moves it to the connected DDR memory for execution, and controls the chip under test to run the implementation test program through the second bus.

[0018] The ZYNQ main control chip interacts with the chip under test to test whether the chip under test is functioning properly in various functions.

[0019] The ZYNQ main control chip reports the test results of various functions to the host computer for display and data processing.

[0020] Specifically, after the host computer sends a DFT command or an implementation command to the ZYNQ main control chip, it detects and displays the system voltage and current through the current limiting and overvoltage protection module; when the system voltage or current exceeds the normal value, it shuts down the programmable power supply and ends the test.

[0021] The beneficial effects of the technical solution provided in this application include at least the following: This system replaces the traditional ATE test board and physical test board with a test system composed of a host computer, ZYNQ main control chip, programmable power supply and physical test board. It integrates the functions of the ATE test board and physical test board, and uses two buses as the lines for testing and data interaction in DFT mode and physical mode respectively. The host computer issues commands to arbitrarily control the test mode of the system, so the test process does not require repeated loading, reducing the test cycle and greatly improving the test efficiency. Attached Figure Description

[0022] Figure 1 This is a structural diagram of an ATE test system used for DFT testing in related technologies;

[0023] Figure 2 This is a structural diagram of an installation test system used for practical functional testing in related technologies;

[0024] Figure 3 This is a system architecture diagram of the chip testing system provided in the embodiments of this application;

[0025] Figure 4 This is a circuit diagram of the chip testing system provided in the embodiments of this application;

[0026] Figure 5 This is a test flowchart in the DFT mode provided in the embodiments of this application;

[0027] Figure 6 This is a waveform diagram in DFT mode provided in the embodiments of this application;

[0028] Figure 7 This is a test flowchart in the implementation mode provided in the embodiments of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0030] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0031] Currently, chip testing is mainly divided into DFT testing and physical functional testing. DFT testing requires functional and performance testing on an ATE (Automatic Test Equipment) machine using an ATE test board. 2. Physical functional testing requires testing on a physical test board. Therefore, a complete chip testing process requires two test systems, and the development of test programs for the ATE machine is difficult and time-consuming. Figure 1 This is a structural diagram of an ATE test system used for DFT testing in related technologies. The chip under test generates test vectors based on the ATE machine and the ATE scan program on the ATE test board, which are then input into the chip under test for execution. Figure 2 This is a structural diagram of an actual test system used for actual functional testing in related technologies. This process requires the interaction of various test commands and data between the main control chip on the actual test board and the chip under test to test each function.

[0032] and Figure 3 This is a system architecture diagram of the chip testing system provided in this application embodiment. The system includes a host computer, a programmable power supply, a physical test board, a ZYNQ main control chip mounted on the physical test board, a chip under test (DUT), a power supply chip module, and a communication serial port module. The host computer and programmable power supply are connected to the physical test board to collect and display test data, and provide data processing and analysis. The ZYNQ main control chip is divided into two parts: PS and PL. The PL part contains 85K logic units, 4.9Mbits of embedded storage resources, and 220 DSP units. In addition, the chip also integrates two Cortex-A9 processors and the AMBA bus protocol. The ZYNQ main control chip and the DUT are interconnected through a first bus and a second bus. The first bus is used for data interaction between chips in DFT mode (DFT scan), and the second bus is used for data interaction between chips in physical mode. The test board also has an onboard communication serial port module, a JTAG interface, DDR memory, flash memory, a power supply chip module, a current limiting and overvoltage protection module, and a power-on and reset circuit module.

[0033] See its circuit diagram. Figure 4The ZYNQ main control chip communicates with the host computer via a serial communication module (DB9). The power supply module is connected to the host computer via a programmable power supply and is connected to both the ZYNQ main control chip and the chip under test (DUT), supplying power to both chips. The host computer sends test commands to the ZYNQ main control chip via the DB9 interface, controlling the system to enter either scan chain DFT mode or physical mode. The entire circuit structure is mounted on a physical test board, including DDR memory, a first flash memory (Flash1), a second flash memory (Flash2), and two reset circuit modules. The ZYNQ main control chip is connected to the DDR memory, the first flash memory, and a reset circuit module. The DUT is connected to the second flash memory and the other reset circuit module via a card slot. Furthermore, the two chips are also connected to a first JTAG interface (JTAG1) and a second JTAG interface (JTAG2), respectively. The first JTAG interface is used to program the ZYNQ main control chip in DFT mode and physical mode into the first flash memory, while the second JTAG interface is used to program the test chip in physical mode into the second flash memory.

[0034] The host computer in this solution is an x86 host computer. The programmable power supply needs to support the GPIB interface for control, and is responsible for controlling the test process and displaying and recording the test trajectory. The test board is based on the ZYNQ chip and the chip under test (DUT), with each building its own minimum system. The ZYNQ main control chip and the DUT interact through a custom bus to meet the test requirements. The power chip module is also connected to a current limiting and overvoltage protection module. Both the programmable power supply and the power chip module are connected via the GPIB interface. In DFT mode, the ZYNQ main control chip initiates a parallel scan of several circuits in the DUT through the parallel function of its PL / FPGA. In the actual function mode, the ZYNQ main control chip runs the actual function test program in its PS / ARM and the DUT to perform actual function testing on the DUT. When the system enters DFT mode, the specific steps are as follows:

[0035] S1, the ZYNQ main control chip reads the DFT scan chain program in the first flash memory, moves it to the DDR memory connected to it for execution, and performs DFT scan on the chip under test through the first bus;

[0036] S2, the ZYNQ main control chip applies test excitation signals from each functional module to the output pins of the chip under test, and receives feedback signals output by the chip under test;

[0037] The S3 ZYNQ main control chip collects and compares the test excitation signals and feedback signals, counts the number of errors and the error rate, and reports the statistical results to the host computer for data processing and display of test data.

[0038] After the host computer sends a DFT command to the ZYNQ main control chip, the system voltage and current are detected and displayed through the current limiting and overvoltage protection module. When the system voltage or current exceeds the normal value, the programmable power supply is turned off and the test ends. Figure 5 This is a test flowchart in DFT mode provided in this application embodiment. After the x86 host computer sends the command, it immediately detects the system's voltage and current, and promptly shuts down the programmable power supply in case of any abnormality. The test excitation signal is the input signal on the scan chain, and its waveform is as follows: Figure 6 As shown, taking a 5-way parallel scan chain as an example, the signal frequencies of these 5-way parallel scan chains are all adjustable.

[0039] When the system enters the implementation mode, the specific steps include the following:

[0040] S1, the ZYNQ main control chip reads the actual test program from the first flash memory, moves it to the DDR memory connected to it for execution, and controls the chip under test to run the actual test program through the second bus;

[0041] S2, the ZYNQ main control chip interacts with the chip under test to test whether the chip under test is functioning properly in each function;

[0042] The S3 ZYNQ main control chip reports the test results of various functions to the host computer for display and data processing.

[0043] Figure 7 This is a test flowchart in the implementation mode provided in the embodiment of this application. After the host computer sends the implementation command to the ZYNQ main control chip, the system voltage and current are detected and displayed through the current limiting and overvoltage protection module. When the system voltage or current exceeds the normal value, the programmable power supply is turned off and the test ends.

[0044] The practical test items include at least interrupt, serial port, reset, GPIO, and memory functions, depending on the functions of the chip under test. The corresponding test procedure is as follows:

[0045] 1. Serial Port: The ZYNQ chip performs serial port transmit / receive tests on the chip under test: It verifies the serial port function of the chip under test by using different baud rates, data bits, stop bits, and parity methods. For example, it performs several consecutive loop tests with a baud rate of 115200bps, 8 data bits, 1 stop bit, and even parity. If each test passes (the transmitted and received data are consistent), the serial port function of the chip under test is considered to have passed the test.

[0046] 2. Interrupt function: The ZYNQ chip outputs various interrupt signals (high level, low level, rising edge and falling edge) to the interrupt pin of the chip under test. After receiving the interrupt signal, the chip under test feeds back the corresponding output to the ZYNQ chip. After the ZYNQ chip collects the data, it determines whether the chip under test has responded correctly to the interrupt signal.

[0047] 3. Reset function: When the chip under test is running its program, the ZYNQ chip randomly sends a reset signal to the reset pin of the chip under test and determines whether the chip under test can complete the reset and continue running the program.

[0048] 4. GPIO Function: The chip under test (DUT) is configured with one set of GPIO pins for input mode and another set for output mode, and the signals on the input GPIO pins are transparently transmitted to the output GPIO pins. The ZYNQ chip outputs test signals to the GPIO input pins of the DUT and collects the feedback signals on the GPIO output pins of the DUT. If the collected signals are consistent with the test signals output by the ZYNQ chip, the GPIO input / output function is considered to be normal.

[0049] 5. Flash storage function: The ZYNQ chip sends the test pattern to the chip under test via serial port. The chip under test writes the test pattern into the Flash memory and reads it back. Then, it feeds back the read data to the ZYNQ chip via serial port. The ZYNQ chip compares the original test pattern with the data and repeats this process several times. If the data sent and received are consistent each time, the chip under test is considered to have passed the Flash storage function test.

[0050] When all the above functions are normal, the actual installation test is considered successful. If two mode switching tests on the same chip both pass, the chip test is confirmed to be normal.

[0051] In summary, this system replaces the traditional ATE test board and physical test board with a test system consisting of a host computer, ZYNQ main control chip, programmable power supply, and physical test board. It integrates the functions of the ATE test board and physical test board, and uses two buses as the lines for testing and data interaction in DFT mode and physical mode respectively. The host computer issues commands to arbitrarily control the test mode of the system, so there is no need for repeated loading during the test process, which reduces the test cycle and greatly improves the test efficiency.

[0052] The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above. The devices and structures not described in detail should be understood as being implemented in a conventional manner in the art. Any person skilled in the art can make many possible changes and modifications, or equivalent changes to equivalent embodiments without departing from the technical solution of the present invention. This does not affect the substantive content of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. A chip testing system, characterized in that, The system includes a host computer, a programmable power supply, a test board, a ZYNQ main control chip mounted on the test board, a chip under test, a power chip module, and a communication serial port module. The ZYNQ main control chip and the chip under test are interconnected via a first bus and a second bus. The ZYNQ main control chip communicates with the host computer via the communication serial port module. The power chip module is connected to the host computer via the programmable power supply, and the power chip module is connected to both the ZYNQ main control chip and the chip under test for system power supply. The host computer is used to send DFT commands or implementation commands to the ZYNQ main control chip through the communication serial port module, control the system to enter scan chain DFT mode or implementation mode, and test the chip under test. In DFT mode, the ZYNQ main control chip initiates a parallel scan of several circuits in the chip under test through the parallel function of its PL / FPGA. In implementation mode, the ZYNQ main control chip performs implementation function testing on the chip under test by running an implementation function test program in its PS / ARM and the chip under test. The first bus is used for data interaction in DFT mode, and the second bus is used for data interaction in implementation mode.

2. The chip testing system according to claim 1, characterized in that, The test board also has onboard DDR memory, a first flash memory, a second flash memory, and two reset circuit modules; The DDR memory and the first flash memory are respectively connected to the ZYNQ main control chip, the second flash memory and the chip under test, and the chip under test and the ZYNQ main control chip are respectively connected to a reset circuit module for chip initialization; The first flash memory stores programs for DFT mode and physical mode, while the second flash memory stores programs that the chip under test needs to run in physical mode.

3. The chip testing system according to claim 2, characterized in that, The ZYNQ main control chip is also connected to a first JTAG interface, and the chip under test is also connected to a second JTAG interface, which are used to burn test programs to the corresponding flash memory of their respective chips.

4. The chip testing system according to claim 1, characterized in that, The power chip module is also connected to a current limiting and overvoltage protection module, and the programmable power supply is connected to the power chip module via a GPIB interface.

5. The chip testing system according to claim 2, characterized in that, When the system enters DFT mode, the ZYNQ main control chip reads the DFT scan chain program in the first flash memory, moves it to the DDR memory connected to it for execution, and performs DFT scan on the chip under test through the first bus. The ZYNQ main control chip applies test excitation signals from each functional module to the output pins of the chip under test, and receives feedback signals output by the chip under test; The ZYNQ main control chip collects and compares the test excitation signal and feedback signal, counts the number of errors and the error rate, and reports the statistical results to the host computer for data processing and display of test data.

6. The chip testing system according to claim 2, characterized in that, When the system enters the actual installation mode, the ZYNQ main control chip reads the actual installation test program from the first flash memory, moves it to the DDR memory connected to it for execution, and controls the chip under test to run the actual installation test program through the second bus. The ZYNQ main control chip interacts with the chip under test to test whether the chip under test is functioning properly in various functions. The ZYNQ main control chip reports the test results of various functions to the host computer for display and data processing.

7. The chip testing system according to claim 5 or 6, characterized in that, After the host computer sends a DFT instruction or an implementation instruction to the ZYNQ main control chip, it detects and displays the system voltage and current through the current limiting and overvoltage protection module; when the system voltage or current exceeds the normal value, it shuts down the programmable power supply and ends the test.

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