MOSFET-TFET hybrid 11T-SRAM cell circuits and modules with high write noise tolerance

Abstract

This invention relates to the field of integrated circuit design technology, and more specifically, to a MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise margin, and a module employing this 11T-SRAM cell circuit layout. The 11T-SRAM cell circuit of this invention fully utilizes the advantages of TFET transistors at low voltages—better switching characteristics and lower subthreshold swing—and employs a break-lock latch structure to improve the cell's write noise margin. By using an NTFET transistor whose drain voltage is always no lower than the source voltage as the transfer control transistor, not only is the SRAM cell's write capability improved, but the forward bias current of the TFET device is also eliminated, reducing the cell's static power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically, to a MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance, and a module employing this 11T-SRAM cell circuit layout. Background Technology

[0002] With the advent of the era of artificial intelligence, big data, and the Internet of Things, and the popularization of wearable devices, the integration of chips is constantly increasing. The power consumption problem of traditional MOSFET devices has gradually become one of the important factors restricting module development. To solve the battery life problem, the demand for low-power chips with low operating voltages is becoming increasingly strong. However, due to the Boltzmann distribution, the subthreshold swing of traditional MOSFET devices has a physical limit in low-voltage applications. This greatly affects the switching characteristics of MOSFET devices, and their leakage current increases exponentially with decreasing voltage, significantly hindering their application in ultra-low-power chips. In the microprocessors (MCUs) of wearable devices, static random access memory (SRAM) occupies more than 50% of the chip area. SRAM consumes most of the static power consumption of the MCU. Therefore, solving the static power consumption problem of SRAM is helpful in promoting the realization of low-power devices. Currently, most research on reducing SRAM static power consumption under subthreshold voltage focuses on optimizing the peripheral logic circuits of SRAM or introducing read / write auxiliary circuits. However, due to the inherent shortcomings of MOSFET devices, the effect of further reducing static power consumption remains very limited.

[0003] Compared to MOSFET devices, tunneling field-effect transistors (TFETs), as non-Boltzmann distributed devices, have a higher on / off ratio and lower subthreshold swing. This makes TFETs promising for applications in low-voltage, low-power fields and a significant potential replacement for MOSFETs. However, due to the non-uniform doping of the source and drain of TFETs, they exhibit unidirectional conductivity. This can lead to a forward bias current uncontrolled by the gate voltage during operation, which will significantly increase the static power consumption of existing SRAMs (6T TFET SRAM, 8T TFET SRAM) and disrupt the voltage stability of the memory node. Furthermore, because TFETs have a smaller on-state current compared to MOSFETs, their write capability and write stability are weaker, resulting in lower write noise margin. Summary of the Invention

[0004] Therefore, it is necessary to provide a MOSFET-TFET hybrid 11T-SRAM cell circuit and module with high write noise margin to address the problems of low write noise margin and high static power consumption of existing TFET SRAM cells. Based on the TFET device, the use of the breakout transistor and read / write separation structure not only improves the write noise margin and write margin of the SRAM cell, but also eliminates the forward bias current that occurs when the TFET is used as the SRAM transmission transistor, thereby reducing the static power consumption of the cell.

[0005] This invention is achieved using the following technical solution:

[0006] In a first aspect, the present invention provides a MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance, comprising four PTFET transistors P1 to P4, five NTFET transistors N1 to N5, and two NMOS transistors NM1 to NM2.

[0007] The source of P1 is electrically connected to the power supply VDD. The source of P2 is electrically connected to the power supply VDD. The source of P3 is electrically connected to the drain of P1, the drain of P3 is electrically connected to the gate of P2, and the gate of P3 is electrically connected to the write control signal LEN. The source of P4 is electrically connected to the drain of P2, the drain of P4 is electrically connected to the gate of P1, and the gate of P4 is electrically connected to the write control signal REN.

[0008] The source of N1 is electrically connected to ground (GND), and the gate of N1 is electrically connected to the drain of P4. The source of N2 is electrically connected to the drain of N1, the drain of N2 is electrically connected to the read bit line (RBL), and the gate of N2 is electrically connected to the read word line (RWL). The source of N3 is electrically connected to ground (GND), the drain of N3 is electrically connected to the drain of P3 and has a memory node Q, and the gate of N3 is electrically connected to the gate of P1. The source of N4 is electrically connected to ground (GND), the drain of N4 is electrically connected to the drain of P4 and has a memory node QB, and the gate of N4 is electrically connected to the gate of P2. The source of N5 is electrically connected to ground (GND), and the gate of N5 is electrically connected to the write word line (WL).

[0009] The source of NM1 is electrically connected to the drain of N5, the drain of NM1 is electrically connected to the drain of P3, and the gate of NM1 is electrically connected to the write bit line BL. The source of NM2 is electrically connected to the drain of N5, the drain of NM2 is electrically connected to the drain of P4, and the gate of NM2 is electrically connected to the write bit line BLB.

[0010] The implementation of this 11T-SRAM cell circuit is based on the method or process of an embodiment of this disclosure.

[0011] In a second aspect, the present invention discloses an 11T-SRAM module, which adopts the MOSFET-TFET hybrid 11T-SRAM cell circuit layout with high write noise tolerance as disclosed in the first aspect.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] The 11T-SRAM cell circuit of this invention fully utilizes the advantages of TFET transistors having better switching characteristics and lower subthreshold swing at low voltages. It adopts a break latch structure to improve the write noise margin of the cell. It uses an NTFET transistor whose drain voltage is always not lower than the source voltage as the transmission control transistor, which not only improves the write capability of the SRAM cell, but also eliminates the forward bias current of the TFET device and reduces the static power consumption of the cell. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of the MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance disclosed in Embodiment 1 of the present invention;

[0016] Figure 2 for Figure 1 Timing diagram of the 11T-SRAM cell circuit;

[0017] Figure 3 As disclosed in Embodiment 2 of the present invention Figure 1 A comparison chart of write noise margin of the 11T-SRAM cell circuit with write noise margin of other cells;

[0018] Figure 4 As disclosed in Embodiment 2 of the present invention Figure 1 A comparison chart of write margin data for the 11T-SRAM cell circuit with other cells;

[0019] Figure 5 As disclosed in Embodiment 2 of the present invention Figure 1 A comparison chart of the static power consumption of the 11T-SRAM cell circuit with that of other cells.

[0020] Figure 6 This is a pin diagram of the module disclosed in Embodiment 3 of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] Example 1

[0025] See Figure 1 This is a structural diagram of a MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance disclosed in this invention. The 11T-SRAM cell circuit includes four PTFET transistors P1 to P4, five NTFET transistors N1 to N5, and two NMOS transistors NM1 to NM2.

[0026] The source of P1 is electrically connected to the power supply VDD. The source of P2 is electrically connected to the power supply VDD. The source of P3 is electrically connected to the drain of P1, the drain of P3 is electrically connected to the gate of P2, and the gate of P3 is electrically connected to the write control signal LEN. The source of P4 is electrically connected to the drain of P2, the drain of P4 is electrically connected to the gate of P1, and the gate of P4 is electrically connected to the write control signal REN.

[0027] The source of N1 is electrically connected to ground (GND), and the gate of N1 is electrically connected to the drain of P4. The source of N2 is electrically connected to the drain of N1, the drain of N2 is electrically connected to the read bit line (RBL), and the gate of N2 is electrically connected to the read word line (RWL). The source of N3 is electrically connected to ground (GND), the drain of N3 is electrically connected to the drain of P3 and has a memory node Q, and the gate of N3 is electrically connected to the gate of P1. The source of N4 is electrically connected to ground (GND), the drain of N4 is electrically connected to the drain of P4 and has a memory node QB, and the gate of N4 is electrically connected to the gate of P2. The source of N5 is electrically connected to ground (GND), and the gate of N5 is electrically connected to the write word line (WL).

[0028] The source of NM1 is electrically connected to the drain of N5, the drain of NM1 is electrically connected to the drain of P3, and the gate of NM1 is electrically connected to the write bit line BL. The source of NM2 is electrically connected to the drain of N5, the drain of NM2 is electrically connected to the drain of P4, and the gate of NM2 is electrically connected to the write bit line BLB.

[0029] Based on the connection relationship of the above devices, the read operation part of the SRAM cell circuit is composed of N1 and N2, which improves the read capability of the SRAM cell compared with the existing 6T TFET SRAM.

[0030] P1 and N3 form one inverter, and P2 and N4 form another inverter. The two inverters form a latch structure. P1 and P2 are pull-up transistors, and N3 and N4 are pull-down transistors. P3 and P4 are located between the pull-up and pull-down transistors. P3 and P4 interrupt the latch structure of the two inverters, which can improve the write capability (write margin and write noise tolerance) of the SRAM cell.

[0031] N5, NM1, and NM2 constitute the cell transmission transistor, which can eliminate the forward bias leakage current problem caused by the forward bias voltage of the TFET. In short, N5, NM1, and NM2 form an effective discharge path during write operations, thereby improving cell write stability.

[0032] See Figure 2 Here is the timing diagram of the 11T-SRAM cell circuit in this embodiment:

[0033] (1) In the holding state, the write word line WL and read word line RWL are low, the write bit line BL and BLB are low, N2, N5, NM1 and NM2 are closed, the write control signals LEN and REN are low, and P3 and P4 are turned on, so that the latch structure is in the latch state, thus ensuring the stability of the SRAM cell in the holding state.

[0034] In addition, the drain voltage of N5 is always no lower than the source voltage of N5, thereby avoiding the TFET from having a forward bias current that is not controlled by the gate and reducing the static power consumption of the cell.

[0035] (2) During the read operation phase, the read bit line RBL is connected to a sensitive amplifier, the write word line WL is at a low level, the write bit lines BL and BLB are at a low level, the write control signals LEN and REN are at a low level, P3 and P4 are turned on, the read word line RWL is set to a high level, and the read bit line RBL is precharged to a high level.

[0036] If the stored data is "0", that is, "Q=0, QB=1", then the read bit line RBL discharges through N1 and N2, the sensitive amplifier detects the change in the level of the read bit line RBL, and reads the output "0".

[0037] If the stored data is "1", that is, "Q=1, QB=0", then the read bit line RBL remains at a high level. The sensitive amplifier detects that the level of the read bit line RBL has not changed and reads "1" as the output.

[0038] For a sensitive amplifier, its input terminal one is connected to the read line RBL, input terminal two is connected to the reference voltage, and the output terminal is used to output the read value.

[0039] (3) During the write operation phase, the read word line RWL is set to low level and the write word line WL is set to high level. The state of the control signal varies depending on the type of data being written.

[0040] When performing a write "0" operation, the write bit line BL is set to high level, the write bit line BLB is set to low level, the write control signal LEN is set to high level, the write control signal REN is set to low level, P3 is turned off, P4 is turned on, NM1 is turned on, and NM2 is turned off. The storage node Q discharges to ground through N5 and NM1, and the level of the storage node QB is flipped through the latch structure. The power supply VDD charges the storage node QB through P2 and P4, causing the voltage of the storage node QB to rise rapidly to a high level, thus completing the write "0" operation.

[0041] To perform a write "1" operation, write bit line BLB is set to high level, write bit line BL is set to low level, write control signal REN is set to high level, write control signal LEN is set to low level, P3 is turned on, P4 is turned off, NM2 is turned on, and NM1 is turned off. Storage node QB discharges to ground through N5 and NM2, and the level of storage node Q is flipped through the latch structure. Power supply VDD charges storage node Q through transistors P1 and P3, causing the voltage of storage node Q to rise rapidly to a high level, thus completing the write "1" operation.

[0042] In addition, after the write operation is completed, the write word line WL is set to low level, the write bit lines BL and BLB are set to low level, the write control signals LEN and REN are set to low level, P3 and P4 are turned on, and the latch structure returns to the latch state.

[0043] Since N5 always maintains a drain voltage no lower than the source voltage, it effectively avoids the forward bias current of the TFET transistor; at the same time, it adopts a write interruption method, using P3 and P4 to interrupt the latch structure composed of two inverters, which improves the write margin and write noise tolerance of the cell.

[0044] Example 2

[0045] This embodiment 2 compares the 11T-SRAM cell circuit disclosed in embodiment 1 with other TFET SRAM cells through simulation to verify the technical effect of the 11T-SRAM cell circuit.

[0046] (I) See Figure 3 This chart compares the write noise margin of the 11T-SRAM cell circuit with that of other cells. Specifically, it shows the comparison of the write noise margin (WSNM) data of the 11T-SRAM cell circuit (denoted as 11T), the traditional 6T TFET SRAM (denoted as 6T), and the read-write separated 8T TFET SRAM cell (denoted as 8T) under a supply voltage of 0.5V to 0.9V.

[0047] The write noise margin is obtained from the voltage transfer characteristic curve (denoted as VTC), by... Figure 3 It can be seen that 11T has a larger write noise margin than 6T and 8T.

[0048] This is because the latching structure of the two inverters is broken during the write operation phase, which improves the write capability of the cell and gives the 11T a higher write noise margin.

[0049] (II) See Figure 4 This is a comparison chart of the write margin of this 11T-SRAM cell circuit with the write margin of other cells. Specifically, it shows the comparison of the write margin (WM) data of this 11T-SRAM cell circuit (denoted as 11T), the traditional 6T TFETSRAM (denoted as 6T), and the read-write separated 8T TFETSRAM cell (denoted as 8T) under the supply voltage of 0.5V to 0.9V.

[0050] Write margin indicates the magnitude of the word line voltage when data writing is complete, determined by... Figure 4 It can be seen that 11T has a larger write margin than 6T and 8T.

[0051] This is because the 11T uses an NTFET pull-down structure during the write operation phase, which gives the 11T a larger write margin than the 6T and 8T.

[0052] (III) See Figure 5This is a comparison chart of the static power consumption of the 11T-SRAM cell circuit with other cells. Specifically, it shows the comparison of the static power consumption (denoted as StaticPower) of the 11T-SRAM cell circuit (denoted as 11T), the traditional 6T TFET SRAM (denoted as 6T), and the read / write separated 8T TFET SRAM cell (denoted as 8T) under a supply voltage of 0.5V to 0.9V.

[0053] Static power consumption refers to the total power consumption of the cell in the hold state. Figure 5 It can be seen that the 11T has lower static power consumption than the 6T and 8T: for example, when the voltage is 0.9V, compared with the static power consumption of 3.157nW of the 6T and 2.261nW of the 8T, the static power consumption of the 11T is 1.875nW, which is reduced by 41.18% and 17.87% respectively.

[0054] This is because when 6T and 8T use unidirectional external NTFET transistors as transmission transistors, there is a forward bias current, which results in a large static power consumption of their SRAM cells. However, the drain voltage of the transmission transistor N5 used in 11T is always no lower than the source voltage, thus eliminating the forward bias current and solving the problem of forward bias current in 6T and 8T when using unidirectional external NTFET transistors as transmission transistors in the hold state.

[0055] Example 3

[0056] This embodiment 3 discloses an 11T-SRAM module, which adopts the MOSFET-TFET hybrid 11T-SRAM cell circuit layout with high write noise tolerance disclosed in embodiment 1. The module packaging makes it easier to promote and apply the aforementioned 11T-SRAM cell circuit.

[0057] See Figure 6 The pins of this 11T-SRAM module include: pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8.

[0058] Pin 1 is electrically connected to the write word line WL. Pin 2 is electrically connected to the write bit line BL. Pin 3 is electrically connected to the write bit line BLB. Pin 4 is electrically connected to the read bit line RBL. Pin 5 is used to transmit the write control signal REN. Pin 6 is used to transmit the write control signal LEN. Pin 7 is connected to the power supply VDD. Pin 8 is electrically connected to ground GND.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance, characterized in that, include: PTFET transistor P1, the source of P1 is connected to power supply VDD; PTFET transistor P2, the source of P2 is connected to the power supply VDD; PTFET transistor P3, the source of P3 is electrically connected to the drain of P1, the drain of P3 is electrically connected to the gate of P2, and the gate of P3 is electrically connected to the write control signal LEN. PTFET transistor P4, the source of P4 is electrically connected to the drain of P2, the drain of P4 is electrically connected to the gate of P1, and the gate of P4 is electrically connected to the write control signal REN. NTFET transistor N1, the source of N1 is electrically connected to ground GND, and the gate of N1 is electrically connected to the drain of P4; The source of NTFET transistor N2 is electrically connected to the drain of N1, the drain of N2 is electrically connected to the read bit line RBL, and the gate of N2 is electrically connected to the read word line RWL. NTFET transistor N3, the source of N3 is electrically connected to ground GND, the drain of N3 is electrically connected to the drain of P3 and a storage node Q is provided, and the gate of N3 is electrically connected to the gate of P1. The NTFET transistor N4 has its source electrically connected to ground GND, its drain electrically connected to the drain of P4 and has a storage node QB, and its gate electrically connected to the gate of P2. NTFET transistor N5, the source of N5 is electrically connected to ground GND, and the gate of N5 is electrically connected to the write line WL. NMOS transistor NM1, the source of NM1 is electrically connected to the drain of N5, the drain of NM1 is electrically connected to the drain of P3, and the gate of NM1 is electrically connected to the write line BL; and NMOS transistor NM2, the source of NM2 is electrically connected to the drain of N5, the drain of NM2 is electrically connected to the drain of P4, and the gate of NM2 is electrically connected to the write bit line BLB. In the hold state, the write word line WL and read word line RWL are at low level, the write bit lines BL and BLB are at low level, N2, N5, NM1, and NM2 are off, the write control signals LEN and REN are at low level, and P3 and P4 are on, so that the latch structure is in the latch state.

2. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 1, characterized in that, N1 and N2 constitute the read operation section; P1 and N3 constitute one inverter, and P2 and N4 constitute another inverter. The two inverters form a latch structure; P1 and P2 are pull-up transistors, N3 and N4 are pull-down transistors, and P3 and P4 are located between the pull-up transistors and the pull-down transistors; N5, NM1, and NM2 constitute the unit transmission transistors.

3. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 1, characterized in that, In the holding state, the drain voltage of N5 is never lower than the source voltage of N5.

4. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 2, characterized in that, During the read operation phase, the read bit line RBL is connected to a sensitive amplifier, the write word line WL is at a low level, the write bit lines BL and BLB are at a low level, the write control signals LEN and REN are at a low level, P3 and P4 are turned on, the read word line RWL is set to a high level, and the read bit line RBL is precharged to a high level. If the stored data is "0", that is, "Q=0, QB=1", then the read bit line RBL discharges through N1 and N2, the sensitive amplifier detects the change in the level of the read bit line RBL, and reads the output "0"; If the stored data is "1", that is, "Q=1, QB=0", then the read bit line RBL remains at a high level. The sensitive amplifier detects that the level of the read bit line RBL has not changed and reads the output "1".

5. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 2, characterized in that, During the write operation phase, the read word line RWL is set to low level, and the write word line WL is set to high level. The state of the control signal varies depending on the data being written.

6. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 5, characterized in that, When performing a write "0" operation, the write bit line BL is set to high level, the write bit line BLB is set to low level, the write control signal LEN is set to high level, the write control signal REN is set to low level, P3 is turned off, P4 is turned on, NM1 is turned on, and NM2 is turned off. The storage node Q discharges to ground through N5 and NM1, and the level of the storage node QB is flipped through the latch structure. The power supply VDD charges the storage node QB through P2 and P4, causing the voltage of the storage node QB to rise rapidly to a high level, thus completing the write "0" operation.

7. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 5, characterized in that, To perform a write "1" operation, write bit line BLB is set to high level, write bit line BL is set to low level, write control signal REN is set to high level, write control signal LEN is set to low level, P3 is turned on, P4 is turned off, NM2 is turned on, and NM1 is turned off. Storage node QB discharges to ground through N5 and NM2, and the level of storage node Q is flipped through the latch structure. Power supply VDD charges storage node Q through transistors P1 and P3, causing the voltage of storage node Q to rise rapidly to a high level, thus completing the write "1" operation.

8. The MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise tolerance according to claim 5, characterized in that, After the write operation is completed, the write word line WL is set to low level, the write bit lines BL and BLB are set to low level, the write control signals LEN and REN are set to low level, P3 and P4 are turned on, and the latch structure returns to the latch state.

9. An 11T-SRAM module, characterized in that, The circuit layout of the MOSFET-TFET hybrid 11T-SRAM cell with high write noise tolerance is adopted as described in any one of claims 1-8.

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