High electron mobility transistor

Abstract

A high electron mobility transistor includes a substrate, a compound semiconductor stack, a cap layer, a gate electrode, a source electrode, a drain electrode, and a buried electrode and / or a conductive structure. The substrate has an active region. The compound semiconductor stack includes a buffer layer, a high-resistance layer, a channel layer, and a barrier layer, which are sequentially disposed on the substrate. The cap layer is disposed on the compound semiconductor stack. The gate electrode is disposed on the cap layer and extends in a first direction. The source electrode and the drain electrode are disposed on the compound semiconductor stack and are arranged in a second direction on both sides of the gate electrode, wherein the first direction is perpendicular to the second direction. The buried electrode and / or the conductive structure pass through the compound semiconductor stack, surround or are disposed in the active region, and have a fixed potential or are grounded.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a high electron mobility transistor. Background Technology

[0002] In semiconductor technology, III-V group semiconductor compounds can be used to form various integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are a type of transistor with a two-dimensional electron gas (2-DEG), where the 2-DEG is adjacent to the junction between two materials with different band gaps (i.e., a heterojunction). Because HEMTs do not use doped regions as the carrier channels of the transistor, but rather use the 2-DEG as the carrier channels, they possess several attractive characteristics compared to existing metal-oxide-semiconductor field-effect transistors (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies.

[0003] Although high electron mobility transistors (HEMTs) have many advantages, existing HEMTs still have many problems to overcome in high current and high voltage applications. Summary of the Invention

[0004] In view of this, it is necessary to propose an improved high electron mobility transistor to overcome the shortcomings of existing high electron mobility transistors.

[0005] According to an embodiment of the present invention, a high electron mobility transistor is provided, comprising: a substrate having an active region; a compound semiconductor stack including a buffer layer, a high-resistivity layer, a channel layer and a barrier layer sequentially disposed on the substrate; a capping layer disposed on the compound semiconductor stack; a gate electrode disposed on the capping layer and extending along a first direction; a source electrode and a drain electrode disposed on the compound semiconductor stack, respectively located on both sides of the gate electrode and arranged along a second direction, wherein the first direction is perpendicular to the second direction; and a buried electrode passing through the compound semiconductor stack, disposed in the active region, and having a fixed potential or ground, wherein the source electrode includes a first portion and a second portion arranged along the first direction, the buried electrode is located between the first portion and the second portion, and the buried electrode is spaced apart from the first portion and the second portion.

[0006] According to another embodiment of the present invention, a high electron mobility transistor is provided, comprising: a substrate having an active region including a plurality of repeating units; a compound semiconductor stack including a buffer layer, a high-resistivity layer, a channel layer and a barrier layer sequentially disposed on the substrate; and a conductive structure passing through the compound semiconductor stack, surrounding the active region, and having a fixed potential or ground; wherein at least one of the repeating units includes: a capping layer disposed on the compound semiconductor stack; a gate electrode disposed on the capping layer and extending along a first direction; and a source electrode and a drain electrode disposed on the compound semiconductor stack, respectively located on both sides of the gate electrode and arranged along a second direction, wherein the first direction is perpendicular to the second direction.

[0007] The beneficial effects of the technical solution of the present invention include: 1) reducing the dynamic on-resistance (dynamic Ron) of high electron mobility transistors in high voltage and high current applications; 2) further improving the grounding effect or potential stabilization effect of the semiconductor layer in the active region of the high electron mobility transistor, especially when the device size increases, so that the high electron mobility transistor of the present invention can significantly reduce the dynamic on-resistance in high current and high voltage applications compared with HEMTs without a conductive structure around the active region, thereby improving the electrical performance of the high electron mobility transistor. Attached Figure Description

[0008] Figure 1 This is a top view of a high electron mobility transistor (HEMT) according to an embodiment of the present invention;

[0009] Figure 2A This is a top view of a repeating unit of a HEMT according to an embodiment of the present invention;

[0010] Figure 2B This is a top view of a repeating unit of a HEMT according to another embodiment of the present invention;

[0011] Figure 3 This is a schematic cross-sectional view of a HEMT according to an embodiment of the present invention, which is along... Figure 1 Draw the A-A' line;

[0012] Figure 4 This is a schematic cross-sectional view of the substrate of a HEMT according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic cross-sectional view of the substrate of a HEMT according to another embodiment of the present invention;

[0014] Figure 6This is a schematic cross-sectional view of a HEMT according to an embodiment of the present invention, which is along... Figure 1 Draw the B-B' line;

[0015] Figure 7 This is a schematic cross-sectional view of a HEMT according to another embodiment of the present invention, which is along... Figure 1 Draw the B-B' line.

[0016] Explanation of reference numerals in the attached figures: 100… High electron mobility transistor 100A…Active Zone 100B…Outer Zone 100U…repeating unit 101…Core Substrate 102…Substrate 103…First Insulation Layer 104…Insulation layer 105… Semiconductor material layer 106, 111… Semiconductor layers 107…Second Insulation Layer 109… Composite Material Layer 110…base 112… Buffer layer 114…High-resistivity layer 116…Channel Layer 118…Barrier Layer 120…compound semiconductor stack 121…cap layer 122-1, 122-2… Gate electrodes 122P… Gate electrode contact pad 132…Source Electrode 132a, 132b... source portion 132P…Contact pads of the source electrode 132V, 142V... vias 135…Source Metal Pattern 136…Drain electrode 136P…Drain electrode contact pad 138…Dielectric layer 140…conductive structure 142… Buried Electrode 144…Metallic Conductor Layer 150… Two-dimensional electron gas region 160… interconnect structure d1, d2... distance Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0018] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature is formed on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any relationship between different embodiments and / or configurations.

[0019] Furthermore, for the purposes of this invention, spatially related terms such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms are used to describe the relative relationship between one element or feature and another (or more) elements or features in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0020] Although the present invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0021] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0022] In this invention, "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Furthermore, "Group III-V semiconductors" can be binary, ternary, or quaternary compound semiconductors, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), and their analogues or combinations of the above compounds, but are not limited thereto. In addition, depending on the requirements, Group III-V semiconductors may also include dopants to form Group III-V semiconductors with specific conductivity types, such as n-type or p-type Group III-V semiconductors. In the following text, Group III-V semiconductors may also be referred to as III-V semiconductors.

[0023] Although the technical solutions of the present invention are described below through specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the present invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0024] This invention proposes a high electron mobility transistor (HEMT), which is a power switching transistor that can be used as a voltage converter. Compared to silicon power transistors, III-V semiconductor HEMTs (III-V HEMTs) have a wider band gap, thus exhibiting low on-state resistance and low switching losses.

[0025] Figure 1This is a plan view (top view) of a high electron mobility transistor according to an embodiment of the present invention. Figure 1 As shown, according to an embodiment of the present invention, a high electron mobility transistor (HEMT) 100, such as an enhancement-mode HEMT, can be divided into an active area 100A and a peripheral area 100B surrounding the active area 100A, wherein a conductive structure 140 is not located in the active area 100A and is separated from the source electrode 132, gate electrodes 122-1, 122-2 and drain electrode 136 within the active area 100A, and the conductive structure 140 is electrically connected to the source electrode 132 via an interconnect structure. Although Figure 1 The conductive structure 140 shown is a continuous ring shape. In other embodiments, the conductive structure 140 may also be a discontinuous ring shape surrounding the active region. Additionally, the conductive structure 140 may be disposed together with a seal ring structure (not shown in the figures) within the peripheral region 100B surrounding the active region 100A.

[0026] According to an embodiment of the present invention, the active region 100A includes a plurality of repeat units 100U, each of which may include a source electrode 132, a gate electrode 122-1, a drain electrode 136, and a gate electrode 122-2 arranged sequentially along a certain direction (e.g., the y-direction). The source electrode 132 includes multiple source portions, such as source portions 132a and 132b, which are arranged along another direction (e.g., the x-direction) and spaced apart from each other. Therefore, for the multiple source portions 132a and 132b extending along the x-direction, these source portions 132a and 132b can constitute one branch electrode of a source finger electrode, and the source electrode 132 is located on one side of the gate electrode 122-1. Each drain electrode 136 can form one branch electrode of a drain finger electrode and is located on the other side of the gate electrode 122-1. Furthermore, in one embodiment, the drain electrode 136 is also disposed between the two gate electrodes 122-1 and 122-2; this embodiment can be referred to as a common drain layout. Meanwhile, in Figure 1 In the layout, the source electrode 132 is placed outside the two gate electrodes 122-1 and 122-2, and the source electrode 132 is also placed on the upper and lower sides of the active region 100A. Additionally, as... Figure 1As shown, in one embodiment, source finger electrodes formed by each source electrode 132 are connected to a source electrode contact pad 132P, and gate finger electrodes formed by each gate electrode 122-1, 122-2 are connected to a gate electrode contact pad 122P. The source electrode contact pad 132P and the gate electrode contact pad 122P can be placed on the same side (e.g., the left side) of the active region 100A, and the source electrode contact pad 132P can be placed outside the gate electrode contact pad 122P. The drain finger electrodes formed by each drain electrode 136 are connected to a drain electrode contact pad 136P, and the drain electrode contact pad 136P is placed on the other side (e.g., the right side) of the active region 100A. The number and arrangement of the source electrode contact pad 132P, the gate electrode contact pad 122P, and the drain electrode contact pad 136P described above are merely illustrative examples, and the embodiments of the present invention are not limited thereto.

[0027] According to an embodiment of the present invention, at least one repeating unit 100U of the active region 100A includes a buried through electrode 142, and the buried through electrode 142 is disposed between adjacent source portions 132a and 132b of the source electrode 132, and the buried through electrode 142 is also spaced apart from these source portions 132a and 132b of the source electrode 132. One repeating unit 100U may include one or more buried through electrodes 142. Furthermore, in one embodiment, each repeating unit 100U of the active region 100A may contain one or more buried through electrodes 142. In another embodiment, some repeating units 100U of the active region 100A may contain one or more buried through electrodes 142, while other repeating units 100U may not contain buried through electrodes 142. For example, buried through electrodes 142 may be disposed at intervals of one or more repeating units 100U. Therefore, for two adjacent repeating units 100U, only one may contain a buried through electrode 142, but this is not a limitation. The number and arrangement of the buried electrodes 142 within the active region 100A can be determined based on the electrical requirements of the HEMT.

[0028] Figure 2A This is a plan view (top view) of a repeating unit of a HEMT according to another embodiment of the present invention. Figure 2A and Figure 1 The difference lies in Figure 2A The repeating cell 100U is arranged with a common source, wherein the source electrode 132 is disposed between the two gate electrodes 122-1 and 122-2. Meanwhile, in Figure 2AIn the layout of the repeating unit 100U, the drain electrode 136 is placed outside the two gate electrodes 122-1 and 122-2, and the drain electrode 136 is also placed on the upper and lower sides of the active region 100A.

[0029] Figure 2B This is a plan view (top view) of a repeating unit of a HEMT according to another embodiment of the present invention. Figure 2B and Figure 1 The difference lies in Figure 2B In the repeating unit 100U, the source electrode 132 is not disconnected, that is, the source electrode 132 has a continuous electrode pattern along the x-direction. Viewed from above, one or more buried electrodes 142 are disposed in the projection area of ​​the source electrode 132. For example, multiple buried electrodes 142 may be arranged spaced apart from each other in the projection area of ​​the source electrode 132 along the x-direction. In one embodiment, the top surface of the buried electrode 142 may be on the same plane as the top surface of the source electrode 132. In other embodiments, the top surface of the buried electrode 142 may be lower than the top surface of the source electrode 132, and the top surface of the buried electrode 142 may at least contact the bottom surface of the source electrode 132, so that the buried electrode 142 is electrically connected to the source electrode 132.

[0030] Figure 3 This is a schematic cross-sectional view of a HEMT according to an embodiment of the present invention, which is along... Figure 1 Draw the A-A' line. For example... Figure 3As shown, according to one embodiment of the present invention, a high electron mobility transistor 100 includes a substrate 110, and a semiconductor layer 111 is disposed on the substrate 110. The semiconductor layer 111 can serve as a seed layer, such as a silicon-containing seed layer. Therefore, by providing the semiconductor layer 111, a compound semiconductor stack 120 can be grown on the seed layer. Furthermore, the semiconductor layer 111 has suitable conductivity and is therefore not electrically insulating. According to some embodiments of the present invention, the material of the semiconductor layer 111 includes one or more combinations of silicon, gallium nitride, ceramic, silicon carbide, aluminum nitride, and aluminum oxide. The compound semiconductor stack 120 is disposed on the semiconductor layer 111, wherein the compound semiconductor stack 120 includes a buffer layer 112, a high resistance layer 114, a channel layer 116, and a barrier layer 118 sequentially disposed from bottom to top on the semiconductor layer 111 and the substrate 110. Each layer of the compound semiconductor stack 120 can be formed by epitaxial growth of III-V semiconductors. According to an embodiment of the present invention, the buffer layer 112 may include a super lattice structure, such as including a plurality of paired III-V binary semiconductors / III-V ternary semiconductors, such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination thereof. The composition of the high-resistivity layer 114 is, for example, carbon-doped gallium nitride (C:GaN), and the resistivity of the high-resistivity layer 114 is higher than that of the buffer layer 112.

[0031] Channel layer 116 may comprise one or more III-V semiconductor layers, the composition of which may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. Furthermore, channel layer 116 may be an undoped or doped one or more III-V semiconductor layers. A doped channel layer 116 may be, for example, a p-type III-V semiconductor layer. For a p-type III-V semiconductor layer, the dopant may be carbon, iron, magnesium, or zinc, but is not limited thereto. Barrier layer 118 may comprise one or more III-V semiconductor layers, and its composition may differ from that of the III-V semiconductor layer 116. For example, barrier layer 118 may comprise AlN, AlzGaN, or a combination of both. According to one embodiment, channel layer 116 may be an undoped GaN layer, while barrier layer 118 may be an essentially n-type AlGaN layer.

[0032] Furthermore, a patterned cap layer 121 is provided on the barrier layer 118 to deplete the two-dimensional electron gas (2-DEG) region, achieving the normally-off state of the HEMT. In one embodiment, the cap layer 121 is, for example, a p-type cap layer or an n-type cap layer. The cap layer 121 can be one or more doped III-V semiconductor layers, the composition of which can be GaN, AlGaN, InGaN, or InAlGaN, and the dopant can be C, Fe, Mg, or Zn, but is not limited thereto. According to one embodiment, the cap layer 121 can be a p-type GaN layer. A gate electrode 122-1 is disposed on the cap layer 121 and extends along a first direction (e.g., the x-direction). Source electrode 132 and drain electrode 136 are disposed on the compound semiconductor stack 120, respectively located on both sides of gate electrode 122-1, and arranged along a second direction (e.g., the y-direction). The first direction is perpendicular to the second direction, and the source electrode 132 and drain electrode 136 can penetrate the barrier layer 118 to reach the top surface of the channel layer 116, or reach a depth position of the channel layer 116. Furthermore, according to an embodiment of the present invention, as... Figure 3 As shown, the distance d2 between the drain electrode 136 and the gate electrode 122-1 can be greater than the distance d1 between the source electrode 132 and the gate electrode 122-1. This is because the drain electrode 136 is usually subjected to a high voltage, so the distance d2 between the drain electrode 136 and the gate electrode 122-1 will be greater than the distance d1 between the source electrode 132 and the gate electrode 122-1.

[0033] Because of the discontinuous bandgap between the channel layer 116 and the barrier layer 118, by stacking the channel layer 116 and the barrier layer 118 together, electrons are concentrated at the heterojunction between the channel layer 116 and the barrier layer 118 due to the piezoelectric effect, thus generating a thin layer with high electron mobility, namely a two-dimensional electron gas (2-DEG) region 150. For normally-off devices, when no voltage is applied to the gate electrode 122-1, the region covered by the capping layer 121 will not form a 2-DEG (such as...). Figure 3 As shown, this area can be considered a 2-DEG cutoff region, where there is no conduction between the source electrode 132 and the drain electrode 136. When a positive voltage is applied to the gate electrode 122-1, a 2-DEG is formed in the area covered by the capping layer 121, creating a continuous 2-DEG region 150 between the source electrode 132 and the drain electrode 136, thus enabling conduction between them.

[0034] According to one embodiment, the source electrode 132 and drain electrode 136 can be single-layer or multi-layer structures, and their composition may include ohmic contact metal. Ohmic contact metal refers to a metal, alloy, or stacked layer thereof that can form an ohmic contact with a semiconductor layer (e.g., channel layer 116), such as Ti, Ti / Al, Ti / Al / Ti / TiN, Ti / Al / Ti / Au, Ti / Al / Ni / Au, or Ti / Al / Mo / Au, but is not limited thereto. Gate electrodes 122-1 and 122-2 can be single-layer or multi-layer structures, such as a bilayer structure including a first conductive layer and a second conductive layer. The first conductive layer can directly contact the capping layer 121, and its composition includes Schottky contact metal. Schottky contact metal refers to a metal, alloy, or stacked layer thereof that can form a Schottky contact with a semiconductor layer (e.g., capping layer 121), such as TiN, W, Pt, or Ni, but is not limited thereto. The composition of the second conductive layer may include, but is not limited to, Ti, Al, Au, and Mo. According to one embodiment, the first conductive layer may further include a metal nitride of a refractory metal, and the refractory metal may be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, uranium, rhenium, ruthenium, osmium, rhodium, and iridium.

[0035] According to one embodiment of the present invention, the conductive structure 140 penetrates the compound semiconductor stack 120 and directly contacts the semiconductor layer 111. For example, the conductive structure 140 may contact the top surface of the semiconductor layer 111, reach a depth of the semiconductor layer 111, or penetrate the semiconductor layer 111. According to one embodiment of the present invention, the conductive structure 140 may be formed by etching trenches in the compound semiconductor stack 120 to expose the semiconductor layer 111 and filling the trenches with conductive material. Therefore, the conductive structure 140 can be electrically connected to the semiconductor layer 111, and according to some embodiments of the present invention, a fixed potential, such as 0V or 1V, can be provided to the conductive structure 140 as needed, so that the semiconductor layer 111 electrically connected to the conductive structure 140 also has a fixed potential. In a preferred embodiment, the conductive structure 140 and the semiconductor layer 111 are grounded, thereby avoiding the back-gating effect of the high electron mobility transistor 100. The conductive material of the conductive structure 140 can be a metal, alloy, or polycrystalline silicon. The metal or alloy material can be, for example, Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TiN, TaN, or any combination thereof. Furthermore, the conductive structure 140 may also include an insulating lining layer (not shown in the figures) deposited on the inner wall of the aforementioned trench to isolate the conductive material in the conductive structure 140 from the compound semiconductor stack 120 and to increase the adhesion of the conductive material. The insulating lining layer can be, for example, silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof. However, to electrically connect the conductive structure 140 to the semiconductor layer 111, an insulating lining layer may not be provided between the conductive material and the semiconductor layer 111.

[0036] Figure 4 This is a schematic cross-sectional view of the substrate of a HEMT according to an embodiment of the present invention. Figure 4As shown, according to an embodiment of the present invention, the substrate 110 of the high electron mobility transistor 100 may include a core substrate 101 and a composite material layer 109 enclosing the top, bottom, and side surfaces of the core substrate 101. The material of the core substrate 101 may be a material whose coefficient of thermal expansion matches that of the compound semiconductor stack 120 subsequently formed on the substrate 110, such as ceramic, silicon carbide, aluminum nitride, or sapphire, and the core substrate 101 may be made of a material with high hardness to provide sufficient mechanical strength to the substrate 110. According to an embodiment of the present invention, the composite material layer 109 may include a first insulating material layer 103, a semiconductor material layer 105, and a second insulating material layer 107, wherein the semiconductor material layer 105 is sandwiched between the first insulating material layer 103 and the second insulating material layer 107. The first insulating material layer 103 may be an oxide, such as silicon oxide; the second insulating material layer 107 may be a nitride, oxide, oxynitride or any combination thereof, for example, the second insulating material layer 107 may be composed of silicon nitride, silicon oxide and silicon nitride; the semiconductor material layer 105 may be a silicon layer or a polycrystalline silicon layer.

[0037] Figure 5 This is a schematic cross-sectional view of the substrate of a HEMT according to another embodiment of the present invention. Figure 5 As shown, according to one embodiment of the present invention, the substrate 110 of the high electron mobility transistor 100 may be a silicon-on-insulator (SOI) substrate, comprising a substrate 102, an insulating layer 104, and a semiconductor layer 106. The substrate 102 may be a handle wafer, and the insulating layer 104 may be an oxide layer, such as silicon oxide, and may be formed on the substrate 102 by thermal oxidation or deposition. The semiconductor layer 106 may be transferred onto the substrate 102 from a device wafer. For example, the device wafer may be bonded to the insulating layer 104 on the side closest to the semiconductor layer 106 via bonding, and the device wafer may be thinned to form the semiconductor layer 106. In one embodiment, the semiconductor layer 111 of the high electron mobility transistor 100 may also be provided by the semiconductor layer 106 of the SOI substrate.

[0038] Figure 6 This is a schematic cross-sectional view of a HEMT according to an embodiment of the present invention, which is along... Figure 1 Draw the B-B' line. For example... Figure 6As shown, according to one embodiment of the present invention, a high electron mobility transistor 100 includes a buried electrode 142 disposed between adjacent source portions of a source electrode 132. The buried electrode 142 directly contacts the semiconductor layer 111 through the compound semiconductor stack 120. For example, the buried electrode 142 may contact the top surface of the semiconductor layer 111, reach a depth of the semiconductor layer 111, or penetrate the semiconductor layer 111. According to one embodiment of the present invention, the buried electrode 142 may be formed by etching through-via holes in the compound semiconductor stack 120 to expose the semiconductor layer 111, and filling the through-via holes with conductive material. Therefore, the buried electrode 142 can be electrically connected to the semiconductor layer 111, and according to one embodiment of the present invention, a fixed potential, such as 0V or 1V, can be provided to the buried electrode 142 as needed, so that the semiconductor layer 111 electrically connected to the buried electrode 142 also has a fixed potential. In a preferred embodiment, the buried electrode 142 and the semiconductor layer 111 are grounded. Through the buried electrode 142 disposed in the active region 100A, all of the semiconductor layer 111 in the active region 100A of the high electron mobility transistor 100 can have a fixed potential or be stably grounded.

[0039] According to one embodiment of the present invention, the conductive material of the buried electrode 142 can be the same as that of the conductive structure 140, and the buried electrode 142 and the conductive structure 140 can be formed together by the same etching and deposition process. For example, a hard shield (not shown in the figures) can be formed on the compound semiconductor stack 120. The opening of the hard shield exposes the area where the conductive structure 140 and the buried electrode 142 are to be formed. Through the same etching process, the trenches of the conductive structure 140 and the through holes of the buried electrode 142 are etched in the compound semiconductor stack 120. Then, through the same deposition process, the conductive material is deposited in the aforementioned trenches and through holes, thereby forming the conductive structure 140 and the buried electrode 142.

[0040] Furthermore, according to one embodiment of the present invention, such as Figure 6 As shown, the buried electrode 142 is electrically connected to the source electrode 132 via an interconnect structure 160 to have a fixed potential or ground. The interconnect structure 160 includes vias 132V and 142V formed in the dielectric layer 138, and a metal conductor layer 144 formed on the dielectric layer 138. Via 132V is connected to the source electrode 132, via 142V is connected to the buried electrode 142, and the metal conductor layer 144 is connected to vias 132V and 142V. Additionally, although... Figure 6Not shown, the conductive structure 140 surrounding the active region 100A can also be electrically connected to the source electrode 132 via the interconnect structure 160 to have a fixed potential or be electrically grounded. For example, the conductive structure 140 can be electrically connected to any source electrode 132 or the contact pad 132P of the source electrode located in the active region 100A via other vias in the dielectric layer 138 and the metal wire layer 144 on the dielectric layer 138.

[0041] Figure 7 This is a schematic cross-sectional view of a HEMT according to another embodiment of the present invention, which is along... Figure 1 It is drawn using the B-B' line. Figure 7 and Figure 6 The difference lies in Figure 7 A source metal pattern 135 is further disposed on a plurality of source portions of the source electrode 132 of the HEMT high electron mobility transistor 100. A buried electrode 142 is located directly below the source metal pattern 135 and is electrically connected to the source electrode 132 by directly contacting the source metal pattern 135. In this embodiment, the buried electrode 142 is electrically connected to the source electrode 132 via the source metal pattern 135 and has a fixed potential or is electrically grounded. According to an embodiment of the present invention, a via can be additionally disposed between the source metal pattern 135 and the source electrode 132, so that the source metal pattern 135 can be electrically connected to those source portions of the source electrode 132 through the via.

[0042] According to an embodiment of the present invention, the conductive structure 140 surrounding the active region 100A is electrically connected to the semiconductor layer 111 on the substrate 110 and has a fixed potential or ground. This avoids the back-gating effect of the semiconductor layer 111 of the high electron mobility transistor 100, so that the dynamic on-state resistance (dynamic Ron) of the high electron mobility transistor 100 does not increase significantly in high voltage and high current applications compared to low voltage and low current applications, thereby improving the operational stability of the HEMT 100.

[0043] Furthermore, the buried electrode 142 within the active region 100A directly contacts and electrically connects to the semiconductor layer 111 on the substrate 110 and has a fixed potential or ground, further enhancing the grounding effect or potential stabilization effect of the semiconductor layer 111 within the active region 100A of the high electron mobility transistor 100. This is particularly important when the device size increases, as the size of the active region 100A also increases. The buried electrode 142 within the active region 100A allows all semiconductor layers 111 to have a fixed potential or be stably electrically grounded. This allows the high electron mobility transistor of the present invention to significantly reduce dynamic on-resistance in high current and high voltage applications compared to high electron mobility transistors without a conductive structure surrounding the active region. For example, at a voltage of 400 volts (V) and a current of 1 ampere (A), the dynamic on-resistance of embodiments of the present invention is significantly lower. The Ron is reduced by at least about 13% compared to a high electron mobility transistor without a conductive structure surrounding the active region, and at a voltage of 400 volts and a current of 4 amperes, the dynamic on-resistance of embodiments of the present invention is reduced even more significantly by at least about 57% compared to a high electron mobility transistor without a conductive structure surrounding the active region, thereby improving the electrical performance of the high electron mobility transistor.

[0044] According to embodiments of the present invention, the conductive structure surrounding the active region is electrically connected to the semiconductor layer on the substrate and has a fixed potential or ground, which can reduce the dynamic on-resistance (Ron) of the high electron mobility transistor in high voltage and high current applications. Furthermore, the buried electrode in the active region directly contacts the semiconductor layer on the substrate and has a fixed potential or ground, which can further improve the grounding effect or potential stabilization effect of the semiconductor layer in the active region of the high electron mobility transistor. Especially when the device size increases, the high electron mobility transistor of the present invention can significantly reduce the dynamic on-resistance in high current and high voltage applications compared to high electron mobility transistors without a conductive structure surrounding the active region, thereby improving the electrical performance of the high electron mobility transistor.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, several equivalent substitutions or obvious modifications can be made without departing from the concept of the present invention, and all such modifications, achieving the same performance or purpose, should be considered within the scope of protection of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, include: A single base has an active region; A semiconductor layer is disposed on the substrate; A compound semiconductor stack includes a buffer layer, a high-resistivity layer, a channel layer and a barrier layer sequentially disposed on the semiconductor layer; A capping layer is disposed on the compound semiconductor stack; A gate electrode is disposed on the capping layer and extends along a first direction; A source electrode and a drain electrode are disposed on the compound semiconductor stack, respectively located on both sides of the gate electrode and arranged along a second direction, wherein the first direction is perpendicular to the second direction; as well as A buried electrode passes through the compound semiconductor stack, is disposed in the active region and is in direct contact with and electrically connected to the semiconductor layer, and has a fixed potential or ground, wherein the source electrode includes a first portion and a second portion arranged along the first direction, the buried electrode is located between the first portion and the second portion, and the buried electrode is spaced apart from the first portion and the second portion.

2. The high electron mobility transistor as described in claim 1, characterized in that, It also includes a semiconductor layer disposed between the substrate and the compound semiconductor stack, wherein the material of the semiconductor layer includes one or more of silicon, gallium nitride, ceramic, silicon carbide, aluminum nitride, and aluminum oxide.

3. The high electron mobility transistor as described in claim 2, characterized in that, Also includes: A conductive structure extends through the compound semiconductor stack and surrounds the active region, wherein the conductive structure has a fixed potential or is grounded.

4. The high electron mobility transistor as described in claim 3, characterized in that, The buried electrode is electrically connected to the semiconductor layer, or the conductive structure is electrically connected to the semiconductor layer.

5. The high electron mobility transistor as described in claim 1, characterized in that, The buried electrode is electrically connected to the source electrode via an interconnect structure.

6. The high electron mobility transistor as claimed in claim 1, characterized in that, Also includes: A source metal pattern is disposed on the first and second portions of the source electrode, the buried electrode is located directly below the source metal pattern, and the buried electrode is electrically connected to the source electrode via the source metal pattern.

7. A high electron mobility transistor, characterized in that, include: A substrate having an active region, the active region comprising a plurality of repeating units; A semiconductor layer is disposed on the substrate; A compound semiconductor stack includes a buffer layer, a high-resistivity layer, a channel layer and a barrier layer sequentially disposed on the semiconductor layer; as well as A conductive structure passes through the compound semiconductor stack, surrounds the active region and is in direct contact with and electrically connected to the semiconductor layer, and has a fixed potential or ground; Wherein, at least one of the repeating units includes: A capping layer is disposed on the compound semiconductor stack; A gate electrode is disposed on the capping layer and extends along a first direction; and A source electrode and a drain electrode are disposed on the compound semiconductor stack, respectively located on both sides of the gate electrode and arranged along a second direction, wherein the first direction is perpendicular to the second direction, the conductive structure is separated from the source electrode, and the conductive structure is electrically connected to the source electrode via an interconnect structure.

8. The high electron mobility transistor as claimed in claim 7, characterized in that, Also includes: A buried electrode passes through the compound semiconductor stack and is disposed in the active region, and has a fixed potential or ground.

9. The high electron mobility transistor as claimed in claim 7, characterized in that, Also includes: A semiconductor layer is disposed between the substrate and the compound semiconductor stack, wherein the material of the semiconductor layer includes one or more of silicon, gallium nitride, ceramic, silicon carbide, aluminum nitride, and aluminum oxide.

10. The high electron mobility transistor as claimed in claim 8, characterized in that, The source electrode includes a first portion and a second portion arranged along the first direction, the buried electrode is located between the first portion and the second portion, and the buried electrode is spaced apart from the first portion and the second portion.

11. The high electron mobility transistor as claimed in claim 10, characterized in that, The buried electrode is electrically connected to the source electrode via an interconnect structure.

12. The high electron mobility transistor as claimed in claim 10, characterized in that, Also includes: A source metal pattern is disposed on the first and second portions of the source electrode, and the buried electrode is located directly below the source metal pattern and is electrically connected to the source electrode by directly contacting the source metal pattern.

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