Thin Film Transistor Substrate and Electronic Device

Abstract

The present invention provides a thin-film transistor substrate and an electronic device. The thin-film transistor substrate includes: a substrate; a boss, the boss includes an undercut structure, and the undercut structure is located on the sidewall of the boss; a filler located within the undercut structure; an active layer located on the boss and the substrate, the active layer includes a channel, and the channel covers the undercut structure and the filler. By providing a boss including an undercut structure on the thin-film transistor substrate, during the laser annealing process, the active layer material within the undercut structure serves as a seed crystal, and finally a channel composed of a single grain is formed, reducing the length of the channel of the thin-film transistor, which is beneficial to improving the integration degree of the thin-film transistor on the substrate. The channel composed of a single grain has no grain boundaries, improving the mobility of the thin-film transistor.

Description

Technical Field

[0001] This application relates to the field of displays, and in particular, to a thin film transistor substrate and an electronic device. Background Art

[0002] Integrating an integrated circuit (IC) on a glass substrate (System On Glass, SOG) can greatly improve the integration of a display panel and reduce the manufacturing cost of the display panel. However, to achieve SOG, it is necessary to improve the integration, maximum operating frequency, and circuit density of thin film transistors on the substrate, all of which require the thin film transistors to have a shorter channel length, a smaller volume, and a higher mobility. Summary of the Invention

[0003] To solve the above problems, the technical solutions provided by the present invention are as follows:

[0004] The present invention provides a thin film transistor substrate and an electronic device, where the thin film transistor substrate includes:

[0005] A substrate;

[0006] A boss, located on the substrate, the boss including an undercut structure, and the undercut structure being located on the side wall of the boss;

[0007] A filler, located in the undercut structure;

[0008] An active layer, located on the boss and the substrate, the active layer including a channel, and the channel covering the undercut structure and the filler.

[0009] Optionally, in some embodiments of the present invention, the undercut structure is located on a side of the boss close to the substrate.

[0010] Optionally, in some embodiments of the present invention, the channel is a single crystal structure; the length of the channel is greater than or equal to 0.01 micrometers and less than or equal to 1 micrometer; the thickness of the boss is greater than or equal to 800 angstroms and less than or equal to 3000 angstroms.

[0011] Optionally, in some embodiments of the present invention, the boss includes a first film layer and a second film layer, and the first film layer and the second film layer are sequentially stacked on the substrate;

[0012] At the junction of the first film layer and the second film layer, the first film layer is locally recessed to form the undercut structure.

[0013] Optionally, in some embodiments of the present invention, the bottom surface of the second film layer and the side wall of the first film layer form the undercut structure, and the bottom surface is the surface where the second film layer contacts the first film layer.

[0014] Optionally, in some embodiments of the present invention, the distance between the edge of the bottom surface and the side wall of the first film layer is greater than or equal to 0.3 micrometers and less than or equal to 1 micrometer.

[0015] Optionally, in some embodiments of the present invention, the angle between the top surface and the side wall of the second film layer is greater than 90°.

[0016] Optionally, in some embodiments of the present invention, the channel covers at least a part of the side wall of the second film layer.

[0017] Optionally, in some embodiments of the present invention, the ratio of the thickness of the second film layer to the thickness of the first film layer is greater than or equal to 2 and less than or equal to 5; the first film layer is a silicon nitride layer, and the second film layer is a silicon oxide layer.

[0018] Optionally, in some embodiments of the present invention, the thin film transistor substrate further includes a gate insulating layer, a gate, an interlayer insulating layer, and a source-drain layer that are sequentially stacked on the active layer, and the orthographic projection of the gate on the substrate covers the orthographic projection of the channel on the substrate.

[0019] Optionally, in some embodiments of the present invention, the gate insulating layer includes an inclined portion that covers a part of the active layer located on the side wall.

[0020] The gate includes a gate side wall located on the inclined portion, and the slope angle of the gate side wall on the inclined portion is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0021] Optionally, in some embodiments of the present invention, the active layer further includes a first doped region and a second doped region located on opposite sides of the channel and connected to the channel, the source-drain layer includes a source and a drain, and the source and the drain are respectively connected to the first doped region and the second doped region through vias;

[0022] wherein, the first doped region is located on the top of the second film layer, and the second doped region is located on the substrate and is arranged in the same layer as the first film layer.

[0023] Optionally, in some embodiments of the present invention, the channel includes a first channel and a second channel, the undercut structure includes a first undercut structure and a second undercut structure located on both sides of the boss, the first channel covers the first undercut structure, and the second channel covers the second undercut structure;

[0024] The active layer further includes a first doped region located between the first channel and the second channel and disposed on the top of the boss, a second doped region disposed opposite to the first doped region on the other side of the first channel and located on the substrate, and a third doped region disposed opposite to the first doped region on the other side of the second channel and located on the substrate; the source-drain layer includes a first source electrode, a second source electrode, and a drain electrode, the drain electrode is connected to the first doped region through a via, the first source electrode is connected to the second doped region through a via, the second source electrode is connected to the third doped region through a via, and the first source electrode and the second source electrode are electrically connected.

[0025] Optionally, in some embodiments of the present invention, the channel includes a first channel and a second channel, the undercut structure includes a first undercut structure and a second undercut structure located on both sides of the boss, the first channel covers the first undercut structure, and the second channel covers the second undercut structure;

[0026] The active layer further includes a first doped region located between the first channel and the second channel and disposed on the top of the boss, a second doped region disposed opposite to the first doped region on the other side of the first channel and located on the substrate, and a third doped region disposed opposite to the first doped region on the other side of the second channel and located on the substrate; the source-drain layer includes a source electrode and a drain electrode, the source electrode is connected to the second doped region through a via, and the drain electrode is connected to the third doped region through a via.

[0027] The present invention further provides an electronic device, and the electronic device includes the thin film transistor substrate according to any one of the embodiments of the present invention.

[0028] Beneficial effects: The present invention provides a thin film transistor substrate and an electronic device. By providing a boss including an undercut structure on the thin film transistor substrate, during the laser annealing process, the active layer material in the undercut structure serves as a seed crystal, and finally a channel composed of a single grain is formed, reducing the length of the channel of the thin film transistor, which is beneficial to improving the integration degree of the thin film transistor on the substrate. The channel composed of a single grain has no boundary, improving the mobility of the thin film transistor. Description of the Drawings

[0029] The following will make the technical solutions and other beneficial effects of the present application obvious by describing the specific embodiments of the present application in detail in conjunction with the drawings.

[0030] Figure 1 Schematic diagram of the structure of the thin film transistor substrate provided by the prior art;

[0031] Figure 2The first top - view structural schematic diagram of the thin - film transistor substrate provided by the embodiment of the present invention;

[0032] Figure 3 is Figure 2 the cross - sectional view in the AA' direction in;

[0033] Figure 4 is Figure 2 the cross - sectional view in the BB' direction in;

[0034] Figure 5 The second top - view structural schematic diagram of the thin - film transistor substrate provided by the embodiment of the present invention;

[0035] Figure 6 is Figure 5 the first cross - sectional view in the AA' direction in;

[0036] Figure 7 is Figure 5 the second cross - sectional view in the AA' direction in;

[0037] Figure 8 is Figure 5 the third cross - sectional view in the AA' direction in;

[0038] Figure 9 is Figure 5 the cross - sectional view in the BB' direction in;

[0039] Figure 10 The third top - view structural schematic diagram of the thin - film transistor substrate provided by the embodiment of the present invention;

[0040] Figure 11 is Figure 10 the cross - sectional view in the AA' direction in;

[0041] Figure 12 is Figure 10 the cross - sectional view in the BB' direction in;

[0042] Figure 13 The third top - view structural schematic diagram of the thin - film transistor substrate provided by the embodiment of the present invention;

[0043] Figure 14 is Figure 12 the cross - sectional view in the AA' direction in;

[0044] Figure 15 is Figure 12 the cross - sectional view in the BB' direction in;

[0045] Figure 16 The flow chart of the preparation method of the thin - film transistor substrate provided by the embodiment of the present invention;

[0046] Figure 17Structural diagram of the method for preparing a thin film transistor substrate provided by an embodiment of the present invention. Detailed implementation manners

[0047] The following will clearly and completely describe the technical solutions in the implementation manners and / or embodiments of the present invention in combination with the specific implementation manners of the present invention. Obviously, the implementation manners and / or embodiments described below are only a part of the implementation manners and / or embodiments of the present invention, rather than all of the implementation manners and / or embodiments. All other implementation manners and / or embodiments obtained by those of ordinary skill in the art based on the implementation manners and / or embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0048] The directional terms mentioned in the present invention, such as [up], [down], [left], [right], [front], [rear], [inside], [outside], [side], etc., are only with reference to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present invention, rather than for limiting the present invention. Terms such as "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features.

[0049] Please refer to Figure 1 , Figure 1 which is a structural schematic diagram of a thin film transistor substrate in the prior art. Combining Figure 1 it can be seen that in a traditional thin film transistor substrate, the active layer 10 is located on a plane, and the length L of the channel 101 of the active layer 10 is usually greater than 2 micrometers. This makes the channel of the traditional thin film transistor too long and the area ratio of the traditional thin film transistor on the substrate too large, which is not conducive to the high-density integration of thin film transistors on the substrate. In addition, the channel 101 with a length greater than 2 micrometers is composed of multiple grains, and there are many grain boundaries, resulting in a lower mobility of the thin film transistor.

[0050] To solve the above problems, the present invention provides a thin film transistor substrate, which includes: a substrate; a boss, the boss includes an undercut structure, and the undercut structure is located on the side wall of the boss; a filler, located in the undercut structure; an active layer, located on the boss and the substrate, and the active layer includes a channel, and the channel covers the undercut structure and the filler.

[0051] In the present invention, by providing a boss including an undercut structure on a thin-film transistor substrate, during the laser annealing process, the active layer material in the undercut structure serves as a seed crystal, and finally a channel composed of a single grain is formed, reducing the length of the channel of the thin-film transistor, which is beneficial to improving the integration degree of the thin-film transistor on the substrate. The channel composed of a single grain has no boundaries, improving the mobility of the thin-film transistor.

[0052] The following will, through specific embodiments and in conjunction with the drawings, provide a detailed explanation of the thin-film transistor substrate provided by the present invention.

[0053] Embodiment 1

[0054] Please refer to Figures 2 to 4 , Figure 2 which is a first top-view structural schematic diagram of the thin-film transistor substrate provided by the embodiment of the present invention; Figure 3 is Figure 2 a cross-sectional view in the AA' direction of Figure 4 is Figure 2 a cross-sectional view in the BB' direction of . In this embodiment, the thin-film transistor substrate includes a substrate, a filler 236, a boss 22, and an active layer 23.

[0055] The substrate includes an insulating substrate 211, a light-shielding portion 213, and a buffer layer 212. The light-shielding portion is located between the insulating substrate 211 and the buffer layer 212. The insulating substrate 211 can be a glass substrate or a flexible substrate. The orthographic projection of the light-shielding portion 213 on the insulating substrate 211 covers the orthographic projection of the channel 231 on the insulating substrate 211. The light-shielding portion 213 functions to block the light incident from the side of the insulating substrate 211. The material for preparing the light-shielding portion 213 is a metal material, and the metal material includes but is not limited to at least one of molybdenum, aluminum, titanium, copper, and silver. The material for preparing the light-shielding portion 213 can also be a black organic photoresist material, etc. The buffer layer 212 covers the insulating substrate 211 and the light-shielding portion 213. The material for preparing the buffer layer 212 includes at least one of silicon nitride or silicon oxide. The thickness of the buffer layer 212 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms, such as 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms, or 3500 angstroms. In other embodiments, the substrate may also be other structures well-known in the art, which will not be limited herein.

[0056] The boss 22 is located on the substrate, specifically on the buffer layer 212. The boss 22 includes an undercut structure 201, and the undercut structure 201 is located on the sidewall of the boss 22. The boss 22 can be formed by stacking one film layer, two film layers, or more than two film layers. The film layers constituting the boss 22 include an insulating layer, and the insulating layer includes at least one of an inorganic insulating layer and an organic insulating layer. The preparation materials of the inorganic insulating layer include, but are not limited to, silicon oxide or silicon nitride, and the preparation materials of the organic insulating layer include, but are not limited to, polyimide, polyacrylate, and silicone, etc. The film layers constituting the boss 22 can also include a conductive film layer.

[0057] The filler 236 is located in the undercut structure 201, and the filler is amorphous silicon.

[0058] The active layer 23 is located on the boss 22 and the buffer layer 212. The active layer 23 includes a channel 231 and a first doping region 232 and a second doping region 233 located on both sides of the channel 231 in the length direction. Both the first doping region 232 and the second doping region 233 include a heavily doped region and a lightly doped region between the heavily doped region and the channel 231.

[0059] The length of the channel 231 is greater than or equal to 0.01 μm and less than or equal to 1 μm, and the width of the channel 231 is greater than or equal to 0.03 μm and less than or equal to 10 μm. The length is the size of the channel 231 in the direction perpendicular to the width direction of the channel 231, and the width is the size of the channel 231 in the direction parallel to the substrate; the length is also the size of the channel 231 in the direction of the connection of the doping regions. Thus, the length of the channel 231 is reduced compared to the length of the channel of a conventional thin-film transistor (the length is greater than 2 μm), which is beneficial to improving the integration degree of the thin-film transistor on the substrate. On the other hand, the channel 231 covers the undercut structure 201, and the undercut structure 201 is located on the sidewall of the boss 22. Therefore, the channel 231 covers at least part of the sidewall of the boss 22; compared with the channel in a conventional thin-film transistor located on a planar structure, for the same length of the channel, the area ratio of the channel 231 of the present invention on the thin-film transistor substrate is smaller, which is more beneficial to improving the integration degree of the thin-film transistor on the substrate.

[0060] The channel 231 may be located on a partial sidewall of the boss 22. For example, the channel 231 only covers the undercut structure 201 and other partial sidewalls, without extending to the top surface of the boss 22, which is the surface of the boss 22 away from the substrate; or, the channel 231 covers the sidewall of the substrate and extends to the top surface of the boss 22. The heavily doped regions on both sides of the channel 231 are located on the top surface of the boss 22 and the buffer layer 212, respectively.

[0061] The channel 231 covers the undercut structure 201, and the channel 231 is part or all of a single grain, that is, the channel 231 is composed of a single grain. In this way, there is no grain boundary in the channel 231, improving the mobility of the thin film transistor. The channel 231 may also include multiple grains. In other words, the channel 231 includes multiple grain boundaries; after the channel 231 is disposed on the sidewall of the boss 22, the length of the channel 231 is reduced to 0.01 to 1 micrometer, and the grain boundaries of the channel 231 are correspondingly reduced, also improving the mobility of the thin film transistor.

[0062] In an embodiment of the present invention, the size of a single grain constituting the channel 231 is greater than or equal to 0.25 micrometer to adapt to the size of grains formed after the current amorphous silicon is crystallized by an excimer laser annealing process. For example, the size of a single grain is 0.28 micrometer, 0.29 micrometer, 0.30 micrometer, 0.32 micrometer, 0.35 micrometer, 0.36 micrometer, 0.38 micrometer or 0.4 micrometer.

[0063] It should be noted that the grain size obtained by crystallizing the current amorphous silicon by an excimer laser annealing process is small, and the difference from the current channel length greater than 2 micrometers is also large, making it impossible for the channel to be composed of a single crystal grain. However, in the present invention, by controlling the thickness of the boss 22, the length of the channel is reduced, so that the length of the channel tends to be the same as the size of a single crystal grain in the current laser annealing process; in addition, the active layer material in the undercut structure 201 is more likely to form a seed crystal, providing conditions for the seed crystal to grow along the sidewall into a single crystal grain, and further providing conditions for the formation of a single crystal grain channel with a smaller length.

[0064] The active layer 23 is a low-temperature polycrystalline silicon active layer or a crystalline metal oxide active layer, etc. Preferably, the active layer 23 is a low-temperature polycrystalline silicon active layer. The material of the channel 231 is preferably a polycrystalline silicon material, obtained by irradiating amorphous silicon with a laser.

[0065] The ratio of the thickness H of the boss 22 to the thickness of the active layer 23 is greater than or equal to 2 and less than or equal to 7. The thickness of the active layer 23 is generally greater than or equal to 350 Å and less than or equal to 600 Å. Therefore, the thickness H of the boss 22 is greater than or equal to 700 Å and less than or equal to 4200 Å. For example, the ratio of the thickness H of the boss 22 to the thickness of the active layer 23 is 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, 4.0, 4.2, 4.4, 4.6, 4.8, 5.0, 5.2, 5.5, 5.8, 6.0, 6.2, 6.5, 6.8 or 7.0; the thickness of the active layer 23 is 350 Å, 380 Å, 400 Å, 420 Å, 440 Å, 460 Å, 480 Å, 500 Å, 520 Å, 540 Å, 560 Å or 600 Å; the corresponding thickness H of the boss 22 is 1000 Å, 1200 Å, 1400 Å, 1600 Å, 1800 Å, 2000 Å, 2200 Å, 2400 Å, 2600 Å, 2800 Å or 3000 Å.

[0066] In this way, by controlling the thickness of the boss 22, the length of the side wall of the boss 22 is adjusted, and then the length of the channel 231 deposited on the side wall of the boss 22 is controlled, so that the length of the channel 231 is less than or equal to 1 μm. Ideally, the channel 231 is located on the side wall of the boss 22 and just covers the side wall of the boss 22, that is, the channel 231 extends along the side wall of the boss 22 and stops at the junction of the top surface and the side wall of the boss 22, and at the undercut structure 201. However, due to the process deviation problem, the channel 231 is not necessarily in the ideal situation. The channel 231 may extend along the side wall of the boss 22 and stop at the side wall of the boss 22, or the channel 231 may extend to the top surface of the boss 22, or the channel 231 may extend to the buffer layer 212.

[0067] In this embodiment, the undercut structure 201 is formed by the side wall between the top surface of the boss 22 and the buffer layer 212 being recessed into the interior of the boss 22.

[0068] The thin film transistor substrate further includes a gate insulating layer 24, a gate 25, an interlayer insulating layer 26 and a source-drain layer sequentially stacked on the active layer 23.

[0069] The gate insulating layer 24 covers the active layer 23. The gate insulating layer 24 includes an inclined portion that covers the portion of the active layer 23 on the sidewall. The material of the gate insulating layer 24 includes at least one of silicon nitride and silicon oxide. The thickness of the gate insulating layer 24 is greater than or equal to 500 angstroms and less than or equal to 1500 angstroms; for example, the thickness of the gate insulating layer 24 is 600 angstroms, 800 angstroms, 1000 angstroms, 1200 angstroms, 1400 angstroms, or 1500 angstroms.

[0070] The orthographic projection of the gate 25 on the substrate covers the orthographic projection of the channel 231 on the substrate. The gate 25 includes a gate sidewall on the inclined portion, and the slope angle α of the gate sidewall on the inclined portion is greater than or equal to 30 degrees and less than or equal to 60 degrees to adapt to the manufacturing process of the gate 25. Further, the slope angle α can be greater than or equal to 40 degrees and less than or equal to 55 degrees; furthermore, the slope angle α can be greater than or equal to 45 degrees and less than or equal to 50 degrees. For example, the slope angle α can be 30 degrees, 40 degrees, 45 degrees, 48 degrees, 50 degrees, 52 degrees, 55 degrees, 58 degrees, or 60 degrees.

[0071] Adapting to the channel 231, the gate 25 can be disposed only on the inclined portion, or can be disposed on the inclined portion and extend to the platform portion of the gate insulating layer 24. The platform portion is a structure connected to the inclined portion and located above the boss. Specifically, as Figure 3 shown. The material of the gate 25 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0072] The material of the interlayer insulating layer 26 is selected from at least one of silicon nitride and silicon oxide. The thickness of the interlayer insulating layer 26 is greater than or equal to 5000 angstroms and less than or equal to 6500 angstroms, for example, 5200 angstroms, 5400 angstroms, 5500 angstroms, 5600 angstroms, or 5800 angstroms.

[0073] The source-drain layer includes a source 271 and a drain 272. The source 271 and the drain 272 are respectively connected to the second doped region 233 and the first doped region 232 through vias, specifically connected to the heavily doped regions in the second doped region 233 and the first doped region 232. The material of the source-drain layer is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0074] Embodiment 2

[0075] Please refer to Figures 5 to 9, the same or similar parts of this embodiment and the first embodiment will not be described again. The differences between this embodiment and the first embodiment are as follows: The boss 22 includes a first film layer 221 and a second film layer 222. The first film layer 221 is located between the second film layer 222 and the buffer layer 212. The bottom surface of the second film layer 222 and the side wall of the first film layer 221 form the undercut structure 201. The bottom surface is the surface where the second film layer 222 contacts the first film layer 221.

[0076] The distance D between the edge of the bottom surface and the side wall of the first film layer 221 is greater than or equal to 0.3 micrometers and less than or equal to 1 micrometer. The distance D matches the size of a single grain, facilitating the undercut structure 201 to accommodate the active layer material during the subsequent preparation of the active layer 23, and enabling the active layer material within the undercut structure 201 to serve as a seed crystal during the laser annealing process to form a channel 231 composed of single grains outward. The undercut structure 201 provides good conditions for the formation of the seed crystal, greatly improving the yield of single grains.

[0077] The thickness H2 of the second film layer 222 is greater than the thickness H1 of the first film layer. Preferably, the ratio of the thickness H2 of the second film layer 222 to the thickness H1 of the first film layer 221 is greater than or equal to 2 and less than or equal to 5. For example, the thickness H1 is 200 angstroms and the thickness H2 is 800 angstroms, or the thickness H1 is 300 angstroms and the thickness H2 is 1000 angstroms, or the thickness H1 is 400 angstroms and the thickness H2 is 1200 angstroms, or the thickness H1 is 500 angstroms and the thickness H2 is 1400 angstroms, or the thickness H1 is 600 angstroms and the thickness H2 is 1500 angstroms, or the thickness H1 is 700 angstroms and the thickness H2 is 1600 angstroms, or the thickness H1 is 800 angstroms and the thickness H2 is 1800 angstroms, or the thickness H1 is 1000 angstroms and the thickness H2 is 2000 angstroms, etc. In this way, the thickness of the first film layer 221 is relatively small, and the size of the formed undercut structure 201 is small. After laser annealing, there are fewer residual seed crystals inside the undercut structure 201, and it is easier to grow high-quality single grains.

[0078] The included angle β between the top surface and the side wall of the second film layer 222 is greater than 90°, where the top surface is the surface opposite to the bottom surface, the side wall is the surface connecting the top surface and the bottom surface, and the side wall and the channel are on the same side of the boss 22. In this way, the thickness of the second film layer 222 gradually increases in the direction away from the substrate, which is beneficial to the deposition of the active layer material on the boss 22. Further, the included angle β between the top surface and the side wall of the second film layer 222 is less than or equal to 135°, so that the length of the side wall of the boss 22 is not too long, which is beneficial to controlling the length of the channel 231. The side wall of the second film layer 222 can be a planar structure or a curved surface structure, which is not limited here.

[0079] In one embodiment, please refer to Figure 6 , the undercut structure 201 is composed of a partial bottom surface of the second film layer 222 and a partial side wall of the first film layer 221. The undercut structure 201 is located at the junction of the first film layer 221 and the second film layer 222 and is recessed into the first film layer 221.

[0080] In another embodiment, please refer to Figure 7 and Figure 8 , the undercut structure 201 is composed of a partial bottom surface of the second film layer 222 and the entire side wall of the first film layer 221, that is, the undercut structure 201 extends to the buffer layer 212. In one implementation, the orthographic projection of the second film layer 222 on the insulating substrate 211 covers the orthographic projection of the first film layer 221 on the insulating substrate 211, as shown in Figure 7 . In other implementations, the orthographic projection of the second film layer 222 on the insulating substrate 211 and the orthographic projection of the first film layer 221 on the insulating substrate 211 partially do not overlap. Further, the orthographic projection of the first film layer 221 on the insulating substrate 211 covers the orthographic projection of the second film layer 222 on the insulating substrate 211, as shown in Figure 8 ; or, the orthographic projection of the first film layer 221 on the insulating substrate 211 is partially outside the orthographic projection of the second film layer 222 on the insulating substrate 211, and the orthographic projection of the second film layer 222 on the insulating substrate 211 is partially outside the orthographic projection of the first film layer 221 on the insulating substrate 211. The side wall of the first film layer 221 can be a planar structure or a curved surface structure, which is not limited here.

[0081] In one embodiment, the first film layer 221 is a silicon nitride layer, and the second film layer 222 is a silicon oxide layer. The undercut structure 201 can be prepared by a dry etching process. In other embodiments, the first film layer 221 and the second film layer 222 can also be other film layers, as long as the first film layer 221 and the second film layer 222 can form the undercut structure 201.

[0082] The channel 231 covers the undercut structure 201 and extends to at least a part of the sidewall of the second film layer 222. The channel 231 can extend to the junction of the top surface and the side surface of the second film layer 222, or can further extend to the top surface of the second film layer 222, specifically according to the actual manufacturing process and channel design.

[0083] Example 3

[0084] Please refer to Figures 10 to 12 , the same or similar parts between this embodiment and Example 2 will not be described again. The differences between this embodiment and Example 2 are as follows: The active layer 23 includes a first channel 231 and a second channel 234, a first doping region 232 connecting the first channel 231 and the second channel 234, a second doping region 233 disposed opposite to the first doping region 232 on the other side of the first channel 231, and a third doping region 235 disposed opposite to the first doping region 232 on the other side of the second channel 234. The first channel 231 and the second channel 234 are respectively disposed on the sidewalls of opposite sides of the boss 22, and the undercut structures 201 are disposed on the sidewalls of opposite sides of the boss 22. The first channel 231 and the second channel 234 respectively cover the corresponding undercut structures 201. The setting manners of the first channel 231 and the second channel 234 are similar to the setting manner of the channel 231 in Example 1. For details, please refer to the above embodiments and will not be elaborated here.

[0085] The source-drain layer includes a first source 271, a second source 273, and a drain 272. The drain 272 is connected to the first doping region 232 through a via, the first source 271 is connected to the second doping region 233 through a via, the second source 273 is connected to the third doping region 235 through a via, and the first source 271 and the second source 273 are electrically connected.

[0086] The thin film transistor substrate includes a first gate 251 and a second gate 252. Both the first gate 251 and the second gate 252 are disposed on the gate insulating layer 24, and the orthographic projection of the first gate 251 on the substrate overlaps with the orthographic projection of the first channel 231 on the substrate. The first gate 251 and the second gate 252 are similar to the gate 25 in the first embodiment. For details, please refer to the first embodiment and will not be elaborated here.

[0087] The thin film transistor substrate includes a first light-shielding portion 213 and a second light-shielding portion 214. The first light-shielding portion 213 and the second light-shielding portion 214 are disposed between the insulating substrate 211 and the buffer layer 212. The orthographic projection of the first light-shielding portion 213 on the insulating substrate 211 covers the orthographic projection of the first channel 231 on the insulating substrate 211, and the orthographic projection of the second light-shielding portion 214 on the insulating substrate 211 covers the orthographic projection of the second channel 234 on the insulating substrate 211. The first light-shielding portion 213 and the second light-shielding portion 214 are similar to the light-shielding portion 213 in the first embodiment. For details, please refer to the first embodiment and will not be elaborated here.

[0088] In this embodiment, by providing two channels formed by single grains on the sidewall of the boss and connecting the two channels in parallel, compared with the second embodiment, the equivalent width of the thin film transistor is increased.

[0089] Embodiment Four

[0090] Please refer to Figures 13 to 15 , the same or similar parts between this embodiment and the third embodiment will not be described. The difference between this embodiment and the third embodiment is that: the source-drain layer includes a source 271 and a drain 273. The source 271 is connected to the second doped region 233 through a via, and the drain 273 is connected to the third doped region 235 through a via.

[0091] In this embodiment, by providing two channels formed by single grains on the sidewall of the boss and connecting the two channels in series, compared with the second embodiment, the equivalent length of the thin film transistor is increased.

[0092] Correspondingly, an embodiment of the present invention further provides a method for manufacturing a thin film transistor substrate for manufacturing the thin film transistor substrate according to any embodiment of the present invention. Please refer to Figure 16 and Figure 17 , the manufacturing method includes:

[0093] Step B1, preparing a substrate; please refer to Figure 17In (a). The specific steps for preparing the substrate substrate include: providing an insulating substrate 211; preparing a light-shielding portion 213 on the insulating substrate; and preparing a buffer layer 212 on the light-shielding portion 213 and the insulating substrate 211.

[0094] Step B2, preparing a boss on the substrate substrate; wherein, the boss includes an undercut structure located on the sidewall of the boss; please refer to Figure 17 In (b).

[0095] Specifically, the step of preparing a boss on the substrate substrate includes:

[0096] By chemical vapor deposition process, a layer of silicon nitride film 221 and a layer of silicon oxide film 222 are sequentially deposited on the substrate substrate;

[0097] Using a dry etching process, in an atmosphere of a mixture of C2HF5, Ar, and H2, the silicon oxide film 222 and the silicon nitride film 221 are etched to form an inclined side; it should be noted that in an atmosphere of a mixture of C2HF5, Ar, and H2, the etching rates of the silicon oxide film 222 and the silicon nitride film 221 are similar, so the obtained side is relatively smooth;

[0098] Using a dry etching process, in an atmosphere of a mixture of SF6 and O2, the silicon oxide film 222 and the silicon nitride film 221 are etched again to obtain the boss; it should be noted that in an atmosphere of a mixture of SF6 and O2, the etching rate of the silicon oxide film 222 is small, while the etching rate of the silicon nitride film 221 is large. Therefore, after etching, the undercut structure 201 is formed on the side of the boss close to the buffer layer 212.

[0099] Step B3, preparing a filler and an active layer on the boss and the substrate substrate; wherein, the filler is located in the undercut structure, and the active layer includes a channel that covers the undercut structure and the filler; please refer to Figure 17 In (c).

[0100] Specifically, the step of preparing the active layer 23 on the boss and the substrate substrate includes:

[0101] Using chemical vapor deposition process, a layer of amorphous silicon film is deposited on the boss and the substrate substrate; wherein, the amorphous silicon film fills the undercut structure and covers the sidewall of the undercut structure;

[0102] The amorphous silicon thin film is annealed by using an excimer laser annealing process; it should be noted that during this process, the amorphous silicon material in the undercut structure will serve as a seed crystal, and the seed crystal grows into single crystal grains along the active layer on the side wall of the boss, and at least part of the single crystal grains serves as the channel structure of the thin film transistor; by controlling the length of the side wall of the boss, only one grain can exist on the side wall of the boss; after laser annealing, part of the amorphous silicon deep inside the undercut structure is not processed and remains in the undercut structure in the form of a filler, and the amorphous silicon thin film on the side wall of the boss is converted into polycrystalline silicon material.

[0103] The annealed amorphous silicon thin film transistor is patterned to obtain an active layer pattern 23;

[0104] The active layer pattern 23 is subjected to lightly doped region and heavily doped treatment, or only the active layer pattern is subjected to heavily doped treatment, and the lightly doped treatment is carried out in subsequent processes.

[0105] Step B4: Prepare a gate insulating layer and a gate on the active layer; please refer to Figure 17 (d) in

[0106] This step may further include: after the gate 25 is prepared, using the gate 25 as a self-aligned mask template to lightly dope the active layer pattern.

[0107] Step B5: Prepare an interlayer insulating layer on the gate; please refer to Figure 17 (e) in

[0108] Step B6: Prepare a source-drain layer on the interlayer insulating layer; please refer to Figure 17 (f) in

[0109] The embodiment of the present invention also provides an electronic device, and the electrode device includes the thin film transistor substrate according to any one of the embodiments of the present invention. The electronic device may be an integrated circuit board including the thin film transistor substrate; the electronic device may also be a display panel including the thin film transistor substrate, and the display panel may be any one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot display panel, a micro light emitting diode display panel, and a submillimeter light emitting diode display panel; the electronic device may also be other electronic device structures including the thin film transistor substrate.

[0110] In summary, the embodiments of the present invention provide a thin film transistor substrate and an electronic device. The thin film transistor substrate includes: a substrate; a boss, the boss includes an undercut structure, and the undercut structure is located on the side wall of the boss; an active layer, located on the boss and the substrate, the active layer includes a channel, and the channel covers the undercut structure. In the present invention, by providing a boss including an undercut structure on the thin film transistor substrate, during the laser annealing process, the active layer material in the undercut structure serves as a seed crystal, and finally a channel composed of a single grain is formed, reducing the length of the channel of the thin film transistor, which is beneficial to improving the integration degree of the thin film transistor on the substrate. The channel composed of a single grain has no boundary, improving the mobility of the thin film transistor.

[0111] The thin film transistor substrate and the electronic device provided by the embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A thin film transistor substrate, characterized in that Comprising: A substrate; A boss located on the substrate, the boss including an undercut structure on the sidewall of the boss; A filler located within the undercut structure, the filler being amorphous silicon; An active layer located on the boss and the substrate, the active layer including a channel that covers the undercut structure and the filler; The boss includes a first film layer and a second film layer, the first film layer and the second film layer being sequentially stacked on the substrate; At the junction of the first film layer and the second film layer, the first film layer is locally retracted to form the undercut structure; the bottom surface of the second film layer and the sidewall of the first film layer form the undercut structure, and the bottom surface is the surface where the second film layer contacts the first film layer; The undercut structure is located on the side of the boss close to the substrate; 2. The thin film transistor substrate according to claim 1, wherein The channel is a single crystal structure; the length of the channel is greater than or equal to 0.01 micrometers and less than or equal to 1 micrometer; the thickness of the boss is greater than or equal to 800 angstroms and less than or equal to 3000 angstroms; 3. The thin film transistor substrate according to claim 1, wherein The distance between the edge of the bottom surface and the sidewall of the first film layer is greater than or equal to 0.3 micrometers and less than or equal to 1 micrometer; 4. The thin film transistor substrate according to claim 1, characterized in that, The angle between the top surface and the sidewall of the second film layer is greater than 90 degrees; 5. The thin film transistor substrate according to claim 1, wherein The channel covers at least a part of the sidewall of the second film layer; 6. The thin film transistor substrate according to claim 1, wherein The ratio of the thickness of the second film layer to the thickness of the first film layer is greater than or equal to 2 and less than or equal to 5; the first film layer is a silicon nitride layer, and the second film layer is a silicon oxide layer; 7. The thin film transistor substrate according to any one of claims 1 to 6, characterized in that, The thin film transistor substrate further includes a gate insulating layer, a gate, an interlayer insulating layer, and a source-drain layer sequentially stacked on the active layer, and the orthographic projection of the gate on the substrate covers the orthographic projection of the channel on the substrate; 8. The thin film transistor substrate according to claim 7, wherein The gate insulating layer includes an inclined portion that covers a part of the active layer on the sidewall; The gate includes a gate sidewall on the inclined portion, and the slope angle of the gate sidewall on the inclined portion is greater than or equal to 30 degrees and less than or equal to 60 degrees; 9. The thin film transistor substrate according to claim 7, wherein, The active layer further includes a first doped region and a second doped region located on opposite sides of the channel and connected to the channel, and the source-drain layer includes a source and a drain, and the source and the drain are respectively connected to the first doped region and the second doped region through vias; Wherein, the first doped region is located on the top of the second film layer, and the second doped region is located on the substrate and is in the same layer as the first film layer; 10. The thin film transistor substrate according to claim 7, characterized in that, The channel includes a first channel and a second channel, the undercut structure includes a first undercut structure and a second undercut structure located on both sides of the boss, the first channel covers the first undercut structure, and the second channel covers the second undercut structure; The active layer further includes a first doped region located between the first channel and the second channel and disposed on the top of the boss, a second doped region disposed opposite to the first doped region on the other side of the first channel and located on the substrate, and a third doped region disposed opposite to the first doped region on the other side of the second channel and located on the substrate; the source-drain layer includes a first source electrode, a second source electrode, and a drain electrode, the drain electrode is connected to the first doped region through a via, the first source electrode is connected to the second doped region through a via, the second source electrode is connected to the third doped region through a via, and the first source electrode and the second source electrode are electrically connected.

11. The thin film transistor substrate according to claim 7, wherein The channel includes a first channel and a second channel, the undercut structure includes a first undercut structure and a second undercut structure located on both sides of the boss, the first channel covers the first undercut structure, and the second channel covers the second undercut structure; The active layer further includes a first doped region located between the first channel and the second channel and disposed on the top of the boss, a second doped region disposed opposite to the first doped region on the other side of the first channel and located on the substrate, and a third doped region disposed opposite to the first doped region on the other side of the second channel and located on the substrate; the source-drain layer includes a source electrode and a drain electrode, the source electrode is connected to the second doped region through a via, and the drain electrode is connected to the third doped region through a via.

12. An electronic device, characterized in that, Comprising a thin film transistor substrate according to any one of claims 1 to 11.

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