A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof, comprising: a substrate, a source electrode, a drain electrode, a gate electrode and a channel structure arranged on one side of the substrate, the channel structure comprising a plurality of nanosheet formed stacks, the gate electrode surrounding the nanosheet, the nanosheet comprising an edge region and a center region, and in a direction perpendicular to a plane where the substrate is located, the nanosheet thickness of the center region is less than that of the edge region, that is, the nanosheet forms a structure of a thin center and thick edges, the thickness and volume of other structures between adjacent nanosheets are reduced, the parasitic resistance of the semiconductor device is reduced, in addition, the nanosheet thickness of the region close to the source electrode or the drain electrode is larger, and the contact area of the source electrode and the drain electrode is larger, the heat generated by the channel structure can be conducted to the source electrode and the drain electrode through the increased contact area, the heat dissipation efficiency is accelerated, the heat dissipation effect is enhanced, and the performance of the finally manufactured semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate FinFETs are limited by gate failure and leakage current degradation at nodes below 3 nanometers (nm). Since the Nanosheet Gate-all-round Field-Effect Transistor (Nanosheet GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.

[0003] Nanosheet GAAFET is a novel device featuring a gate-around structure and stacked horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers better gate control than FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet GAAFET exhibits bulk inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0004] However, current Nanosheet GAAFETs suffer from high parasitic resistance from the channel to the source / drain due to the inner sidewall isolation between the stacked nanosheet channel and the source / drain, resulting in poor heat dissipation, increased device power consumption, and decreased overall performance. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can reduce the parasitic resistance of the semiconductor device, enhance the heat dissipation effect, and improve the performance of the final manufactured semiconductor device.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Substrate;

[0008] A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets.

[0009] The nanosheet includes an edge region and a central region. The edge region is the area of ​​the nanosheet close to the source or the drain, and the central region is the area of ​​the nanosheet away from the source or the drain. In a direction perpendicular to the plane of the substrate, the thickness of the nanosheet in the central region is less than the thickness of the nanosheet in the edge region.

[0010] A gate, which surrounds the nanosheet.

[0011] Optionally, the thickness of the nanosheet gradually increases along the direction from the central region of the nanosheet toward the edge region of the nanosheet.

[0012] Optionally, an inner wall is provided between adjacent nanosheets, and in a direction perpendicular to the plane of the substrate, the thickness of the inner wall on the side closer to the source or drain is less than the thickness of the inner wall away from the source or drain.

[0013] Optionally, the thickness of the inner wall gradually decreases along the direction from the central region of the nanosheet toward the edge region of the nanosheet.

[0014] Optionally, the interface between the inner wall and the nanosheet is an arc surface.

[0015] Optionally, the material of the inner wall is one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, low-k materials, and air.

[0016] This application provides a method for manufacturing a semiconductor device, the method comprising:

[0017] A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate;

[0018] The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region;

[0019] The first semiconductor layer located in the channel region is selectively etched along a first direction. In a direction perpendicular to the plane of the substrate, the thickness of the second semiconductor layer in the central region is less than the thickness of the second semiconductor layer in the edge region. The second semiconductor layer includes an edge region and a central region. The edge region is the region of the second semiconductor layer close to the source region or the drain region, and the central region is the region of the second semiconductor layer away from the source region or the drain region. The line connecting the source region and the drain region is the first direction.

[0020] A source and a drain are formed in the source region and the drain region, respectively.

[0021] The first semiconductor layer is replaced with a gate, which surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure.

[0022] Optionally, the selective etching of the first semiconductor layer located in the channel region along the first direction includes:

[0023] Along the first direction, the first semiconductor layer is etched using a selective cavity etching process.

[0024] Optionally, before the source and drain regions are formed, the method further includes:

[0025] An inner wall is formed in the channel region, the inner wall being located between adjacent second semiconductor layers.

[0026] Optionally, replacing the first semiconductor layer with a gate includes:

[0027] The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers.

[0028] The gate is filled in one of the multiple gaps to be filled.

[0029] This application provides a semiconductor device comprising: a substrate; a source, a drain, a gate, and a channel structure disposed on one side of the substrate; the channel structure being located between the source and drain; the channel structure comprising a stack of multiple nanosheets; the gate surrounding the nanosheets; and the nanosheets comprising an edge region and a central region. The edge region is the area of ​​the nanosheet close to the source or drain, and the central region is the area of ​​the nanosheet away from the source or drain. In a direction perpendicular to the plane of the substrate, the thickness of the nanosheet in the central region is less than the thickness of the nanosheet in the edge region. That is, the nanosheet forms a structure that is thin in the middle and thick at the edges, reducing the thickness and volume of other structures between adjacent nanosheets, and lowering the parasitic resistance of the semiconductor device. In addition, the nanosheet in the region close to the source or drain is thicker, increasing the contact area with the source and drain. The heat generated by the channel structure can be conducted to the source and drain through the increased contact area, accelerating heat dissipation efficiency, enhancing heat dissipation effect, and improving the performance of the finally manufactured semiconductor device. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application is shown;

[0032] Figure 2 and Figure 3 Provided for the embodiments of this application Figure 1 The diagram shows cross-sectional structures of a semiconductor device in various directions.

[0033] Figure 4A and Figure 4B Provided for the embodiments of this application Figure 1 The diagram shows cross-sectional structures of a semiconductor device in various directions.

[0034] Figure 5 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;

[0035] Figures 6-20 show schematic diagrams of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0037] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0038] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate FinFETs are limited by gate failure and leakage current degradation at nodes below 3 nanometers (nm). Since the Nanosheet Gate all-round Field-Effect Transistor (Nanosheet GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.

[0039] Nanosheet GAAFET is a novel device featuring a gate-around structure and stacked horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers better gate control than FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet GAAFET exhibits bulk inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0040] However, the current stacked nanosheets are suspended channel structures, which are prone to heat accumulation and hot spot phenomenon when operating with high current, leading to uncontrolled device characteristics. Furthermore, as the channel size shrinks, the thermal conductivity of the material decreases rapidly, making the hot spot phenomenon even more severe.

[0041] Furthermore, in the fabrication process of Nanosheet GAAFETs, the formation of inner sidewalls between the channel structure and the source and drain electrodes to limit the lateral expansion of the gate during subsequent nanosheet processes, and the filling insulating dielectric material and its thickness, have a significant impact on the parasitic resistance and capacitance of the device in the source and drain regions. The narrow contact area between the conductive channel and the inner sidewalls also affects heat dissipation capabilities.

[0042] In other words, current Nanosheet GAAFETs have a large parasitic resistance from the channel to the source / drain due to the inner sidewall isolation between the stacked nanosheet channel and the source / drain, resulting in poor heat dissipation, increased device power consumption, and decreased overall performance.

[0043] Based on this, embodiments of this application provide a semiconductor device, comprising: a substrate, a source, a drain, a gate, and a channel structure disposed on one side of the substrate, the channel structure being located between the source and the drain, the channel structure comprising a stack of multiple nanosheets, the gate surrounding the nanosheets, the nanosheets comprising an edge region and a central region, the edge region being the region of the nanosheets close to the source or drain, and the central region being the region of the nanosheets far from the source or drain, in a direction perpendicular to the plane of the substrate, the thickness of the nanosheets in the central region is less than the thickness of the nanosheets in the edge region, that is, the nanosheets form a structure that is thin in the middle and thick at the edges, reducing the thickness and volume of other structures between adjacent nanosheets, reducing the parasitic resistance of the semiconductor device, and furthermore, the nanosheets in the region close to the source or drain are thicker, increasing the contact area with the source and drain, the heat generated by the channel structure can be conducted to the source and drain through the increased contact area, accelerating heat dissipation efficiency, enhancing heat dissipation effect, and improving the performance of the finally manufactured semiconductor device.

[0044] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0045] See Figure 1 The figure is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application.

[0046] The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, and a gate 160.

[0047] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0048] In the embodiments of this application, a source 131, a drain 132, and a channel structure are disposed on one side of the substrate 110. The channel structure is disposed between the source 131 and the drain 132, and includes a stack of multiple nanosheets. The channel structure is obtained by removing the first semiconductor layer 121 from the stacked structure. The stacked structure is composed of alternating layers of the first semiconductor layer 121 and the second semiconductor layer 122. That is, the nanosheets in the channel structure are the second semiconductor layer 122 in the stacked structure. (Refer to...) Figure 2 and Figure 3 As shown, where, Figure 2 Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 3 Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional structure of the semiconductor device in the XX direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.

[0049] In the embodiments of this application, there is a gap between the multiple nanosheets in the channel structure, and the gap is filled with a gate 160, that is, the gate 160 surrounds the nanosheets to form a ring gate structure.

[0050] In embodiments of this application, the nanosheet may include an edge region and a central region, wherein, in a direction parallel to the plane of the substrate 110, the edge region is the area of ​​the nanosheet close to the source 131 or drain 132, and the central region is the area of ​​the nanosheet away from the source 131 or drain 132. (See reference...) Figure 3 As shown, the central region of the nanosheet is located between the edge regions on both sides.

[0051] In the direction perpendicular to the plane of substrate 110, the thickness of the nanosheets in the central region is smaller than that in the edge region. (Reference) Figure 3As shown, the nanosheets form a structure that is thin in the middle and thick at the edges, reducing the thickness and volume of other structures between adjacent nanosheets, thus lowering the parasitic resistance of the semiconductor device. In addition, the thickness of the nanosheet edge region near the source 131 or drain 132 is relatively large, increasing the contact area between the nanosheets and the source 131 and drain 132. The heat generated by the channel structure can be conducted to the source 131 and drain 132 through the increased contact area, accelerating heat dissipation efficiency, enhancing heat dissipation effect, and improving the performance of the finally manufactured semiconductor device.

[0052] In the embodiments of this application, the thickness of the nanosheet gradually increases along the direction from the center region of the nanosheet to the edge region of the nanosheet. That is, the nanosheet forms a structure that gradually thickens from the center region to the edge region. By using this gradually thickening structure to gradually increase the thickness of the edge region of the nanosheet, a larger contact area between the nanosheet and the source electrode 131 and the drain electrode 132 can be achieved, thereby improving the heat dissipation effect.

[0053] Specifically, the thickness difference between the central and edge regions of the nanosheet can range from 1 nm to 30 nm.

[0054] In embodiments of this application, an inner wall 206 is provided between adjacent nanosheets. The inner wall 206 can be disposed between adjacent nanosheets, the source 131, and the drain 132 to limit the lateral expansion of the gate 160 during subsequent nanosheet processes. (See reference...) Figure 3 As shown, in the direction perpendicular to the plane of the substrate 110, the thickness of the inner sidewall 206 near the source 131 or drain 132 is less than the thickness of the inner sidewall 206 away from the source 131 or drain 132. In other words, the inner sidewall 206 forms a structure with a thinner thickness near the source 131 or drain 132, reducing the thickness and volume of the inner sidewall 206, thereby reducing the parasitic resistance of the semiconductor device and improving the performance of the semiconductor device.

[0055] In the embodiments of this application, the thickness of the inner sidewall 206 gradually decreases along the direction from the center region of the nanosheet towards the edge region of the nanosheet. That is, the inner sidewall 206 forms a gradually thinning structure. By using this gradually thinning structure to gradually reduce the thickness of the inner sidewall 206, the volume of the inner sidewall 206 is reduced, thereby reducing the parasitic resistance of the channel structure and improving the performance of the semiconductor device.

[0056] In the embodiments of this application, the thickness of the nanosheet gradually increases along the direction from the center region of the nanosheet towards the edge region of the nanosheet, while the thickness of the inner sidewall 206 gradually decreases. Based on the corresponding thickness variation trends of the nanosheet and the inner sidewall 206, the interface between the nanosheet and the inner sidewall 206 can have various shapes.

[0057] As an example, the interface between the inner wall 206 and the nanosheet is curved, which can form a more gentle contact interface and avoid the performance degradation of semiconductor devices due to interface issues.

[0058] In practical applications, the interface between the inner wall 206 and the nanosheet can also be a multi-faceted or irregular interface, which can be adjusted according to the actual manufacturing process.

[0059] In the embodiments of this application, the material of the inner wall 206 may be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, low-k materials and air. The material of the inner wall 206 is air, which means that an air cavity can be formed at the location of the inner wall 206, and the function of the inner wall 206 is achieved by utilizing the air cavity.

[0060] In embodiments of this application, a high-k dielectric layer 150 may also be disposed between the gate 160 and the nanosheet, that is, the high-k dielectric layer 150 is disposed around the nanosheet, as shown in the reference. Figure 4A and Figure 4B As shown.

[0061] As an example, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0062] In embodiments of this application, the semiconductor device further includes a shallow trench isolation 203, a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.

[0063] Shallow trench isolation 203 is disposed between different fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than or lower than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.

[0064] The second sidewall 205 is disposed on the side of the channel structure away from the substrate 110, and the gate 160 is located between the second sidewalls 205. The isolation layer 207 is disposed on the side of the source 131 or drain 132 away from the substrate 110, and the second sidewall 205 and the gate 160 are located between the isolation layers 207.

[0065] The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160. The top dielectric layer 170 has a contact electrode 180 for electrically leading out the source 131 or the drain 132.

[0066] Therefore, the semiconductor device provided in this application includes: a substrate, a source, a drain, a gate, and a channel structure disposed on one side of the substrate. The channel structure is located between the source and the drain and includes a stack of multiple nanosheets. The gate surrounds the nanosheets. The nanosheets include an edge region and a central region. The edge region is the area of ​​the nanosheet close to the source or drain, and the central region is the area of ​​the nanosheet away from the source or drain. In the direction perpendicular to the plane of the substrate, the thickness of the nanosheet in the central region is less than the thickness of the nanosheet in the edge region. That is, the nanosheets form a structure that is thin in the middle and thick at the edges, which reduces the thickness and volume of other structures between adjacent nanosheets and reduces the parasitic resistance of the semiconductor device. In addition, the nanosheets in the region close to the source or drain are thicker, and the contact area with the source and drain is larger. The heat generated by the channel structure can be conducted to the source and drain through the increased contact area, which accelerates the heat dissipation efficiency, enhances the heat dissipation effect, and improves the performance of the finally manufactured semiconductor device.

[0067] Based on the semiconductor device provided in the above embodiments, this application also provides a method for manufacturing a semiconductor device, and its working principle will be described in detail below with reference to the accompanying drawings.

[0068] See Figure 5 The figure is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application.

[0069] The method for manufacturing a semiconductor device provided in this application includes the following steps:

[0070] S101, a substrate 110 is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 is formed on one side of the substrate 110, with reference to... Figure 6A and Figure 6B As shown.

[0071] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0072] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate 110 varies depending on the device type. For P-type semiconductor devices, the highly doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

[0073] In embodiments of this application, a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 can be formed on one side of the substrate 110, as shown in the reference. Figure 6A and Figure 6B As shown, where, Figure 6A Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 6B Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional structure of the semiconductor device in the XX direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.

[0074] The first semiconductor layer 121 and the second semiconductor layer 122 can be formed using an epitaxial process.

[0075] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0076] In practical applications, silicon oxide may be formed on the substrate 110. The stacked structure can be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0077] S102, etching is performed on the stacked structure to form the source region 101 and the drain region 102, reference. Figure 12A and Figure 12B As shown.

[0078] In embodiments of this application, the stacked structure can be etched to form a source region 101 and a drain region 102, wherein a channel region 103 is formed between the source region 101 and the drain region 102. (Refer to...) Figure 12A and Figure 12B As shown.

[0079] The specific process flow for forming the source region 101 and the drain region 102 is as follows:

[0080] S1021, Sidewall Transfer Process, Reference Figure 7A and Figure 7B As shown.

[0081] In the embodiments of this application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern. Silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.

[0082] S1022, forming fins, see reference. Figure 8A and Figure 8B As shown.

[0083] In the embodiments of this application, the stacked structure can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 8A and Figure 8B As shown, etching is performed using the first sidewall 201 as a mask to form a fin with a stacked structure. The upper part of the fin is the channel region 103 formed by the stacked structure, and the lower part of the fin is the substrate 110, forming a structure as shown. Figure 8A The fin shown is not only a stacked structure but also includes a single-crystal silicon structure extending into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin will be used to form nanosheets for semiconductor devices. Although Figure 8A A fin is shown, and it should be understood that any suitable number and shape of fins can be used in practical applications.

[0084] S1022, forming shallow trench isolation 203 (STI), see reference. Figure 9A and Figure 9B As shown.

[0085] In embodiments of this application, shallow trench isolation 203 can be formed between different fins. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as CMP, and then a selective etch-back process of the dielectric insulating material to expose the three-dimensional fins, thereby forming shallow trench isolation 203 between adjacent fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.

[0086] In practical applications, when forming shallow trench isolation 203, the first sidewall 201 can also be removed.

[0087] S1023, forming a dummy gate 204, reference. Figure 10A and Figure 10B As shown.

[0088] In the embodiments of this application, a dummy gate stack is formed on the exposed fin in a direction perpendicular to the fin lines, i.e., in the YY direction. The dummy gate stack is a multilayer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.

[0089] S1024, forming the second sidewall 205, see reference. Figure 11A and Figure 11B As shown.

[0090] In the embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack along the fin direction, i.e., the XX direction, and the thickness of the second sidewalls 205 on both sides is the same. The material of the second sidewalls 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0091] In the embodiments of this application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process, specifically source and drain etching on the fins. The source region 101 and the drain region 102 no longer have a stacked structure after etching. (Refer to...) Figure 12B As shown.

[0092] S103, selectively etch the first semiconductor layer 121 located in the channel region 103 along the first direction, reference Figure 13A and Figure 13B As shown.

[0093] In the embodiments of this application, the first semiconductor layer 122 in the stacked structure located in the channel region 103 is selectively etched along a first direction, namely the direction of the line connecting the source region 101 and the drain region 102, i.e., the XX direction. During the etching process, funnel-shaped lateral etching can be achieved by multiple step etching steps and adjusting the anisotropic etching ratio, so that the thickness of the second semiconductor layer 122 in the central region is less than the thickness of the second semiconductor layer 122 in the edge region in the direction perpendicular to the plane of the substrate 110. In the direction parallel to the plane of the substrate 110, the second semiconductor layer 122 includes an edge region and a central region. The edge region is the area of ​​the second semiconductor layer 122 close to the source region 101 or the drain region 102, and the central region is the area of ​​the second semiconductor layer 122 far away from the source region 101 or the drain region 102.

[0094] Along the XX direction, the portion of the first semiconductor layer 121 missing from the second semiconductor layer 122 forms an embedded cavity structure 401. That is, selective anisotropic etching is performed, etching away a portion of the first semiconductor layer 121 from the source region 101 and drain region 102 towards the channel region 103. (Refer to...) Figure 13A and Figure 13B As shown.

[0095] Specifically, a second semiconductor layer 122 that gradually thickens from the center region to the edge region can be formed by using a selective cavity etching process and adjusting the cavity etching parameters.

[0096] As an example, the cavity etching process can be used to form a second semiconductor layer 122 that widens from the inside out in an arc shape.

[0097] S104, source 131 and drain 132 are formed in source region 101 and drain region 102, respectively, for reference. Figure 15A and Figure 15B As shown.

[0098] In the embodiments of this application, after etching the stacked structure to form the source region 101 and the drain region 102, the source 131 and drain 132 can be selectively epitaxially formed outward from the source region 101 and the drain region 102, respectively, using the remaining second semiconductor layer 122 as the growth base. (Refer to...) Figure 15A and Figure 15B As shown.

[0099] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain epitaxial materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain epitaxial materials are phosphorus-doped silicon, i.e., Si:P.

[0100] In the embodiments of this application, before forming the source 131 and drain 132, an inner sidewall 206 may be formed in the channel region 103. The specific process flow is as follows:

[0101] S1041, forming inner wall 206, reference Figure 14A and Figure 14B As shown.

[0102] In the embodiments of this application, after etching the first semiconductor layer 121, a dielectric material is deposited on the stacked structure located in the channel region 103, i.e., the periphery of the fins. The dielectric material is etched to form an inner sidewall 206. The inner sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. That is, the embedded cavity structure 401 formed by etching in S103 is filled by the inner sidewall 206. The material of the inner sidewall 206 can be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, low-k materials, and air. The use of air as the material of the inner sidewall 206 means that an air cavity can be formed at the location of the inner sidewall 206, thereby achieving the function of the inner sidewall 206.

[0103] In embodiments of this application, after forming the source 131 and drain 132, the dummy gate 204 can be removed, see reference. Figure 16A and Figure 16B As shown.

[0104] In embodiments of this application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, source 131, and drain 132 to prevent short circuits between the dummy gate 204 and the source 131 or drain 132 in subsequent steps. The isolation layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 16A and Figure 16B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.

[0105] S105, replace the first semiconductor layer 121 with the gate 160, as shown in Figures 17-19.

[0106] In embodiments of this application, the first semiconductor layer 121 can be replaced with the gate 160, as shown in Figures 17-19.

[0107] The specific process flow is as follows:

[0108] S1051, remove the first semiconductor layer 121 of the channel region 103, reference Figure 17A and Figure 17B As shown.

[0109] In embodiments of this application, the first semiconductor layer 121 of the channel region 103 can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, see reference. Figure 17A and Figure 17B As shown.

[0110] Specifically, the first semiconductor layer 121 in the stacked structure located in the channel region 103 can be selectively etched to release the nanosheet channel. That is, the stacked structure exposed by the fins is processed to remove the first semiconductor layer 121 of each layer, which is the sacrificial layer, to release the nanosheets formed by the second semiconductor layer 122.

[0111] In the embodiments of this application, there are several possible ways to achieve nanosheet channel release for different types of devices:

[0112] In a first possible implementation, for both P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-laminated nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0113] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon. Silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon-germanium, to form a silicon-germanium stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon-germanium can be used.

[0114] In a third possible implementation, for N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0115] S1052, a high-k dielectric layer 150 is formed on the surface of the second semiconductor layer 122, reference. Figure 18A and Figure 18B As shown.

[0116] In embodiments of this application, after removing the first semiconductor layer 121, a high-k dielectric layer 150 may be formed on the surface of the second semiconductor layer 122. The high-k dielectric layer 150 surrounds the surface of the second semiconductor layer 122. (Refer to...) Figure 18A and Figure 18B As shown. Specifically, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0117] In embodiments of this application, the high-k dielectric layer 150 may further include an interface oxide layer (IL) (not shown).

[0118] S1053, fill the gate 160 in multiple gaps 402 to be filled, reference. Figure 19A and Figure 19B As shown.

[0119] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122. A gate 160 can be filled into these gaps 402, and the gate 160 surrounds the second semiconductor layers 122, forming a gate-ring structure. The stack of multiple second semiconductor layers 122 forms a channel structure, i.e., a nanosheet channel for a semiconductor device. (Refer to...) Figure 19A and Figure 19B As shown.

[0120] In embodiments of this application, the gate 160 may further include a multilayer structure such as a diffusion barrier layer, a work function layer, and a conductive filling layer (not shown).

[0121] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the isolation layer 207 and the dummy gate 204 is removed. The gate 160 covered by the isolation layer 207 can be chemically mechanically polished to perform planarization.

[0122] In embodiments of this application, after forming the gate 160, dielectric deposition can be performed on the top of the semiconductor device away from the substrate 110 to form a top dielectric layer 170, as shown in the reference. Figure 20A and Figure 20B As shown.

[0123] In the embodiments of this application, contact hole etching is performed in the top dielectric layer 170, etching down to the surface of the source 131 or drain 132, and metal material is deposited in the contact holes to form the contact electrodes 180 of the source 131 or drain 132. (Refer to...) Figure 4A and Figure 4B As shown, subsequent processes include multi-layer back-end interconnection and passivation protection.

[0124] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The apparatus embodiments described above are merely illustrative. The units and modules described as separate components may or may not be physically separate. Furthermore, some or all of the units and modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0125] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Substrate; A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets. The nanosheet includes an edge region and a central region. The edge region is the area of ​​the nanosheet close to the source or the drain, and the central region is the area of ​​the nanosheet away from the source or the drain. In a direction perpendicular to the plane of the substrate, the thickness of the nanosheet in the central region is less than the thickness of the nanosheet in the edge region. A gate, the gate surrounding the nanosheet; An inner wall is provided between adjacent nanosheets. In a direction perpendicular to the plane of the substrate, the thickness of the inner wall on the side closer to the source or the drain is less than the thickness of the inner wall away from the source or the drain. The interface between the inner wall and the nanosheet is an arc surface.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the nanosheet gradually increases along the direction from the center region of the nanosheet towards the edge region of the nanosheet.

3. The semiconductor device according to claim 2, characterized in that, The thickness of the inner wall gradually decreases along the direction from the center region of the nanosheet toward the edge region of the nanosheet.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The material of the inner wall is one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, low-k materials, and air.

5. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate; The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region; The first semiconductor layer located in the channel region is selectively etched along a first direction. In a direction perpendicular to the plane of the substrate, the thickness of the second semiconductor layer in the central region is less than the thickness of the second semiconductor layer in the edge region. The second semiconductor layer includes an edge region and a central region. The edge region is the region of the second semiconductor layer close to the source region or the drain region, and the central region is the region of the second semiconductor layer away from the source region or the drain region. The line connecting the source region and the drain region is the first direction. A source and a drain are formed in the source region and the drain region, respectively. The first semiconductor layer is replaced with a gate, the gate surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure; The selective etching of the first semiconductor layer located in the channel region along the first direction includes: Along the first direction, the first semiconductor layer is etched using a selective cavity etching process. Before the source and drain regions are formed, respectively, the method further includes: An inner sidewall is formed in the channel region, the inner sidewall being located between adjacent second semiconductor layers; In a direction perpendicular to the plane of the substrate, the thickness of the inner wall on the side closer to the source or the drain is less than the thickness of the inner wall away from the source or the drain. The interface between the inner wall and the second semiconductor layer is an arc surface.

6. The manufacturing method according to claim 5, characterized in that, The step of replacing the first semiconductor layer with a gate includes: The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. The gate is filled in one of the multiple gaps to be filled.

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