Micro LED chip and preparation method thereof
By introducing a non-conductive current regulation layer into the micro LED chip, the current flow is adjusted, which solves the problem of charge carriers flowing to the sidewalls under low current conditions in micro LEDs and improves luminous efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGZHOU CHANGELIGHT
- Filing Date
- 2022-12-23
- Publication Date
- 2026-06-02
AI Technical Summary
Miniature LEDs have poor luminous efficiency under low current conditions, mainly due to the reduction in efficiency caused by nonradiative recombination of charge carriers at sidewall defects.
A first current adjustment layer and a second current adjustment layer are introduced into the N-type and P-type layers of the micro LED chip. The regions of both layers near the sidewalls of the epitaxial structure are non-conductive, thereby adjusting the current flow, blocking the flow of charge carriers to the sidewalls, and promoting radiative recombination of charge carriers in the active layer.
It effectively suppresses nonradiative recombination caused by sidewall defects and improves the luminous efficiency of micro LED chips under low current conditions.
Smart Images
Figure CN115986024B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of LED chip technology, and in particular to a micro LED chip and a method for fabricating the micro LED chip. Background Technology
[0002] In recent years, with the rapid development of the micro-display field, miniature LEDs such as Mini / Micro LEDs have also developed rapidly, demonstrating great potential application value in the micro-display field. However, the luminous efficiency of miniature LEDs drops sharply under low current conditions, resulting in poor luminous efficiency. Therefore, providing a miniature LED chip with good luminous efficiency under low current conditions has become a research focus in the current field of micro-LED research. Summary of the Invention
[0003] In view of this, this application provides a micro LED chip and a method for fabricating the same, as follows:
[0004] A micro LED chip, comprising:
[0005] The N-type layer, active layer, and P-type layer are arranged sequentially from bottom to top. The P-type layer includes a P-type stacked structure and a P-type current spreading layer. The lower surface of the stacked structure is connected to the active layer, and the upper surface is connected to the P-type current spreading layer, exposing part of the P-type current spreading layer.
[0006] An N-type metal electrode is located on the side of the N-type layer away from the active layer;
[0007] A P-type metal electrode is located on the exposed portion of the P-type current extension layer facing the active layer.
[0008] The N-type layer includes a first current adjustment layer, and the P-type layer includes a second current adjustment layer located in the P-type stacked structure. The first current adjustment layer includes a first preset region and two second preset regions, which are located on both sides of the first preset region and are non-conductive. The second current adjustment layer includes a third preset region and two fourth preset regions, which are located on both sides of the third preset region and are non-conductive.
[0009] Optionally, the first current adjustment layer includes a first sub-layer, a second sub-layer, and a third sub-layer stacked sequentially from bottom to top;
[0010] Wherein, the portion of the first sub-layer located in the first preset region is Al. x Ga 1-xThe As layer, the portion of the second sub-layer located in the first preset region is an AlAs layer, and the portion of the third sub-layer located in the first preset region is an Al layer. y Ga 1-y As layer; the portions of the first sub-layer, the second sub-layer, and the third sub-layer located in the two second preset regions are Al2O3 layers.
[0011] Optionally, Al in the first sub-layer x Ga 1-x The content of Al component in the As layer is x, where 0.6 ≤ x < 1; the Al content in the third sublayer is... y Ga 1-y The content of Al component in the As layer is y, where 0.6 ≤ y < 1;
[0012] The thickness of the first sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values; the thickness of the second sublayer ranges from 30 angstroms to 150 angstroms, including the endpoint values; and the thickness of the third sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values.
[0013] Optionally, the second current adjustment layer includes a fourth sub-layer, a fifth sub-layer, and a sixth sub-layer stacked sequentially from bottom to top;
[0014] Wherein, the portion of the fourth sub-layer located in the third preset region is A1 m Ga 1-m The fifth sub-layer located in the third preset region is an AlAs layer, and the sixth sub-layer located in the third preset region is an Al layer. n Ga 1-n As layer; the portions of the fourth, fifth, and sixth sub-layers located in the two fourth preset regions are Al2O3 layers.
[0015] Optionally, the Al in the fourth sub-layer m Ga 1-m The content of Al component in the As layer is m, where 0.6 ≤ m < 1; the Al content in the sixth sublayer n Ga 1-n The content of Al component in the As layer is n, where 0.6 ≤ n < 1;
[0016] The thickness of the fourth sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values; the thickness of the fifth sublayer ranges from 30 angstroms to 150 angstroms, including the endpoint values; and the thickness of the sixth sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values.
[0017] Optionally, the N-type layer includes an N-type ohmic contact layer, an N-type current spreading layer, a first current adjusting layer, and an N-type confinement layer stacked sequentially from bottom to top; wherein, the N-type confinement layer is connected to the active layer, and the N-type metal electrode is located on the side of the N-type ohmic contact layer away from the active layer;
[0018] The P-type stacked structure includes a P-type confinement layer, a second current adjustment layer, and a transition layer stacked sequentially from bottom to top; wherein the P-type confinement layer is connected to the active layer, and the transition layer is connected to the P-type current extension layer.
[0019] Optionally, the doping element of the N-type ohmic contact layer is Si or Te, and the doping concentration is 1E18 to 5E18, including the endpoint value;
[0020] The doping element of the N-type current spreading layer is Si or Te, and the doping concentration is 1E18 to 5E18, including the endpoint value.
[0021] The first current adjustment layer is doped with Si or Te, and the doping concentration is 1E18 to 3E18, including the endpoint values.
[0022] The doping element of the N-type confinement layer is Si or Te, and the doping concentration is 0.8E18 to 3E18, including the endpoint values;
[0023] The doping element of the P-type confinement layer is Mg or Zn, and the doping concentration is 0.5E18 to 2E18, including the endpoint values;
[0024] The doping element of the second current adjustment layer is Mg, Zn or C, and the doping concentration is 1E18 to 3E18, including the endpoint value;
[0025] The doping element of the transition layer is Mg or Zn, and the doping concentration is 3E18 to 5E18, including the endpoint values.
[0026] The doping element of the P-type current spreading layer is Mg, Zn, or C, and the doping concentration is 1E18 to 3E18, including the endpoint values.
[0027] A method for fabricating a micro LED chip, comprising:
[0028] An N-type layer, an active layer, and a P-type layer are formed in sequence. The P-type layer includes a stacked structure and a P-type current spreading layer. The lower surface of the stacked structure is in contact with the active layer, and the upper surface is in contact with the P-type current spreading layer, exposing part of the P-type current spreading layer.
[0029] An N-type metal electrode is formed, wherein the N-type metal electrode is located on the side of the N-type layer opposite to the active layer;
[0030] A P-type metal electrode is formed, wherein the P-type metal electrode is located on the side of the exposed portion of the P-type current extension layer facing the active layer;
[0031] The N-type layer includes a first current adjustment layer, and the P-type layer includes a second current adjustment layer located in the P-type stacked structure. The first current adjustment layer includes a first preset region and two second preset regions, which are located on both sides of the first preset region and are non-conductive. The second current adjustment layer includes a third preset region and two fourth preset regions, which are located on both sides of the third preset region and are non-conductive.
[0032] Optionally, the N-type layer, active layer, and P-type layer stacked sequentially include:
[0033] Provide a substrate;
[0034] An etching structure is formed on the surface of the substrate, the etching structure comprising, in sequence: a buffer layer, an etching stop layer, an N-type ohmic contact layer, an N-type current spreading layer, a first initial current adjustment layer, an N-type confinement layer, an active layer, a P-type confinement layer, a second initial current adjustment layer, a transition layer, and a P-type current spreading layer.
[0035] Remove the substrate, the buffer layer, and the corrosion stop layer;
[0036] The etched structure is etched along the N-type ohmic contact layer to expose a portion of the P-type current spreading layer;
[0037] Subsequently, the first initial current adjustment layer and the second initial current adjustment layer are subjected to wet oxidation to form the first current adjustment layer and the second current adjustment layer, respectively, forming an N-type layer, an active layer and a P-type layer stacked sequentially.
[0038] The N-type layer includes an N-type ohmic contact layer, an N-type current spreading layer, a first current adjusting layer, and an N-type confinement layer stacked sequentially. The N-type confinement layer is connected to the active layer, and the N-type metal electrode is located on the side of the N-type ohmic contact layer away from the active layer.
[0039] The P-type stacked structure includes a P-type confinement layer, a second current adjustment layer, and a transition layer stacked sequentially. The P-type confinement layer is connected to the active layer, and the transition layer is connected to the P-type current extension layer.
[0040] Compared with the prior art, the beneficial effects of the technical solution provided in this application are as follows:
[0041] The N-type layer of the micro-LED chip provided in this application includes a first current adjustment layer. Two second predetermined regions of the first current adjustment layer near the etched sidewall of the epitaxial structure are non-conductive. The P-type stacked structure includes a second current adjustment layer. Two fourth predetermined regions of the second current adjustment layer near the etched sidewall of the epitaxial structure are non-conductive. That is, the regions of the first current adjustment layer near the sidewall of the epitaxial structure are non-conductive, and the regions of the second current adjustment layer near the sidewall of the epitaxial structure are also non-conductive. Therefore, the first current adjustment layer can adjust the direction of the current injected from the N-type metal electrode, blocking the current injected from the N-type metal electrode from flowing to the sidewall. Similarly, the second current adjustment layer can also adjust the direction of the current injected from the P-type metal electrode, blocking the current injected from the P-type metal electrode from flowing to the sidewall. This effectively suppresses the flow of charge carriers in the micro-LED chip to the sidewall, reduces the risk of non-radiative recombination caused by sidewall defects, and thus reduces the impact of sidewall defects on the luminous efficiency of the micro-LED chip under low current conditions, helping to improve the luminous efficiency of the micro-LED chip under low current conditions. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0043] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.
[0044] Figure 1 This is a schematic diagram of the structure of a micro LED chip provided in an embodiment of this application;
[0045] Figure 2 A schematic diagram of the current flow of a micro LED chip provided in an embodiment of this application;
[0046] Figure 3 This is a schematic diagram of the structure of the first current adjustment layer in a micro LED chip provided in an embodiment of this application;
[0047] Figure 4 This is a schematic diagram of the structure of the second current adjustment layer in a micro LED chip provided in an embodiment of this application;
[0048] Figure 5 This is a schematic diagram of the structure of the N-type layer and the P-type layer in a micro LED chip provided in an embodiment of this application;
[0049] Figure 6 This is a schematic diagram of another micro LED chip provided in an embodiment of this application;
[0050] Figure 7 This is a flowchart illustrating a method for fabricating a micro LED chip, as provided in an embodiment of this application. Detailed Implementation
[0051] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely one area of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0052] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0053] Typically, the fabrication of micro LED chips involves preparing multiple epitaxial structures on a large-size substrate, followed by etching and cutting to obtain independent epitaxial structures. However, this also leads to potential defects on the sidewalls of the epitaxial structures, and as the chip size gradually decreases, the defects caused by sidewall etching become increasingly prominent.
[0054] It should be noted that the luminous efficiency of a micro-LED chip under low-current conditions is also one of its important parameters. However, under low-current conditions, the slower carrier migration rate causes carriers to move towards the sidewalls, and non-radiative recombination occurs due to sidewall defects, leading to a decrease in the luminous efficiency of the micro-LED chip. Furthermore, as the chip size gradually decreases, defects become more prominent, and non-radiative recombination of carriers caused by sidewall defects becomes more severe, further resulting in lower luminous efficiency of the micro-LED chip under low-current conditions.
[0055] The inventors discovered that the main factors affecting the luminous efficiency of micro-LEDs are: first, internal quantum efficiency, which is the radiative recombination of electrons and holes in the active region; and second, light extraction efficiency, i.e., external quantum efficiency. Therefore, improving the luminous efficiency of micro-LEDs can be achieved by improving the epitaxial structure or enhancing its growth quality to increase the efficiency of radiative recombination of electrons and holes in the active region. Alternatively, it can be achieved by adding a DBR reflective layer to the epitaxial structure or by depositing a DBR reflective layer at the chip end to improve the external quantum efficiency.
[0056] Based on the above research, this application provides a micro LED chip, such as... Figure 1 As shown, the micro LED chip includes:
[0057] The epitaxial structure includes an N-type layer 10, an active layer 20, and a P-type layer 30 arranged sequentially from bottom to top. The P-type layer 30 includes a P-type stacked structure 31 and a P-type current spreading layer 32. The lower surface of the stacked structure 31 is in contact with the active layer 20, and the upper surface of the stacked structure 31 is in contact with the P-type current spreading layer 32, exposing a portion of the P-type current spreading layer 32. It should be noted that the epitaxial structure of the micro-LED described in this embodiment includes an N-type layer, an active layer, and a P-type layer to form the epitaxial structure of the micro-LED chip. This embodiment only describes the main components of the epitaxial structure, and other structures may be included in practice, depending on the specific circumstances.
[0058] N-type metal electrode 40, the N-type metal electrode 40 is located on the side of the N-type layer 10 away from the active layer 20, and is electrically connected to the N-type layer;
[0059] P-type metal electrode 50, the P-type metal electrode 50 is located on the side of the exposed portion of the P-type current spreading layer 32 facing the active layer 20, and is electrically connected to the P-type current spreading layer;
[0060] The N-type layer 10 includes a first current adjustment layer 11, and the P-type layer 30 includes a second current adjustment layer 33 located in the P-type stacked structure 31. The first current adjustment layer 11 includes a first preset region 111 and two second preset regions 112. The two second preset regions 112 are respectively located on both sides of the first preset region 111, that is, one of the two second preset regions 112 is located on one side of the first preset region 111, and the other second preset region 112 is located on the other side. Furthermore, the two second preset regions 112 are non-conductive, that is, they are located on both sides of the first current adjustment layer 11. The first preset region is non-conductive, while the middle region (first preset region) excluding the two side regions is conductive. The second current adjustment layer 33 includes a third preset region 331 and two fourth preset regions 332. The two fourth preset regions 332 are located on both sides of the third preset region 331, that is, one of the four fourth preset regions 332 is located on one side of the third preset region 331, and the other is located on the other side. Furthermore, the two fourth preset regions 332 are non-conductive. In other words, the two side regions of the second current adjustment layer 33 are non-conductive, while the middle region (third preset region) excluding the two side regions is conductive. It should be noted that the side regions of the first and second current adjustment layers are regions near the etched sidewalls of the epitaxial structure composed of an N-type layer, an active layer, and a P-type layer. The etched sidewalls are two opposing etched sidewalls formed during the etching process to form the epitaxial structure.
[0061] In this embodiment, the N-type layer includes a first current adjustment layer, the regions on both sides of the first current adjustment layer being non-conductive. The P-type stacked structure includes a second current adjustment layer, the regions on both sides of the second current adjustment layer being non-conductive. Specifically, the regions of the first current adjustment layer near the sidewalls of the epitaxial structure are non-conductive, and the regions of the second current adjustment layer near the sidewalls of the epitaxial structure are also non-conductive. Therefore, the first current adjustment layer can adjust the direction of the current injected from the N-type metal electrode, blocking the current injected from the N-type metal electrode from flowing to the sidewall. Similarly, the second current adjustment layer can also adjust the direction of the current injected from the P-type metal electrode, blocking the current injected from the P-type metal electrode from flowing to the sidewall. This effectively suppresses the flow of charge carriers in the micro-LED chip to the sidewall, reduces the risk of non-radiative recombination caused by sidewall defects, and thus reduces the impact of sidewall defects on the luminous efficiency of the micro-LED chip under low current conditions, helping to improve the luminous efficiency of the micro-LED chip under low current conditions.
[0062] Furthermore, since the two sides of the first current adjustment layer are non-conductive, except for the middle region of the two sides, and the two sides of the second current adjustment layer are non-conductive, except for the middle region of the two sides, the current injected from the N-type metal electrode will not flow to the sidewall, but will flow to the active layer through the middle region of the first current adjustment layer. Similarly, the current injected from the P-type metal electrode will not flow to the sidewall, but will flow to the active layer through the middle region of the second current adjustment layer. Thus, while the first and second current adjustment layers suppress the flow of charge carriers to the sidewall, they enable more charge carriers to flow to the active layer and perform radiative recombination luminescence in the active layer, thereby helping to improve the luminous efficiency of the micro LED chip.
[0063] Specifically, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the current flow of the micro LED chip provided in this application. The solid lines represent the direction of current injected into the N-type metal electrode 40, and the dashed lines represent the direction of current injected into the P-type metal electrode 50. Figure 2 As can be seen, due to the presence of the first current adjustment layer 11 and the second current adjustment layer 33, the current flowing from the N-type metal electrode 40 and the P-type metal electrode 50 passes through the first current adjustment layer 11 and the second current adjustment layer 33 respectively. Since the regions on both sides of the first current adjustment layer 11 and the second current adjustment layer 33 are not conductive, the current flow region is at a certain distance from the sidewall of the epitaxial structure after passing through the first current adjustment layer 11 and the second current adjustment layer 33. This suppresses the current from flowing towards the sidewall, that is, it suppresses the flow of charge carriers towards the sidewall, so that the charge carriers flow more towards the active layer.
[0064] Based on the above embodiments, in one embodiment of this application, such as Figure 3 As shown, the first current adjustment layer 11 includes a first sub-layer 113, a second sub-layer 114, and a third sub-layer 115 arranged sequentially from bottom to top. The first sub-layer 113 is located on the side away from the active layer, and the third sub-layer 115 is located on the side closer to the active layer. The portion of the first sub-layer 113 located in the first preset region 111 is A1. x Ga 1-x The second sub-layer 114, located in the first preset region 111, is an AlAs layer, and the third sub-layer 115, located in the first preset region 111, is an AlAs layer. y Ga 1-y As layer; the portions of the first sub-layer 113, the second sub-layer 114, and the third sub-layer 115 located in the second preset region 112 are Al2O3 layers. It should be noted that Al2O3 is non-conductive. x Ga 1-xAs and AlAs are conductive, so that the portions of the first sub-layer, the second sub-layer, and the third sub-layer located in the second preset region are non-conductive, while the portions located in the first preset region are conductive, thus making the second preset region of the first current adjustment layer non-conductive, thereby improving the luminous efficiency of the micro LED chip under low current conditions.
[0065] It should also be noted that Al2O3 can be obtained through wet oxidation of AlGaAs or AlAs. This allows for the preparation of the first and second current adjustment layers, where the initial films of the first, third, fourth, and sixth sub-layers are AlGaAs layers, and the initial films of the second and fifth sub-layers are AlAs layers. Wet oxidation of the initial films of each sub-layer results in Al2O3 in the lateral regions of each sub-layer, thus obtaining the first and second current adjustment layers. This method is relatively simple. Furthermore, the inward extension depth of the Al2O3 layer in the first and second current adjustment layers can be controlled by the oxidation time, making the operation simple.
[0066] Based on the above embodiments, in one embodiment of this application, the Al in the first sub-layer x Ga 1-x The content of Al component in the As layer is x, where 0.6 ≤ x < 1; the Al content in the third sublayer is... y Ga 1-y The Al content of the As layer is y, 0.6≤y<1; and the second sublayer is AlAs with an Al content of 1. Thus, the Al content of the first, second, and third sublayers located in the first preset region is relatively high, which results in a relatively high Al content in the portion of the first current adjustment layer located in the second preset region. Consequently, the band gap of the portion of the first current adjustment layer located in the second preset region is wider, which can effectively prevent the absorption of red and yellow light generated by the active layer by the portion of the first current adjustment layer located in the second preset region, allowing as much light generated by the active layer as possible to be emitted.
[0067] Furthermore, Al in the first sub-layer x Ga 1-x The content of Al component in the As layer is x, where 0.6 ≤ x < 1; the Al content in the third sublayer is... y Ga 1-yThe Al content of the As layer is y, where 0.6 ≤ y < 1; the second sublayer is AlAs with an Al content of 1, resulting in different Al content in each sublayer of the first initial current adjustment layer, with higher content in the middle and lower content at the edges. It is known that higher Al content makes it easier to oxidize. The higher Al content in the middle and lower content at the edges of the first initial current adjustment layer allows the outer layers to inhibit oxidation of the middle layer, thus better controlling the oxidation level. This results in a narrower Al2O3 layer closer to the sidewalls, preventing excessive oxidation that would lead to an overly wide Al2O3 layer, making the non-conductive region too large and the conductive region too small. Consequently, the light-emitting region in the active layer corresponding to the conductive region is smaller. Therefore, the first current adjustment layer can suppress carrier flow towards the sidewalls while maintaining the size of the light-emitting region in the active layer, improving the performance of the micro-LED chip.
[0068] Furthermore, the thickness of the first sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values; the thickness of the second sublayer ranges from 30 angstroms to 150 angstroms, including the endpoint values; and the thickness of the third sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values. However, this application does not impose any limitations on this, and the specific thickness depends on the circumstances.
[0069] Based on the above embodiments, in one embodiment of this application, such as Figure 4 As shown, the second current adjustment layer 33 includes a fourth sub-layer 333, a fifth sub-layer 334, and a sixth sub-layer 335 stacked sequentially from bottom to top; wherein, the portion of the fourth sub-layer 333 located in the third preset region 331 is A1. m Ga 1-m As layer, the portion of the fifth sub-layer 334 located in the third preset region 331 is an AlAs layer, and the portion of the sixth sub-layer 335 located in the third preset region 331 is an Al layer. n Ga 1-n The As layer; the portions of the fourth sub-layer 333, the fifth sub-layer 334, and the sixth sub-layer 335 located in the fourth preset region 332 are Al2O3 layers, which improve the luminous efficiency of the micro LED chip under low current conditions and make it easier to obtain the second current adjustment layer. It should be noted that the working principle of the second current adjustment layer is the same as that of the first current adjustment layer, and will not be repeated here.
[0070] Based on the above embodiments, in one embodiment of this application, the Al in the fourth sub-layer m Ga 1-m The content of Al component in the As layer is m, where 0.6 ≤ m < 1; the Al content in the sixth sublayern Ga 1-n The Al content of the As layer is n, where 0.6 ≤ n < 1; and the fifth sub-layer is AlAs with an Al content of 1. This results in a higher Al content in the portion of the second current adjustment layer located in the third preset region, which can effectively prevent the absorption of red and yellow light generated by the active layer in the portion of the second current adjustment layer located in the third preset region. This allows as much light generated by the active layer as possible to be emitted, while also ensuring the size of the light-emitting area in the active layer and improving the working performance of the micro LED chip.
[0071] Furthermore, the thickness of the fourth sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values; the thickness of the fifth sublayer ranges from 30 angstroms to 150 angstroms, including the endpoint values; and the thickness of the sixth sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values. However, this application does not impose any limitations on this, and the specific thickness depends on the circumstances.
[0072] Based on the above embodiments, in one embodiment of this application, such as Figure 5 As shown, the N-type layer 10 includes an N-type ohmic contact layer 12, an N-type current spreading layer 13, a first current adjusting layer 11, and an N-type confinement layer 14 stacked sequentially from bottom to top; wherein, the N-type confinement layer 14 is connected to the active layer 20, and the N-type metal electrode 40 is located on the side of the N-type ohmic contact layer 12 away from the active layer 20; the P-type stacked structure 31 includes a P-type confinement layer 311, a second current adjusting layer 33, and a transition layer 312 stacked sequentially from bottom to top; wherein, the P-type confinement layer 311 is connected to the active layer 20, and the transition layer 312 is connected to the P-type current spreading layer 32, thereby forming the epitaxial structure of the micro LED chip.
[0073] Based on the above embodiments, in this embodiment, to ensure that each film layer in the N-type layer is an N-type doped layer, the doping element of the N-type ohmic contact layer is Si or Te, with a doping concentration of 1E18 to 5E18, including the endpoint values; the doping element of the N-type current spreading layer is Si or Te, with a doping concentration of 1E18 to 5E18, including the endpoint values; the doping element of the first current adjustment layer is Si or Te, with a doping concentration of 1E18 to 3E18, including the endpoint values; and the doping element of the N-type confinement layer is Si or Te, with a doping concentration of 0.8E18 to 3E18, including the endpoint values.
[0074] Furthermore, to ensure that each film layer in the P-type layer is a P-type doped layer, the doping element of the P-type confinement layer is Mg or Zn, with a doping concentration of 0.5E18 to 2E18, including the endpoint values; the doping element of the second current adjustment layer is Mg, Zn, or C, with a doping concentration of 1E18 to 3E18, including the endpoint values; the doping element of the transition layer is Mg or Zn, with a doping concentration of 3E18 to 5E18, including the endpoint values; and the doping element of the P-type current extension layer is Mg, Zn, or C, with a doping concentration of 1E18 to 3E18, including the endpoint values.
[0075] It should be noted that this application does not limit the doping elements and doping concentrations of the above-mentioned films; the specific requirements will depend on the circumstances.
[0076] Based on any of the above embodiments, in one embodiment of this application, such as Figure 6 As shown, the micro-LED also includes an insulating protective layer 60, which covers the portion of the micro-LED chip surface described in any of the above embodiments, excluding the surfaces of the N-type metal electrode 40 and the P-type metal electrode 50, thus protecting the micro-LED chip. Continuing as... Figure 6 As shown, the micro LED chip also includes an external connector 70 for an N-type metal electrode and an external connector 80 for a P-type metal electrode, so as to transmit signals to the N-type metal electrode and the P-type metal electrode when the micro LED is working.
[0077] Based on the above embodiments, in one embodiment of this application, such as Figure 6 As shown, the micro LED chip also includes a sapphire substrate 90 located on the side of the P-type current spreading layer away from the active layer, providing support for the micro LED; it also includes a SiO2 insulating spacer layer 100 located on the side of the sapphire substrate 90 facing the P-type current spreading layer 32, and a SiO2 insulating spacer layer 200 located on the side of the P-type current spreading layer 32 facing the substrate 90. The two SiO2 insulating spacer layers are bonded together to insulate and isolate the sapphire substrate 90 from the P-type current spreading layer 32, and to fix the sapphire substrate 90 and the P-type current spreading layer 32 to each other.
[0078] The sapphire substrate is a light-transmitting substrate and does not affect the emission of light from the active layer. However, this application does not limit this, and the substrate may also be a light-transmitting substrate other than sapphire.
[0079] The surface of the P-type current spreading layer facing away from the active layer is roughened, which increases the exit angle of the light emitted by the active layer after passing through this surface, thereby making the illumination range of the micro LED chip wider. In addition, it also makes the P-type current spreading layer bond firmly to the SiO2 insulating spacer layer on its surface.
[0080] Accordingly, this application also provides a method for fabricating a micro LED chip, which is used to fabricate the micro LED chip described in any of the above embodiments, such as... Figure 7 As shown, the preparation method includes:
[0081] S1: Form an N-type layer, an active layer, and a P-type layer stacked sequentially, wherein the P-type layer includes a stacked structure and a P-type current extension layer, the lower surface of the stacked structure is in contact with the active layer, the upper surface is in contact with the P-type current extension layer, and a portion of the P-type current extension layer is exposed.
[0082] S2: Form an N-type metal electrode, wherein the N-type metal electrode is located on the side of the N-type layer away from the active layer;
[0083] S3: Form a P-type metal electrode, wherein the P-type metal electrode is located on the side of the exposed portion of the P-type current extension layer facing the active layer;
[0084] The N-type layer includes a first current adjustment layer, and the P-type layer includes a second current adjustment layer located in the P-type stacked structure. The first current adjustment layer includes a first preset region and two second preset regions, which are located on both sides of the first preset region and are non-conductive. The second current adjustment layer includes a third preset region and two fourth preset regions, which are located on both sides of the third preset region and are non-conductive.
[0085] Specifically, in this embodiment, the regions on both sides of the first current adjustment layer are non-conductive, and the regions on both sides of the second current adjustment layer are non-conductive. That is, the region of the first current adjustment layer near the sidewall of the epitaxial structure is non-conductive, and the region of the second current adjustment layer near the sidewall of the epitaxial structure is non-conductive. Therefore, the first current adjustment layer can adjust the direction of the current injected from the N-type metal electrode, blocking the current injected from the N-type metal electrode from flowing to the sidewall. Similarly, the second current adjustment layer can also adjust the direction of the current injected from the P-type metal electrode, blocking the current injected from the P-type metal electrode from flowing to the sidewall. This effectively suppresses the flow of charge carriers to the sidewall, reduces the risk of non-radiative recombination caused by sidewall defects, and thus reduces the impact of sidewall defects on the luminous efficiency of the micro LED chip under low current conditions, which helps to improve the luminous efficiency of the micro LED chip under low current conditions.
[0086] Furthermore, since the two sides of the first current adjustment layer are non-conductive, except for the middle area of the two sides, the two sides of the second current adjustment layer are non-conductive, except for the middle area of the two sides. The current injected from the N-type metal electrode will not flow to the sidewall, but will flow to the active layer through the middle area of the first current adjustment layer. Similarly, the current injected from the P-type metal electrode will not flow to the sidewall, but will flow to the active layer through the middle area of the second current adjustment layer. Thus, while the first and second current adjustment layers suppress the flow of charge carriers to the sidewall, they also enable more charge carriers to flow to the active layer and perform radiative recombination luminescence in the active layer, thereby helping to improve the luminous efficiency of the micro LED chip.
[0087] Based on the above embodiments, in one embodiment of this application, such as Figure 7 As shown, step S1, forming the sequentially stacked N-type layer, active layer, and P-type layer, includes:
[0088] S11: Provide a substrate; the substrate is a GaAs flip-chip 15° substrate, but this application does not limit it and it depends on the specific circumstances;
[0089] S12: An etching structure is formed on the surface of the substrate, the etching structure comprising, in sequence: a buffer layer, an etching stop layer, an N-type ohmic contact layer, an N-type current spreading layer, a first initial current adjustment layer, an N-type confinement layer, an active layer, a P-type confinement layer, a second initial current adjustment layer, a transition layer, and a P-type current spreading layer.
[0090] S13: Remove the substrate, the buffer layer, and the etching stop layer;
[0091] S14: Etch the etched structure along the N-type ohmic contact layer to expose a portion of the P-type current spreading layer;
[0092] S15: Then, wet oxidation is performed on the first initial current adjustment layer and the second initial current adjustment layer to form the first current adjustment layer and the second current adjustment layer respectively, forming an N-type layer, an active layer and a P-type layer stacked in sequence.
[0093] The N-type layer includes an N-type ohmic contact layer, an N-type current spreading layer, a first current adjusting layer, and an N-type confinement layer stacked sequentially. The N-type confinement layer is connected to the active layer, and the N-type metal electrode is located on the side of the N-type ohmic contact layer away from the active layer.
[0094] The P-type stacked structure includes a P-type confinement layer, a second current adjustment layer, a transition layer, and a P-type current extension layer stacked sequentially. The P-type confinement layer is connected to the active layer, and the transition layer is connected to the P-type current extension layer.
[0095] The specific process for forming the sequentially stacked N-type layer, active layer, and P-type layer is as follows: A GaAs substrate is placed in a reaction chamber, and after heating, a GaAs buffer layer is grown. Then, a GaInP-N type etch stop layer is grown on the GaAs buffer layer. A GaAs-N type ohmic contact layer is grown on the GaInP-N type etch stop layer. An AlGaInP-N type current spreading layer is grown on the GaAs-N type ohmic contact layer. A first initial current adjustment layer is grown on the AlGaInP-N type current spreading layer. An AlInP-N type confinement layer is grown on the first initial current adjustment layer. An active layer is grown on the AlInP-N type confinement layer. An AlInP-P type confinement layer is grown on the active layer. A second initial current adjustment layer is grown on the AlInP-P type confinement layer. A transition layer with a thickness of 20 nm to 50 nm is grown on the second initial current adjustment layer. Finally, a GaP-P type current spreading layer is grown on the transition layer to form the etched structure. After forming the etched structure, the GaAs substrate, GaAs buffer layer, and GaInP-N etching stop layer are removed, exposing the GaAs-N type ohmic contact layer. An N-type metal electrode is formed on the side of the exposed GaAs-N type ohmic contact layer away from the active layer. Then, the etched structure is etched along the GaAs-N type ohmic contact layer down to the surface of the GaP-P type current spreading layer, exposing a portion of the GaP-P type current spreading layer. This etched structure is formed into a stepped structure, with the mesa being the GaAs-N type ohmic contact layer and the GaP-P type current spreading layer, which are not on the same plane. A P-type metal electrode is formed on the surface of the exposed GaP-P type current spreading layer facing the active layer. Then, the first initial current adjustment layer and the second initial current adjustment layer are wet-oxidized from the sidewalls of the formed stepped structure, forming Al2O3 in the regions near the sidewalls of the first and second initial current adjustment layers, thus completing the fabrication of the epitaxial structure.
[0096] It should be noted that the doping element of the etching stop layer is Si or Te, and the doping concentration is 1E18 to 5E18, including the endpoint value, but this application does not limit this; it depends on the specific circumstances. It should also be noted that this application does not limit the material of each film layer in the above-mentioned etched structure; it can be determined according to the specific circumstances.
[0097] Based on the above embodiments, in one embodiment of this application, the preparation method further includes:
[0098] S4: Roughen the surface of the P-type current spread layer away from the active layer so that the surface of the P-type current spread layer away from the active layer is a roughened surface.
[0099] S5: A SiO2 insulating spacer layer is formed on the roughened surface of the P-type current spreading layer, and a SiO2 insulating spacer layer is formed on the side of the sapphire substrate facing the P-type current spreading layer. The two SiO2 insulating spacer layers are bonded together, thereby fixing the P-type current spreading layer and the sapphire substrate to each other and insulating them. It should be noted that the surface of the P-type current spreading layer away from the active layer is a roughened surface, which makes the exit angle of the light emitted by the active layer larger after passing through this surface, thereby making the illumination range of the micro LED chip wider. In addition, it also makes the P-type current spreading layer bond firmly to the SiO2 insulating layer on its surface.
[0100] S6: Form an insulating protective layer that covers the portion of the surface of the micro LED chip prepared by the preparation method described in any of the above embodiments, excluding the surfaces of the N-type metal electrode 40 and the P-type metal electrode 50, thereby protecting the micro LED chip.
[0101] It should be noted that the structure and working principle of the micro LED chip prepared by this method have been described in detail in the relevant content on micro LED chips mentioned above, and will not be repeated here.
[0102] In summary, this application provides a micro LED chip and its fabrication method. The micro LED includes an N-type layer, an active layer, and a P-type layer. The N-type layer includes a first current adjustment layer, the regions on both sides of which are non-conductive. The P-type stacked structure includes a second current adjustment layer, the regions on both sides of which are non-conductive. Specifically, the regions of the first current adjustment layer near the sidewalls of the epitaxial structure are non-conductive, and the regions of the second current adjustment layer near the sidewalls of the epitaxial structure are also non-conductive. Therefore, the first current adjustment layer can adjust the direction of the current injected from the N-type metal electrode, blocking the current injected from the N-type metal electrode from flowing to the sidewalls. Similarly, the second current adjustment layer can also adjust the direction of the current injected from the P-type metal electrode, blocking the current injected from the P-type metal electrode from flowing to the sidewalls. This effectively suppresses carrier flow to the sidewalls, reduces the risk of non-radiative recombination caused by sidewall defects, and thus reduces the impact of sidewall defects on the luminous efficiency of the micro LED chip under low current conditions, helping to improve the luminous efficiency of the micro LED chip under low current conditions.
[0103] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical areas between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant details can be found in the description of the method area.
[0104] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.
[0105] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.
[0106] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A micro LED chip, characterized in that, include: The N-type layer, active layer, and P-type layer are arranged sequentially from bottom to top. The P-type layer includes a P-type stacked structure and a P-type current spreading layer. The lower surface of the P-type stacked structure is connected to the active layer, and the upper surface is connected to the P-type current spreading layer, exposing part of the P-type current spreading layer. An N-type metal electrode is located on the side of the N-type layer away from the active layer; a P-type metal electrode is located on the exposed portion of the P-type current extension layer facing the active layer. The N-type layer includes a first current adjustment layer, and the P-type layer includes a second current adjustment layer located in the P-type stacked structure. The first current adjustment layer includes a first preset region and two second preset regions, which are located on both sides of the first preset region and are non-conductive. The second current adjustment layer includes a third preset region and two fourth preset regions, which are located on both sides of the third preset region and are non-conductive. The first current adjustment layer includes a first sub-layer, a second sub-layer, and a third sub-layer stacked sequentially from bottom to top; the portion of the first sub-layer located in the first preset region is Al. x Ga 1-x As layer, 0.6≤x<1, the portion of the second sub-layer located in the first preset region is the AlAs layer, and the portion of the third sub-layer located in the first preset region is the Al layer. y Ga 1-y As layer, 0.6≤y<1; the portions of the first sub-layer, the second sub-layer, and the third sub-layer located in the two second preset regions are Al2O3 layers; The second current adjustment layer includes a fourth sub-layer, a fifth sub-layer, and a sixth sub-layer stacked sequentially from bottom to top; the portion of the fourth sub-layer located in the third preset region is Al. m Ga 1-m As layer, 0.6≤m<1, the portion of the fifth sub-layer located in the third preset region is an AlAs layer, and the portion of the sixth sub-layer located in the third preset region is an Al layer. n Ga 1-n As layer, 0.6≤n<1; the portions of the fourth, fifth and sixth sub-layers located in the two fourth preset regions are Al2O3 layers.
2. The micro LED chip according to claim 1, characterized in that, The thickness of the first sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values; the thickness of the second sublayer ranges from 30 angstroms to 150 angstroms, including the endpoint values; and the thickness of the third sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values.
3. The micro LED chip according to claim 1, characterized in that, The thickness of the fourth sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values; the thickness of the fifth sublayer ranges from 30 angstroms to 150 angstroms, including the endpoint values; and the thickness of the sixth sublayer ranges from 30 angstroms to 100 angstroms, including the endpoint values.
4. The micro LED chip according to claim 1, characterized in that, The N-type layer includes, from bottom to top, an N-type ohmic contact layer, an N-type current spreading layer, a first current adjusting layer, and an N-type confinement layer; wherein, the N-type confinement layer is connected to the active layer, and the N-type metal electrode is located on the side of the N-type ohmic contact layer away from the active layer; The P-type stacked structure includes a P-type confinement layer, a second current adjustment layer, and a transition layer stacked sequentially from bottom to top; wherein the P-type confinement layer is connected to the active layer, and the transition layer is connected to the P-type current extension layer.
5. The micro LED chip according to claim 4, characterized in that, The doping element of the N-type ohmic contact layer is Si or Te, and the doping concentration is 1E18~5E18, including the endpoint value. The doping element of the N-type current spreading layer is Si or Te, and the doping concentration is 1E18~5E18, including the endpoint values. The doping element of the first current adjustment layer is Si or Te, and the doping concentration is 1E18~3E18, including the endpoint values. The doping element of the N-type confinement layer is Si or Te, and the doping concentration is 0.8E18~3E18, including the endpoint values; The doping element of the P-type confinement layer is Mg or Zn, and the doping concentration is 0.5E18~2E18, including the endpoint values; The doping element of the second current adjustment layer is Mg, Zn or C, and the doping concentration is 1E18~3E18, including the endpoint value; The doping element of the transition layer is Mg or Zn, and the doping concentration is 3E18~5E18, including the endpoint values. The doping element of the P-type current spreading layer is Mg, Zn, or C, and the doping concentration is 1E18~3E18, including the endpoint values.
6. A method for fabricating a micro LED chip, characterized in that, For preparing the micro LED chip according to any one of claims 1-5, comprising: An N-type layer, an active layer, and a P-type layer are formed in sequence. The P-type layer includes a stacked structure and a P-type current spreading layer. The lower surface of the P-type stacked structure is in contact with the active layer, and the upper surface is in contact with the P-type current spreading layer, exposing part of the P-type current spreading layer. An N-type metal electrode is formed, located on the side of the N-type layer away from the active layer; a P-type metal electrode is formed, located on the exposed portion of the P-type current extension layer facing the active layer. The N-type layer includes a first current adjustment layer, and the P-type layer includes a second current adjustment layer located in the P-type stacked structure. The first current adjustment layer includes a first preset region and two second preset regions, which are located on both sides of the first preset region and are non-conductive. The second current adjustment layer includes a third preset region and two fourth preset regions, which are located on both sides of the third preset region and are non-conductive. The first current adjustment layer includes a first sub-layer, a second sub-layer, and a third sub-layer stacked sequentially from bottom to top; the portion of the first sub-layer located in the first preset region is Al. x Ga 1-x As layer, 0.6≤x<1, the portion of the second sub-layer located in the first preset region is the AlAs layer, and the portion of the third sub-layer located in the first preset region is the Al layer. y Ga 1-y As layer, 0.6≤y<1; the portions of the first sub-layer, the second sub-layer, and the third sub-layer located in the two second preset regions are Al2O3 layers; The second current adjustment layer includes a fourth sub-layer, a fifth sub-layer, and a sixth sub-layer stacked sequentially from bottom to top; the portion of the fourth sub-layer located in the third preset region is Al. m Ga 1-m As layer, 0.6≤m<1, the portion of the fifth sub-layer located in the third preset region is an AlAs layer, and the portion of the sixth sub-layer located in the third preset region is an Al layer. n Ga 1-n As layer, 0.6≤n<1; the portions of the fourth, fifth and sixth sub-layers located in the two fourth preset regions are Al2O3 layers.
7. The preparation method according to claim 6, characterized in that, The formation of the N-type layer, active layer, and P-type layer stacked sequentially includes: Provide a substrate; An etching structure is formed on the surface of the substrate, the etching structure comprising, in sequence: a buffer layer, an etching stop layer, an N-type ohmic contact layer, an N-type current spreading layer, a first initial current adjustment layer, an N-type confinement layer, an active layer, a P-type confinement layer, a second initial current adjustment layer, a transition layer, and a P-type current spreading layer. Remove the substrate, the buffer layer, and the corrosion stop layer; The etched structure is etched along the N-type ohmic contact layer to expose a portion of the P-type current spreading layer; Subsequently, the first initial current adjustment layer and the second initial current adjustment layer are subjected to wet oxidation to form the first current adjustment layer and the second current adjustment layer, respectively, forming an N-type layer, an active layer and a P-type layer stacked sequentially. The N-type layer includes an N-type ohmic contact layer, an N-type current spreading layer, a first current adjusting layer, and an N-type confinement layer stacked sequentially. The N-type confinement layer is connected to the active layer, and the N-type metal electrode is located on the side of the N-type ohmic contact layer away from the active layer. The P-type stacked structure includes a P-type confinement layer, a second current adjustment layer, and a transition layer stacked sequentially. The P-type confinement layer is connected to the active layer, and the transition layer is connected to the P-type current extension layer.