High-speed high-precision analog-to-digital converter and performance improvement method of analog-to-digital converter

Abstract

The application provides a high-speed high-precision analog-digital converter and a performance improvement method of the analog-digital converter, the analog-digital converter comprises an input configuration module, an analog-digital conversion module, an adaptive parameter extraction module and a whole cycle data recovery module, in a parameter extraction working mode, the modified parameters are extracted through the cooperation among the input configuration module, the analog-digital conversion module, the adaptive parameter extraction module and the whole cycle data recovery module; in a normal working mode, the digital calibration and correction of the digital signal are realized through the analog-digital conversion module and the modified parameters, the modified parameters comprise a jitter correction parameter, a gain correction parameter and a mismatch error correction parameter, the signal-to-noise ratio and the linearity of the analog-digital converter are improved, the influence of the performance of the analog-digital converter caused by the smaller and smaller intrinsic gain and the larger and larger mismatch error with the reduction of the process size is avoided, the injected random jitter is completely eliminated, and the influence of the signal-to-noise ratio of the analog-digital converter caused by the injected random jitter is avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-speed, high-precision analog-to-digital converter and a method for improving the performance of the analog-to-digital converter. Background Technology

[0002] An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. Its speed and accuracy determine the quality of signal acquisition and conversion. With the development of information technology, the requirements for signal acquisition and conversion are becoming increasingly stringent, making high-speed, high-precision ADCs a key requirement for complete systems. While advancements in manufacturing processes have led to increased speeds, they have also resulted in decreased signal-to-noise ratios and linearity, exhibiting the following shortcomings:

[0003] (1) As the process size shrinks, the device size becomes smaller and smaller, and the mismatch error of the device becomes larger and larger, which leads to a decrease in the signal-to-noise ratio and linearity of the analog-to-digital converter.

[0004] (2) As the process size shrinks, the intrinsic gain of the device becomes smaller and smaller, and the gain of the operational amplifier is difficult to meet the accuracy requirements of the analog-to-digital converter. This further leads to a decrease in the signal-to-noise ratio and linearity of the analog-to-digital converter.

[0005] (3) The traditional method of injecting random jitter signals can improve the conversion linearity of analog-to-digital converters. However, due to the influence of device process deviations, the injected random jitter often cannot be completely eliminated, which leads to a decrease in the signal-to-noise ratio of analog-to-digital converters while improving linearity.

[0006] Therefore, there is an urgent need for a high-speed, high-precision analog-to-digital converter (ADC) solution to address the issues of reduced signal-to-noise ratio (SNR) and linearity caused by process deviations and insufficient intrinsic gain of devices, as well as the SNR reduction caused by jitter injection. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-speed and high-precision analog-to-digital converter (ADC) solution to solve the problems of reduced signal-to-noise ratio and linearity caused by process deviations and insufficient intrinsic gain of devices, as well as the problem of reduced signal-to-noise ratio caused by jitter injection.

[0008] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0009] A high-speed, high-precision analog-to-digital converter includes an input configuration module, an analog-to-digital conversion module, an adaptive parameter extraction module, and an integer-cycle data recovery module.

[0010] The adaptive parameter extraction module sends a configuration control signal to the input configuration module. Under the control of the configuration control signal, the input configuration module configures and generates analog signals, quantization control signals, and output mode control signals.

[0011] The analog-to-digital conversion module receives the analog signal, the quantization control signal, and the output mode control signal, performs analog-to-digital conversion on the analog signal to obtain a digital signal, and under the control of the quantization control signal and the output mode control signal, when the high-speed high-precision analog-to-digital converter is in the parameter extraction working mode, rearranges the digital signal to obtain a rearranged digital signal, and when the high-speed high-precision analog-to-digital converter is in the normal working mode, calibrates the digital signal according to the correction parameters to obtain a corrected digital signal;

[0012] The adaptive parameter extraction module sends output data mode information to the full-cycle data recovery module. The full-cycle data recovery module receives the output data mode information and the rearranged digital signal, and recovers the rearranged digital signal into full-cycle data according to the output data mode information, thereby obtaining and outputting the full-cycle rearranged digital signal.

[0013] The adaptive parameter extraction module receives the integer-cycle corrected digital signal, extracts the correction parameters from the integer-cycle rearranged digital signal using an adaptive parameter extraction method, and then sends the correction parameters to the parameter memory inside the analog-to-digital converter for storage.

[0014] The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters.

[0015] Optionally, the analog-to-digital conversion module includes a first operational circuit, n cascaded quantization circuits, n random number generation circuits, and n analog random signal generation circuits. The n random number generation circuits are connected one-to-one with the n analog random signal generation circuits. Each random number generation circuit generates a random digital signal, and the analog random signal generation circuit performs digital-to-analog conversion on the random digital signal to obtain a random analog signal. The first input terminal of the first operational circuit is connected to the analog signal, the second input terminal of the first operational circuit is connected to the first random analog signal, and the output terminal of the first operational circuit is connected to the analog input terminal of the first-stage quantization circuit. The first operational circuit performs addition on the analog signal and the first random analog signal. The feedback adjustment input of the first-stage quantization circuit... The first stage quantization circuit connects to the second random analog signal, the control input of the first stage quantization circuit connects to the first quantization control signal, the analog output of the first stage quantization circuit connects to the analog input of the second stage quantization circuit, and the digital output of the first stage quantization circuit outputs the first stage digital signal; the feedback adjustment input of the i-th stage quantization circuit connects to the (i+1)-th random analog signal, the control input of the i-th stage quantization circuit connects to the i-th quantization control signal, the analog output of the i-th stage quantization circuit connects to the analog input of the (i+1)-th stage quantization circuit, and the digital output of the i-th stage quantization circuit outputs the i-th stage digital signal; the digital output of the n-th stage quantization circuit outputs the n-th stage digital signal; where n is an integer greater than or equal to 2, and i is an integer from 2 to n-1.

[0016] Optionally, the j-th stage quantization circuit includes a sub-analog-to-digital converter (ADC) and a multiplicative digital-to-analog converter (DAC). The analog input terminal of the sub-ADC serves as the analog input terminal of the j-th stage quantization circuit. The sub-ADC receives the analog input signal and performs analog-to-digital conversion on the analog input signal to obtain a digital output signal. The digital output terminal of the sub-ADC serves as the digital output terminal of the j-th stage quantization circuit. The multiplicative DAC includes a sub-ADC, a second operational circuit, and an amplifier. The sub-ADC receives the digital output signal and performs digital-to-analog conversion on the digital output signal to obtain an analog output signal. The second operational circuit... The first input terminal of the second operational circuit is connected to the analog input terminal of the sub-analog-to-digital converter; the second input terminal of the second operational circuit is connected to the analog output signal; the third input terminal of the second operational circuit serves as the feedback adjustment input terminal of the j-th stage quantization circuit; the third input terminal of the second operational circuit is connected to the random analog signal; the output terminal of the second operational circuit is connected to the input terminal of the amplifier; the second operational circuit performs an operation by subtracting the analog output signal from the analog input signal and adding the random analog signal; the output terminal of the amplifier serves as the analog output terminal of the j-th stage quantization circuit; where j is an integer from 1 to n-1.

[0017] Optionally, the quantization circuit of the nth stage includes a sub-analog-to-digital converter (ADC), the analog input terminal of the sub-ADC serves as the analog input terminal of the quantization circuit of the nth stage, the sub-ADC receives the analog input signal and performs analog-to-digital conversion on the analog input signal to obtain a digital output signal, and the digital output terminal of the sub-ADC serves as the digital output terminal of the quantization circuit of the nth stage.

[0018] Optionally, the analog-to-digital conversion module further includes a data alignment unit, which receives n random digital signals and n levels of digital signals, and performs alignment processing on the random digital signals and digital signals of each level of the quantization circuit.

[0019] Optionally, the analog-to-digital converter module further includes a data rearrangement unit. The data rearrangement unit is connected to the output mode control signal and the aligned n random digital signals and n-level digital signals. Under the control of the output mode control signal, when the high-speed, high-precision analog-to-digital converter is in the parameter extraction working mode, the n random digital signals and n-level digital signals after one sampling and alignment are rearranged to obtain the rearranged digital signal, and the rearranged digital signal is output multiple times.

[0020] Optionally, the analog-to-digital converter module further includes a digital calibration unit, which is connected to the data alignment unit and the parameter memory respectively. When the high-speed, high-precision analog-to-digital converter is in normal working mode, the digital calibration unit calibrates and corrects the n random digital signals and the n-level digital signals after one sampling and alignment according to the correction parameters stored in the parameter memory to obtain the corrected digital signal.

[0021] Optionally, the analog-to-digital converter module further includes an output interface unit, which is connected to the data rearrangement unit, the digital calibration unit, and the full-cycle data recovery module. When the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the output interface unit receives the rearranged digital signal and sends the rearranged digital signal to the full-cycle data recovery module multiple times. When the high-speed, high-precision analog-to-digital converter is in normal operation mode, the output interface unit receives the corrected digital signal and outputs the corrected digital signal.

[0022] Optionally, the parameter memory includes:

[0023] The software parameter storage unit is used to receive and store the correction parameters extracted by the adaptive parameter extraction module at one time, and send the correction parameters to the digital calibration unit for digital calibration.

[0024] The hardware repair parameter storage unit, when the correction parameters output by the software repair parameter storage unit are qualified, sends the correction parameters stored in the software repair parameter storage unit to the hardware repair parameter storage unit and solidifies them, storing them in the hardware repair parameter storage unit for a long time. When the system is powered off and then powered on again, the software repair parameter storage unit reads the correction parameters stored in the hardware repair parameter storage unit once and outputs them.

[0025] Optionally, the jitter correction parameter includes the actual weight of each of the random analog signals, the gain correction parameter includes the actual gain of each stage of the quantization circuit, and the mismatch error correction parameter includes the actual weight of the sub-digital-to-analog converter in each stage of the quantization circuit.

[0026] A method for improving the performance of an analog-to-digital converter includes the following steps:

[0027] An analog-to-digital converter is provided, incorporating a random number generation circuit and an analog random signal generation circuit. Multiple random analog signals are generated by the random number generation circuit and the analog random signal generation circuit, and jitter is injected into the analog-to-digital converter through the multiple random analog signals.

[0028] An input configuration module, a data rearrangement unit, an integer cycle data recovery module, and an adaptive parameter extraction module are added to the analog-to-digital converter. Through the cooperation of the input configuration module, the data rearrangement unit, the integer cycle data recovery module, and the adaptive parameter extraction module, the correction parameters of each quantization circuit in the analog-to-digital converter are extracted.

[0029] A parameter memory is added to the analog-to-digital converter to store the correction parameters. During the test extraction phase, the parameter memory stores the correction parameters once, and after the test is passed, the parameter memory permanently stores the correction parameters.

[0030] A digital calibration unit is added to the analog-to-digital converter. In the digital calibration unit, the digital signal obtained by analog-to-digital conversion of the analog-to-digital converter is calibrated and corrected according to the correction parameters stored in the parameter memory to obtain a corrected digital signal, thereby realizing digital calibration.

[0031] The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters.

[0032] Optionally, the step of extracting the correction parameters of each quantization circuit stage in the analog-to-digital converter through the cooperation of the input configuration module, the data rearrangement unit, the integer cycle data recovery module, and the adaptive parameter extraction module includes:

[0033] The adaptive parameter extraction module sends a configuration control signal to the input configuration module. Under the control of the configuration control signal, the input configuration module configures and generates analog signals, quantization control signals, and output mode control signals.

[0034] The analog-to-digital conversion module receives the analog signal, the quantization control signal, and the output mode control signal. Under the control of the quantization control signal, it performs analog-to-digital conversion on the analog signal to obtain a digital signal. Under the control of the output mode control signal, it rearranges the digital signal to obtain a rearranged digital signal. The rearranged digital signals are then sent to the full-cycle data recovery module through multiple outputs.

[0035] The adaptive parameter extraction module sends output data mode information to the full-cycle data recovery module. The full-cycle data recovery module receives the output data mode information and the rearranged digital signal, and recovers the rearranged digital signal into full-cycle data according to the output data mode information, thereby obtaining and outputting the full-cycle rearranged digital signal.

[0036] The adaptive parameter extraction module receives the integer-cycle corrected digital signal and extracts the correction parameters from the integer-cycle rearranged digital signal using an adaptive parameter extraction method.

[0037] As described above, the high-speed, high-precision analog-to-digital converter and the method for improving the performance of the analog-to-digital converter provided by the present invention have at least the following beneficial effects:

[0038] Based on the overall structural design of "input configuration module + analog-to-digital conversion module + adaptive parameter extraction module + full-cycle data recovery module", when the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the correction parameters can be extracted through the cooperation of the input configuration module, analog-to-digital conversion module, adaptive parameter extraction module, and full-cycle data recovery module. When the high-speed, high-precision analog-to-digital converter is in normal operation mode, the digital calibration and correction of the digital signal obtained after digital-to-analog conversion is achieved through the analog-to-digital conversion module and the correction parameters. The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters, which effectively improves the analog-to-digital conversion efficiency. The signal-to-noise ratio and linearity of the converter are improved, avoiding the impact of decreasing intrinsic gain and increasing mismatch error on the performance of the analog-to-digital converter as the process size shrinks. Injected random jitter is completely eliminated, preventing its impact on the signal-to-noise ratio. Simultaneously, the adaptive parameter extraction module uses an adaptive parameter extraction method to extract correction parameters, requiring fewer samples and significantly reducing the computational load. The calibration method is digital calibration, which, while addressing the decrease in signal-to-noise ratio and linearity of the analog-to-digital converter caused by process deviations and insufficient intrinsic gain of the devices, offers higher accuracy in error calibration compared to analog calibration methods. Attached Figure Description

[0039] Figure 1 The diagram shown is a structural block diagram of the high-speed, high-precision analog-to-digital converter in this invention.

[0040] Figure 2 The diagram shown is a circuit structure diagram of the first n-1 stages of quantization circuit in an optional embodiment of the present invention.

[0041] Figure 3 The diagram shown is a circuit structure diagram of the nth-level quantization circuit in an optional embodiment of the present invention.

[0042] Figure 4 The diagram shown is a structural block diagram of the parameter storage 8 in an optional embodiment of the present invention.

[0043] Figure 5 The diagram shows the steps of the method for improving the performance of an analog-to-digital converter in this invention. Detailed Implementation

[0044] As mentioned in the background section, the inventors have discovered that with the development of high-speed and high-precision analog-to-digital converters (ADCs), while advancements in manufacturing processes bring about speed improvements, they also lead to a decrease in the signal-to-noise ratio and linearity of the ADCs, resulting in at least the following shortcomings:

[0045] (1) As the process size shrinks, the device size becomes smaller and smaller, and the mismatch error of the device becomes larger and larger, which leads to a decrease in the signal-to-noise ratio and linearity of the analog-to-digital converter.

[0046] (2) As the process size shrinks, the intrinsic gain of the device becomes smaller and smaller, and the gain of the operational amplifier is difficult to meet the accuracy requirements of the analog-to-digital converter. This further leads to a decrease in the signal-to-noise ratio and linearity of the analog-to-digital converter.

[0047] (3) The traditional method of injecting random jitter signals can improve the conversion linearity of analog-to-digital converters. However, due to the influence of device process deviations, the injected random jitter often cannot be completely eliminated, which leads to a decrease in the signal-to-noise ratio of analog-to-digital converters while improving linearity.

[0048] Based on this, the present invention proposes a high-speed, high-precision analog-to-digital converter (ADC) technical solution: A jitter generation structure is added to the ADC to generate multiple random analog signals, injecting jitter into the ADC to improve its linearity; a correction parameter extraction structure is added to the ADC to extract correction parameters for each stage of the quantization circuit, including at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters; a parameter memory is added to the ADC, employing a combination of one-time storage and permanent storage to improve storage efficiency; and a digital calibration unit is added to the ADC to calibrate and correct the digital signal obtained from analog-to-digital conversion, in conjunction with the correction parameters, achieving digital calibration to avoid the impact on ADC performance caused by decreasing intrinsic gain and increasing mismatch error as process dimensions shrink, and to completely eliminate the injected random jitter.

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Please see Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0051] like Figure 1 As shown, the present invention provides a high-speed, high-precision analog-to-digital converter, which includes an input configuration module 11, an analog-to-digital conversion module 12, an adaptive parameter extraction module 13, and an integer-cycle data recovery module 14.

[0052] The adaptive parameter extraction module 13 sends a configuration control signal Cv to the input configuration module 11. Under the control of the configuration control signal Cv, the input configuration module 11 configures and generates analog signal Vin, quantization control signals Ctl1 to Ctl(n-1) and output mode control signal Ct1.

[0053] The analog-to-digital converter module 12 receives the analog signal Vin, quantization control signals Ctl1 to Ctl(n-1), and output mode control signal Ct1, and performs analog-to-digital conversion on the analog signal Vin to obtain digital signals D1 to D2. n Under the control of quantization control signals Ctl1~Ctl(n-1) and output mode control signal Ct1, when the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the digital signals D1~D2 are processed. n The digital signals are rearranged to obtain rearranged digital signals. When the high-speed, high-precision analog-to-digital converter is in normal working mode, the digital signals are calibrated according to the correction parameters to obtain corrected digital signals.

[0054] The adaptive parameter extraction module 13 sends the output data mode information to the full cycle data recovery module 14. The full cycle data recovery module 14 receives the output data mode information and the rearranged digital signal, and recovers the rearranged digital signal into full cycle data according to the output data mode information, and obtains and outputs the full cycle rearranged digital signal.

[0055] The adaptive parameter extraction module 13 receives the whole-cycle corrected digital signal and extracts the correction parameters from the whole-cycle rearranged digital signal using an adaptive parameter extraction method. The correction parameters are then sent to the parameter memory 8 inside the analog-to-digital converter 12 for storage.

[0056] The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters.

[0057] In detail, such as Figure 1 As shown, the analog-to-digital conversion module 12 includes a first operational circuit 01, n cascaded quantization circuits 21-2n, n random number generation circuits 30-3(n-1), and n analog random signal generation circuits 40-4(n-1). The n random number generation circuits 30-3(n-1) and the n analog random signal generation circuits 40-4(n-1) are connected in a one-to-one correspondence. The random number generation circuit 3k generates a random digital signal Dither. k Analog random signal generation circuit 4kbps for random digital signal Dithering k Perform digital-to-analog conversion to obtain a random analog signal. k The first input terminal of the first operational circuit 01 is connected to the analog signal Vin, the second input terminal of the first operational circuit 01 is connected to the first random analog signal dither0, and the output terminal of the first operational circuit 01 is connected to the analog input terminal of the first-stage quantization circuit 21. The first operational circuit 01 performs an addition operation on the analog signal Vin and the random analog signal dither0. The feedback adjustment input terminal of the first-stage quantization circuit 21 is connected to the second random analog signal dither1, the control input terminal of the first-stage quantization circuit 21 is connected to the first quantization control signal Ctl1, the analog output terminal of the first-stage quantization circuit 21 is connected to the analog input terminal of the second-stage quantization circuit 22, and the digital output terminal of the first-stage quantization circuit 21 outputs the first-stage digital signal D1. The feedback adjustment input terminal of the i-th stage quantization circuit 2i is connected to the (i+1)-th random analog signal dither0. i The control input terminal of the i-th quantization circuit 2i is connected to the i-th quantization control signal Ctli. The analog output terminal of the i-th quantization circuit 2i is connected to the analog input terminal of the (i+1)-th quantization circuit 2(i+1). The digital output terminal of the i-th quantization circuit 2i outputs the i-th digital signal D. i The digital output terminal of the nth-stage quantization circuit 2n outputs the nth-stage digital signal D. n Where n is an integer greater than or equal to 2, k is a natural number from 0 to n-1, and i is an integer from 2 to n-1.

[0058] More in detail, such as Figure 1As shown, n random number generation circuits 30 to 3(n-1) are connected one-to-one with n analog random signal generation circuits 40 to 4(n-1), that is, random number generation circuit 30 is connected to analog random signal generation circuit 40, random number generation circuit 31 is connected to analog random signal generation circuit 41, random number generation circuit 32 is connected to analog random signal generation circuit 42, ..., random number generation circuit 3(n-1) is connected to analog random signal generation circuit 4(n-1).

[0059] Among them, the k-th level random number generation circuit 3k is used to generate random integer digital signals Dither. k This signal can be selected to be generated or not generated according to system needs; the k-th stage analog random signal generation circuit 4k is used to generate the input random digital signal Dither. k Converted to the corresponding analog random signal dither k The output signal can be selected to be generated or not, depending on the system requirements.

[0060] More in detail, such as Figure 2 As shown, in an optional embodiment of the present invention, the j-th stage quantization circuit 2j includes a sub-analog-to-digital converter 201 and a multiplication digital-to-analog converter 202. The analog input terminal of the sub-analog-to-digital converter 201 serves as the analog input terminal of the j-th stage quantization circuit 2j, and the sub-analog-to-digital converter 201 is connected to the analog input signal V. inj And for the analog input signal V inj Perform analog-to-digital conversion to obtain the digital output signal D. j The digital output of the sub-analog-to-digital converter 201 serves as the digital output of the j-th stage quantization circuit; the multiplication digital-to-analog converter 202 includes a sub-analog-to-digital converter 2021, a second operational circuit 2022, and an amplifier 2023. The sub-analog-to-digital converter 2021 is connected to the digital output signal D. j And the digital output signal D j Perform digital-to-analog conversion to obtain the analog output signal V dacj The first input terminal of the second operational circuit 2022 is connected to the analog input terminal of the analog-to-digital converter 201, and the second input terminal of the second operational circuit 2022 is connected to the analog output signal V. dacj The third input terminal of the second operational circuit 2022 serves as the feedback adjustment input terminal of the j-th stage quantization circuit 2j, and the third input terminal of the second operational circuit 2022 is connected to the random analog signal dither. j The output of the second operational circuit 2022 is connected to the input of the amplifier 2023. The second operational circuit 2022 processes the analog input signal V. inj Subtract analog output signal V dacj In addition, the random analog signal dither jOperation; the output of amplifier 2023 serves as the analog output of the j-th stage quantization circuit 2j, and amplifier 2023 amplifies the output G of the second operational circuit 2022. j This yields the output V of the j-th quantization circuit 2j. Oj ; where j is an integer from 1 to n-1.

[0061] In this design, the sub-analog-to-digital converter 201 and the sub-digital-to-analog converter 2021 have the same number of bits, both having a kj-bit structure, and generate a digital output signal D. j For kj bits, D j1 …D j2kj The gain of amplifier 2023 is typically G. j =2 kj-1 It can also be adjusted under the control of Ctlj.

[0062] More in detail, such as Figure 3 As shown, in an optional embodiment of the present invention, the nth-stage quantization circuit 2n includes a sub-analog-to-digital converter 203, the analog input terminal of which serves as the analog input terminal of the nth-stage quantization circuit 2n, and the sub-analog-to-digital converter 203 is connected to the analog input signal V. inn And for the analog input signal V inn Perform analog-to-digital conversion to obtain the digital output signal D. n The digital output of the sub-analog-to-digital converter 203 serves as the digital output of the nth-stage quantization circuit 2n. No jitter signal is added to the nth-stage quantization circuit 2n.

[0063] The number of bits in the sub-analog-to-digital converter 203 can be set according to requirements and is not limited here. For example, if it is a kn-bit structure, the generated digital output signal D n For kn bits, D n1 …D n2kn .

[0064] It should be noted that when the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the correction parameter extraction for the m-th quantization circuit 2m is controlled and adjusted by the quantization control signals Ctl1 to Ctl(m-1) to increase the amplitude of the analog output signal of the (m-1)-th quantization circuit 2(m-1) by a factor of 2, so that the correction parameter extraction for the m-th quantization circuit 2m can cover all expected application ranges, where m is an integer from 2 to n; the correction parameter extraction for the 1st quantization circuit 21 is configured by the input configuration module 11 to set the required input signal amplitude, which will not be elaborated here.

[0065] In detail, such as Figure 1 As shown, the analog-to-digital conversion module 12 also includes a data alignment unit 5, which receives n random digital signals Dither0 to Dither0.(n-1) And n-level digital signals D1 to Dn, and perform alignment processing on the random digital signals and digital signals of each quantization circuit.

[0066] More in detail, such as Figure 1 As shown, the data alignment unit 5 is used to align the digital signals D at each stage corresponding to the same input signal. j and random digital signals Dither j Alignment, if the conversion time for each stage is t c Then the random digital signal Dither j The relative delay time between the random digital signal Dither1 and the random digital signal Dither1 is (j-1)×t c Digital signal D j The relative delay time between the digital signal D1 and the digital signal D1 is (j-1)×t c While ensuring the relative delay time, a fixed delay time can also be added as needed.

[0067] More in detail, such as Figure 1 As shown, the analog-to-digital conversion module 12 also includes a data rearrangement unit 6, which is connected to the output mode control signal Ct1 and the aligned n random digital signals Dither0 to Dither0. (n-1) and n-level digital signals D1~D n Under the control of the output mode control signal Ct1, when the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the n random digital signals Dither0 to Dither0 after one sampling and alignment are processed. (n-1) and n-level digital signals D1~D n The data is rearranged to obtain a rearranged digital signal, which is then output multiple times.

[0068] Among them, the data rearrangement unit 6 is only used in the parameter extraction working mode. Since the number of output data ports required in the normal working mode is less than the amount of data to be sent in the parameter extraction mode, in order to ensure the output data Dither required for parameter extraction, k and D k As needed, the data obtained from a single sampling needs to be rearranged and sent out multiple times from output interface unit 9. By combining data rearrangement with multiple outputs, all quantization intermediate parameters can be sent out as needed without changing the output interface, solving the problem that traditional analog-to-digital converters cannot send out all quantization intermediate parameters.

[0069] More in detail, such as Figure 1As shown, the analog-to-digital converter module 12 also includes a digital calibration unit 7, which is connected to the data alignment unit 6 and the parameter memory 8. When the high-speed, high-precision analog-to-digital converter is in normal working mode, the digital calibration unit 7, according to the correction parameters stored in the parameter memory 8, calibrates the n random digital signals Dither0 to Dither0 after one sampling and alignment. (n-1) and n-level digital signals D1~D n The calibration and correction are performed to obtain the corrected digital signal, which is then sent to the output interface unit 9.

[0070] More in detail, such as Figure 1 As shown, the analog-to-digital converter module 12 also includes an output interface unit 9. The output interface unit 9 is connected to the data rearrangement unit 6, the digital calibration unit 7, and the full-cycle data recovery module 14. When the high-speed, high-precision analog-to-digital converter is in the parameter extraction working mode, the output interface unit 9 receives the rearranged digital signal and sends the rearranged digital signal to the full-cycle data recovery module 14 in multiple parts. When the high-speed, high-precision analog-to-digital converter is in the normal working mode, the output interface unit 9 receives the corrected digital signal and outputs the corrected digital signal.

[0071] More in detail, such as Figure 4 As shown, in an optional embodiment of the present invention, the parameter memory 8 further includes:

[0072] The software parameter storage unit 81 is used to receive and store the correction parameters extracted by the adaptive parameter extraction module 13 at one time, and send the correction parameters to the digital calibration unit 7 for digital calibration.

[0073] When the correction parameters output by the soft repair parameter storage unit 81 are qualified, the correction parameters stored in the soft repair parameter storage unit 81 are sent to the hard repair parameter storage unit 82 and solidified, and stored in the hard repair parameter storage unit 82 for a long time. When the system is powered off and then powered on again, the soft repair parameter storage unit 81 reads the correction parameters stored in the hard repair parameter storage unit 82 once and outputs them.

[0074] Among them, the parameter memory 8 adopts a combination of one-time storage and fixed storage, which can flexibly realize one-time storage during the testing phase and fixed storage after the test is completed, effectively improving storage efficiency.

[0075] It should be noted that when the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the correction parameters of each quantization circuit are extracted step by step to obtain multiple correction parameters for each quantization circuit.

[0076] More specifically, the adaptive parameter extraction module 13 employs an adaptive parameter extraction method to extract correction parameters from the integer-cycle rearranged digital signal. These correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters. The jitter correction parameters include at least the values ​​of each random analog signal dither0 to dither0. (n-1) The actual weights and gain correction parameters should include at least the actual gain G of each quantization stage. 1_real ~G n-1_real The mismatch error correction parameters include at least the actual weights W of the sub-digital-to-analog converters in each stage of the quantization circuit. 1_real ~W n_real .

[0077] More specifically, when the high-speed, high-precision analog-to-digital converter (ADC) is in parameter extraction mode, a correction parameter extraction structure is formed by combining the input configuration module 11, the data rearrangement unit 6 in the ADC module 12, the output interface unit 9, the adaptive parameter extraction module 13, and the full-cycle data recovery module 14. Through this correction parameter extraction structure, correction parameters of each quantization circuit in the ADC module 12 are extracted. When the high-speed, high-precision ADC is in normal operating mode, a correction structure is formed by combining the digital calibration unit 7 and the parameter memory 8 in the ADC module 12. Through this correction structure, the digital signal obtained by the ADC from analog-to-digital conversion is calibrated and corrected to achieve digital calibration. At the same time, each quantization circuit in the ADC module 12 can selectively add or not add jitter signals, which can selectively improve the linearity of the ADC module 12.

[0078] Among them, the adaptive parameter extraction module 13 adopts an adaptive parameter extraction method, which requires fewer samples and can greatly reduce the computational load of parameter extraction; by combining intermediate parameter output with the adaptive parameter extraction method, it realizes multi-level and multi-correction parameter extraction of the analog-to-digital converter, solving the problem that traditional analog-to-digital converters cannot extract multi-level and multi-correction parameters; by injecting jitter to improve the linearity of the analog-to-digital converter, and the extracted correction parameters include jitter correction parameters, combined with the jitter correction in the digital calibration unit 7, the injected jitter can be accurately eliminated, thereby avoiding the decrease in system signal-to-noise ratio caused by inaccurate jitter elimination; the digital calibration unit 7 is a digital calibration method, which has higher error calibration accuracy compared with analog calibration method.

[0079] Furthermore, based on the aforementioned design concept of a high-speed, high-precision analog-to-digital converter, this invention also provides a method for improving the performance of an analog-to-digital converter, such as... Figure 5 As shown, it includes the following steps:

[0080] S1. Provide an analog-to-digital converter, add a random number generation circuit and an analog random signal generation circuit to the analog-to-digital converter, generate multiple random analog signals through the random number generation circuit and the analog random signal generation circuit, and inject jitter into the analog-to-digital converter through the multiple random analog signals;

[0081] S2. Add an input configuration module, a data rearrangement unit, an integer cycle data recovery module, and an adaptive parameter extraction module to the analog-to-digital converter. Through the cooperation of the input configuration module, the data rearrangement unit, the integer cycle data recovery module, and the adaptive parameter extraction module, extract the correction parameters of each quantization circuit in the analog-to-digital converter.

[0082] S3. Add a parameter memory to the analog-to-digital converter to store the correction parameters. During the test extraction phase, the parameter memory stores the correction parameters once. After the test is passed, the parameter memory stores the correction parameters permanently.

[0083] S4. Add a digital calibration unit to the analog-to-digital converter. In the digital calibration unit, the digital signal obtained by analog-to-digital conversion is calibrated and corrected according to the correction parameters stored in the parameter memory to obtain the corrected digital signal and realize digital calibration.

[0084] The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters.

[0085] In detail, in step S1, a jitter generation structure is formed by a random number generation circuit and an analog random signal generation circuit. The jitter generation structure generates multiple random analog signals, which inject jitter into the analog-to-digital converter (ADC), effectively improving the linearity of the ADC. The jitter generation structure can selectively inject jitter signals (i.e., random analog signals) into some or all quantization levels of the ADC; this is not limited here.

[0086] In detail, step S2, which extracts the correction parameters of each quantization circuit stage in the analog-to-digital converter through the cooperation of the input configuration module, the data rearrangement unit, the integer cycle data recovery module, and the adaptive parameter extraction module, further includes:

[0087] S21. The adaptive parameter extraction module sends a configuration control signal to the input configuration module. Under the control of the configuration control signal, the input configuration module configures and generates analog signals, quantization control signals and output mode control signals.

[0088] S22. The analog-to-digital conversion module receives analog signals, quantization control signals, and output mode control signals. Under the control of the quantization control signal, it performs analog-to-digital conversion on the analog signals to obtain digital signals. Under the control of the output mode control signal, it rearranges the digital signals to obtain rearranged digital signals. Through multiple outputs, it sends all rearranged digital signals to the full cycle data recovery module.

[0089] S23. The adaptive parameter extraction module sends the output data mode information to the full cycle data recovery module. The full cycle data recovery module receives the output data mode information and the rearranged digital signal, and recovers the rearranged digital signal into full cycle data according to the output data mode information, and obtains and outputs the full cycle rearranged digital signal.

[0090] S24. The adaptive parameter extraction module receives the whole-cycle corrected digital signal and extracts the correction parameters from the whole-cycle rearranged digital signal using an adaptive parameter extraction method.

[0091] The adaptive parameter extraction module uses an adaptive parameter extraction method to extract correction parameters, which requires fewer samples and can greatly reduce the computational load of parameter extraction. Step S2 only shows the correction parameter extraction process of the first-stage quantization circuit in the analog-to-digital converter. In this invention, the correction parameters of each stage of the quantization circuit in the analog-to-digital converter need to be extracted separately, which will not be described in detail here.

[0092] In detail, in step S3, a parameter memory is added to the analog-to-digital converter. The parameter memory adopts a combination of one-time storage and fixed storage. The correction parameters of each quantization circuit in the analog-to-digital converter can only be fixed and saved after passing the verification test, which effectively improves the storage efficiency.

[0093] In detail, in step S4, a digital calibration unit is added to the analog-to-digital converter (ADC). In this unit, the digital signal obtained from the ADC's analog-to-digital conversion is calibrated and corrected according to the correction parameters stored in the parameter memory, resulting in a corrected digital signal. This achieves digital calibration. The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters. This effectively improves the ADC's signal-to-noise ratio (SNR) and linearity, avoiding the impact on ADC performance caused by decreasing intrinsic gain and increasing mismatch error as process dimensions shrink. It also completely eliminates injected random jitter, preventing its impact on the ADC's SNR. The calibration method is digital calibration, which, while addressing the problem of decreased SNR and linearity caused by process deviations and insufficient intrinsic gain of devices, offers higher accuracy in error calibration compared to analog calibration methods.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-speed, high-precision analog-to-digital converter, characterized in that, It includes an input configuration module, an analog-to-digital conversion module, an adaptive parameter extraction module, and a full-cycle data recovery module. The adaptive parameter extraction module sends a configuration control signal to the input configuration module. Under the control of the configuration control signal, the input configuration module configures and generates analog signals, quantization control signals, and output mode control signals. The analog-to-digital conversion module receives the analog signal, the quantization control signal, and the output mode control signal, performs analog-to-digital conversion on the analog signal to obtain a digital signal, and under the control of the quantization control signal and the output mode control signal, when the high-speed high-precision analog-to-digital converter is in the parameter extraction working mode, rearranges the digital signal to obtain a rearranged digital signal, and when the high-speed high-precision analog-to-digital converter is in the normal working mode, calibrates the digital signal according to the correction parameters to obtain a corrected digital signal; The adaptive parameter extraction module sends output data mode information to the full-cycle data recovery module. The full-cycle data recovery module receives the output data mode information and the rearranged digital signal, and recovers the rearranged digital signal into full-cycle data according to the output data mode information, thereby obtaining and outputting the full-cycle rearranged digital signal. The adaptive parameter extraction module receives the full-cycle rearranged digital signal and extracts the correction parameter from the full-cycle rearranged digital signal using an adaptive parameter extraction method. The correction parameter is then sent to the parameter memory inside the analog-to-digital converter for storage. The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters.

2. The high-speed, high-precision analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital conversion module includes a first arithmetic circuit, n cascaded quantization circuits, n random number generation circuits, and n analog random signal generation circuits. Each of the n random number generation circuits is connected in a one-to-one correspondence with one of the n analog random signal generation circuits. Each random number generation circuit generates a random digital signal, and each analog random signal generation circuit performs digital-to-analog conversion on the random digital signal to obtain a random analog signal. The first input terminal of the first arithmetic circuit is connected to the analog signal, the second input terminal of the first arithmetic circuit is connected to the first random analog signal, and the output terminal of the first arithmetic circuit is connected to the analog input terminal of the first-stage quantization circuit. The first arithmetic circuit performs an addition operation on the analog signal and the first random analog signal. The feedback adjustment input terminal of the first-stage quantization circuit is connected to... The second random analog signal is connected to the control input of the first-stage quantization circuit, which is connected to the first quantization control signal. The analog output of the first-stage quantization circuit is connected to the analog input of the second-stage quantization circuit, and the digital output of the first-stage quantization circuit outputs the first-stage digital signal. The feedback adjustment input of the i-th-stage quantization circuit is connected to the (i+1)-th random analog signal. The control input of the i-th-stage quantization circuit is connected to the i-th quantization control signal. The analog output of the i-th-stage quantization circuit is connected to the analog input of the (i+1)-th-stage quantization circuit, and the digital output of the i-th-stage quantization circuit outputs the i-th-stage digital signal. The digital output of the n-th-stage quantization circuit outputs the n-th-stage digital signal. Wherein, n is an integer greater than or equal to 2, and i is an integer from 2 to n-1.

3. The high-speed, high-precision analog-to-digital converter according to claim 2, characterized in that, The j-th stage quantization circuit includes a sub-analog-to-digital converter (ADC) and a multiplicative digital-to-analog converter (DAC). The analog input terminal of the sub-ADC serves as the analog input terminal of the j-th stage quantization circuit. The sub-ADC receives the analog input signal and performs analog-to-digital conversion on the analog input signal to obtain a digital output signal. The digital output terminal of the sub-ADC serves as the digital output terminal of the j-th stage quantization circuit. The multiplicative DAC includes a sub-ADC, a second operational circuit, and an amplifier. The sub-ADC receives the digital output signal and performs digital-to-analog conversion on the digital output signal to obtain an analog output signal. The second operational circuit... The first input terminal of the circuit is connected to the analog input terminal of the sub-analog-to-digital converter; the second input terminal of the second operational circuit is connected to the analog output signal; the third input terminal of the second operational circuit serves as the feedback adjustment input terminal of the j-th stage quantization circuit; the third input terminal of the second operational circuit is connected to the random analog signal; the output terminal of the second operational circuit is connected to the input terminal of the amplifier; the second operational circuit performs an operation by subtracting the analog output signal from the analog input signal and adding the random analog signal; the output terminal of the amplifier serves as the analog output terminal of the j-th stage quantization circuit; where j is an integer from 1 to n-1.

4. The high-speed, high-precision analog-to-digital converter according to claim 2, characterized in that, The quantization circuit of the nth stage includes a sub-analog-to-digital converter (ADC). The analog input terminal of the sub-ADC serves as the analog input terminal of the quantization circuit of the nth stage. The sub-ADC receives an analog input signal and performs analog-to-digital conversion on the analog input signal to obtain a digital output signal. The digital output terminal of the sub-ADC serves as the digital output terminal of the quantization circuit of the nth stage.

5. The high-speed, high-precision analog-to-digital converter according to claim 3, characterized in that, The analog-to-digital conversion module further includes a data alignment unit, which receives n random digital signals and n levels of digital signals, and performs alignment processing on the random digital signals and digital signals of each level of the quantization circuit.

6. The high-speed, high-precision analog-to-digital converter according to claim 5, characterized in that, The analog-to-digital converter module further includes a data rearrangement unit. The data rearrangement unit is connected to the output mode control signal and the aligned n random digital signals and the n-level digital signals. Under the control of the output mode control signal, when the high-speed high-precision analog-to-digital converter is in the parameter extraction working mode, the n random digital signals and the n-level digital signals after one sampling and alignment are rearranged to obtain the rearranged digital signal, and the rearranged digital signal is output in multiple steps.

7. The high-speed, high-precision analog-to-digital converter according to claim 6, characterized in that, The analog-to-digital converter module further includes a digital calibration unit, which is connected to the data alignment unit and the parameter memory. When the high-speed, high-precision analog-to-digital converter is in normal working mode, the digital calibration unit calibrates and corrects the n random digital signals and the n-level digital signals after one sampling and alignment according to the correction parameters stored in the parameter memory, to obtain the corrected digital signal.

8. The high-speed, high-precision analog-to-digital converter according to claim 7, characterized in that, The analog-to-digital converter module further includes an output interface unit, which is connected to the data rearrangement unit, the digital calibration unit, and the full-cycle data recovery module. When the high-speed, high-precision analog-to-digital converter is in parameter extraction mode, the output interface unit receives the rearranged digital signal and sends the rearranged digital signal to the full-cycle data recovery module multiple times. When the high-speed, high-precision analog-to-digital converter is in normal operation mode, the output interface unit receives the corrected digital signal and outputs the corrected digital signal.

9. The high-speed, high-precision analog-to-digital converter according to claim 7, characterized in that, The parameter storage includes: The software parameter storage unit is used to receive and store the correction parameters extracted by the adaptive parameter extraction module at one time, and send the correction parameters to the digital calibration unit for digital calibration. The hardware repair parameter storage unit, when the correction parameters output by the software repair parameter storage unit are qualified, sends the correction parameters stored in the software repair parameter storage unit to the hardware repair parameter storage unit and solidifies them, storing them in the hardware repair parameter storage unit for a long time. When the system is powered off and then powered on again, the software repair parameter storage unit reads the correction parameters stored in the hardware repair parameter storage unit once and outputs them.

10. The high-speed, high-precision analog-to-digital converter according to claim 9, characterized in that, The jitter correction parameter includes the actual weight of each of the random analog signals, the gain correction parameter includes the actual gain of each stage of the quantization circuit, and the mismatch error correction parameter includes the actual weight of each sub-digital-to-analog converter in each stage of the quantization circuit.

11. A method for improving the performance of an analog-to-digital converter, characterized in that, The enhancement method is applied to the high-speed, high-precision analog-to-digital converter as described in any one of claims 1-10, and includes the following steps: An analog-to-digital converter is provided, incorporating a random number generation circuit and an analog random signal generation circuit. Multiple random analog signals are generated by the random number generation circuit and the analog random signal generation circuit, and jitter is injected into the analog-to-digital converter through the multiple random analog signals. An input configuration module, a data rearrangement unit, an integer cycle data recovery module, and an adaptive parameter extraction module are added to the analog-to-digital converter. Through the cooperation of the input configuration module, the data rearrangement unit, the integer cycle data recovery module, and the adaptive parameter extraction module, the correction parameters of each quantization circuit in the analog-to-digital converter are extracted. A parameter memory is added to the analog-to-digital converter to store the correction parameters. During the test extraction phase, the parameter memory stores the correction parameters once, and after the test is passed, the parameter memory permanently stores the correction parameters. A digital calibration unit is added to the analog-to-digital converter. In the digital calibration unit, the digital signal obtained by analog-to-digital conversion of the analog-to-digital converter is calibrated and corrected according to the correction parameters stored in the parameter memory to obtain a corrected digital signal, thereby realizing digital calibration. The correction parameters include at least jitter correction parameters, gain correction parameters, and mismatch error correction parameters.

12. The method for improving the performance of an analog-to-digital converter according to claim 11, characterized in that, The step of extracting the correction parameters of each quantization circuit stage in the analog-to-digital converter through the cooperation of the input configuration module, the data rearrangement unit, the integer cycle data recovery module, and the adaptive parameter extraction module includes: The adaptive parameter extraction module sends a configuration control signal to the input configuration module. Under the control of the configuration control signal, the input configuration module configures and generates analog signals, quantization control signals, and output mode control signals. The analog-to-digital conversion module receives the analog signal, the quantization control signal, and the output mode control signal. Under the control of the quantization control signal, it performs analog-to-digital conversion on the analog signal to obtain a digital signal. Under the control of the output mode control signal, it rearranges the digital signal to obtain a rearranged digital signal. The rearranged digital signals are then sent to the full-cycle data recovery module through multiple outputs. The adaptive parameter extraction module sends output data mode information to the full-cycle data recovery module. The full-cycle data recovery module receives the output data mode information and the rearranged digital signal, and recovers the rearranged digital signal into full-cycle data according to the output data mode information, thereby obtaining and outputting the full-cycle rearranged digital signal. The adaptive parameter extraction module receives the full-cycle rearranged digital signal and extracts the correction parameters from the full-cycle rearranged digital signal using an adaptive parameter extraction method.

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