Semiconductor Structure and Method for Preparing the Same

Abstract

The present application provides a semiconductor structure and a method for manufacturing the same, relating to the field of semiconductor technology, and is used to solve the technical problem of large contact resistance of a contact structure. The manufacturing method includes providing a substrate; forming a target layer in an array region and an isolation region of the substrate; performing patterning on the target layer to form a first pattern in the isolation region; forming a first mask layer covering the target layer and the first pattern in the array region and the isolation region; patterning the first mask layer in the array region, and using the first mask layer as a mask to etch the target layer in the array region to form a second pattern in the array region; wherein, the feature size of the first pattern is larger than that of the second pattern; forming a second trench exposing the first pattern in the isolation region, and forming a first contact structure in contact connection with the first pattern in the second trench, and the feature size of the first contact structure is not larger than that of the first pattern. The present application can reduce the contact resistance of the first contact structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, including many repeated memory cells. Each memory cell usually includes a transistor and a capacitor. The gate of the transistor is connected to a word line (WL), the drain is connected to a bit line (BL), and the source is connected to the capacitor.

[0003] With the continuous development of semiconductor chips, their critical dimensions are continuously reduced, and the critical dimensions of the devices formed in the array region of DRAM are also continuously reduced. The gradually reduced critical dimensions often cause over-etching problems during the etching process when preparing connection ends such as contact structures that are in contact with these devices, affecting the comprehensive performance of the devices. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can avoid over-etching or even perforation during the production of the contact structure, and at the same time can reduce the contact resistance of the contact structure, thereby improving the comprehensive performance such as the reliability of the electrical performance of the semiconductor structure.

[0005] To achieve the above object, embodiments of the present application provide the following technical solutions:

[0006] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, including:

[0007] Providing a substrate, the substrate having an array region, an isolation region, and a peripheral circuit region, the isolation region being located between the array region and the peripheral circuit region;

[0008] Forming a target layer on the array region and the isolation region;

[0009] Performing patterning on the target layer of the isolation region to form a plurality of first patterns arranged at intervals in a first direction in the isolation region, the first patterns extending in a second direction; the first direction is perpendicular to the second direction;

[0010] Forming a first mask layer covering the target layer and the first patterns on the array region and the isolation region;

[0011] Pattern the first mask layer of the array region, form a first trench in the first mask layer of the array region, and etch the target layer along the first trench, so that the target layer in the array region forms a plurality of second patterns arranged at intervals along the first direction, the second patterns extend along the second direction, and in the second direction, the first pattern and the second pattern in the same extension direction as it are in contact connection; wherein, the feature size of the first pattern in the first direction is greater than the feature size of the second pattern in the first direction;

[0012] Pattern the first mask layer of the isolation region, and use the patterned first mask layer as a mask to form a second trench in the isolation region, and the second trench exposes the first pattern;

[0013] Form a first contact structure in contact connection with the first pattern in the second trench; wherein, the feature size of the first contact structure in the first direction is not greater than the feature size of the first pattern in the first direction.

[0014] As an optional implementation manner, in the step of patterning the target layer of the isolation region to form a plurality of first patterns arranged at intervals along the first direction in the isolation region, the first patterns extend along the second direction, including:

[0015] Form a second mask layer on the target layer;

[0016] Pattern the second mask layer of the isolation region to form a plurality of third trenches arranged at intervals along the first direction in the second mask layer;

[0017] Etch the target layer along the third trench to pattern the target layer of the isolation region, so that the isolation region forms a plurality of first patterns arranged at intervals along the first direction, and the first patterns extend along the second direction.

[0018] As an optional implementation manner, in the step of forming a target layer on the array region and the isolation region, including:

[0019] Form a first conductive layer, a second conductive layer, a third conductive layer, and an insulating layer on the substrate in sequence from bottom to top along the thickness of the substrate;

[0020] Wherein, the first conductive layer, the second conductive layer, the third conductive layer, and the insulating layer together form the target layer.

[0021] As an alternative implementation, after forming a plurality of first patterns arranged at intervals in the first direction in the isolation region, before forming a first mask layer covering the target layer and the first patterns on the array region and the isolation region, it further includes:

[0022] Forming a dielectric layer between any two adjacent first patterns in the isolation region.

[0023] As an alternative implementation, it further includes:

[0024] While forming the target layer on the array region and the isolation region, simultaneously forming the target layer on the peripheral circuit region.

[0025] As an alternative implementation, after forming the target layer on the peripheral circuit region, it further includes:

[0026] Performing patterning on the target layer in the isolation region, while forming a plurality of first patterns arranged at intervals in the first direction in the isolation region, simultaneously performing patterning on the target layer in the peripheral circuit region, so as to form a third pattern extending in the second direction in the target layer of the peripheral circuit region.

[0027] As an alternative implementation, it further includes: while forming the first mask layer covering the target layer and the first patterns on the array region and the isolation region, simultaneously forming the first mask layer covering the third pattern on the peripheral circuit region.

[0028] As an alternative implementation, it further includes:

[0029] Patterning the first mask layer in the isolation region, while forming a second trench in the first mask layer in the isolation region, simultaneously patterning the first mask layer in the peripheral circuit region, and forming a fourth trench in the first mask layer in the peripheral circuit region, where the fourth trench exposes the source / drain electrodes of the transistors in the peripheral circuit region.

[0030] As an alternative implementation, in the step of forming a first contact structure in contact connection with the first pattern in the second trench, it includes:

[0031] Simultaneously filling a conductive material in the second trench and the fourth trench, where the conductive material in the second trench forms a first contact structure in contact connection with the first pattern; the conductive material in the fourth trench forms a second contact structure in contact connection with the source / drain electrode.

[0032] The second aspect of the embodiments of the present application further provides a semiconductor structure, including:

[0033] a substrate having an array region, an isolation region, and a peripheral circuit region; the isolation region is located between the array region and the peripheral circuit region;

[0034] a first pattern having a plurality of elements, the plurality of first patterns being arranged at intervals in a first direction in the isolation region, and the first pattern extending in a second direction; the first direction and the second direction are perpendicular to each other;

[0035] a second pattern having a plurality of elements, the plurality of second patterns being arranged at intervals in the first direction in the array region, the second pattern extending in the second direction; in the second direction, the first pattern and the second pattern in the same extension direction as it are in contact connection, wherein the feature size of the first pattern in the first direction is greater than the feature size of the second pattern in the first direction;

[0036] a first contact structure disposed in the isolation region, and the first contact structure is in contact connection with the first pattern.

[0037] As an optional implementation manner, the feature size of the first pattern in the first direction is greater than the feature size of the first contact structure in the first direction.

[0038] In the semiconductor structure and its manufacturing method provided by the embodiments of the present application, by separately manufacturing the part of the bit line in the array region and the part in the isolation region through two processes, so that the feature size of the bit line in the isolation region in the first direction (for example, the width of the bit line in the first direction) is greater than the feature size of the bit line in the array region in the first direction, and the feature size of the bit line in the isolation region may not decrease as the feature size of the DRAM decreases, so that the feature size of the bit line in the isolation region in the first direction is not less than the feature size of the first contact structure in the first direction. In this way, when manufacturing the second trench, the part of the bit line in the isolation region is equivalent to the shape of a pad, thereby avoiding the phenomenon of over-etching or even perforation caused by the etching rate of the dielectric layer exposed on both sides of the bit line being greater than the etching rate of the bit line during the manufacturing of the second trench. In addition, increasing the feature size of the bit line in the isolation region can also increase the contact area between the first contact structure and the bit line, thereby reducing the contact resistance between the first contact structure and the bit line, and further improving the comprehensive performance such as the electrical performance reliability of the semiconductor structure.

[0039] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features of the technical solutions, other technical problems that can be solved by the semiconductor structure and its manufacturing method provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 Top view schematic diagram of a semiconductor structure provided by an embodiment of the present application;

[0042] Figure 2 Top view schematic diagram of forming a gate in a semiconductor structure provided by an embodiment of the present application;

[0043] Figure 3 For Figure 2 Cross-sectional structure schematic diagram at A-A in;

[0044] Figure 4 Top view schematic diagram of a mask layer of a patterned array region and an isolation region in a semiconductor structure provided by an embodiment of the present application;

[0045] Figure 5 Cross-sectional structure schematic diagram of a mask layer of a patterned array region and an isolation region in a semiconductor structure provided by an embodiment of the present application;

[0046] Figure 6 Cross-sectional structure schematic diagram of forming a bit line in a semiconductor structure provided by an embodiment of the present application;

[0047] Figure 7 Cross-sectional structure schematic diagram of an isolation region after forming a trench in a semiconductor structure provided by an embodiment of the present application;

[0048] Figure 8 For filling a conductive material in a trench in Figure 7 to form a cross-sectional structure schematic diagram of a contact structure;

[0049] Figure 9 Flow chart schematic diagram of a method for manufacturing a semiconductor structure provided by another embodiment of the present application;

[0050] Figure 10 Top view schematic diagram of forming a first pattern during the manufacturing process of a semiconductor structure provided by another embodiment of the present application;

[0051] Figure 11 Cross-sectional structure schematic diagram of forming a first pattern during the manufacturing process of a semiconductor structure provided by another embodiment of the present application;

[0052] Figure 12 A top view schematic diagram of forming a first mask layer during the preparation of a semiconductor structure provided by another embodiment of the present application;

[0053] Figure 13 A cross-sectional structure schematic diagram of the first mask layer of forming a first mask layer and patterning an array region during the preparation of a semiconductor structure provided by another embodiment of the present application;

[0054] Figure 14 A cross-sectional structure schematic diagram of forming a second pattern during the preparation of a semiconductor structure provided by another embodiment of the present application;

[0055] Figure 15 A top view schematic diagram of forming a second trench during the preparation of a semiconductor structure provided by another embodiment of the present application;

[0056] Figure 16 A cross-sectional structure schematic diagram of forming a second trench during the preparation of a semiconductor structure provided by another embodiment of the present application;

[0057] Figure 17 A cross-sectional structure schematic diagram of forming a first contact structure in a second trench in a semiconductor structure provided by another embodiment of the present application.

[0058] Reference numerals:

[0059] 100 - Substrate; 10 - Bit line; 110 - Target layer; 111 - First conductive layer;

[0060] 112 - Second conductive layer; 113 - Third conductive layer; 114 - Insulating layer; 20 - Gate;

[0061] 30 - Mask layer; 31 - Channel; 32 - Trench; 33 - Contact structure; 34 - Slit;

[0062] 120 - First pattern; 130 - First mask layer; 131 - First trench; 140 - Second pattern;

[0063] 150 - Second trench; 160 - First contact structure; 171 - Third trench;

[0064] 180 - Third pattern; 190 - Fourth trench; 200 - Second contact structure; 210 - Third mask layer. Detailed implementation manners

[0065] In the actual research process, the inventors of the present application found that a dynamic random access memory (DRAM) includes multiple repeating memory cells. Each memory cell generally includes a capacitor and a transistor. The gate of the transistor is connected to a word line (WL for short), the drain is connected to a bit line (BL for short), and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage. The word line is connected to a word line driver through a contact plug located in the peripheral circuit region of the memory cell, so as to facilitate the word line driver to input a voltage signal into the word line.

[0066] Figure 1 A top view schematic diagram of a semiconductor structure provided in an embodiment of the present application; Figure 2 A top view schematic diagram of forming a gate in a semiconductor structure provided in an embodiment of the present application; Figure 3 For Figure 2 A cross-sectional structure schematic diagram at A-A in Figure 4 A top view schematic diagram of a mask layer of a patterned array region and an isolation region in a semiconductor structure provided in an embodiment of the present application; Figure 5 A cross-sectional structure schematic diagram of forming a first pattern during the preparation process of a semiconductor structure provided in an embodiment of the present application; Figure 6 A cross-sectional structure schematic diagram of forming a bit line in a semiconductor structure provided in an embodiment of the present application; Figure 7 A cross-sectional structure schematic diagram of over-etching occurring when forming a trench in an isolation region in a semiconductor structure provided in an embodiment of the present application; Figure 8 For Figure 7 A cross-sectional structure schematic diagram of filling a conductive material in the trench in

[0067] Currently, a general semiconductor structure is generally provided with a substrate 100, on which a word line and a bit line 10 are sequentially arranged. The word line and the bit line 10 are arranged in an interleaved manner. The bit line 10 can be arranged at intervals along the first direction as shown in Figure 1 and extend along the second direction.

[0068] Among them, the substrate includes an array region, an isolation region, and a peripheral circuit region. The isolation region is located between the array region and the peripheral circuit region; a target layer 110 can be formed on the substrate. The target layer 110 can be multiple layers. Exemplarily, the target layer 110 includes a first conductive layer 111, a second conductive layer 112, a third conductive layer 113, and an insulating layer 114 that are sequentially stacked from bottom to top along the thickness direction of the substrate. And the target layer 110 in the peripheral circuit region is patterned to form a gate 20 of a transistor in the peripheral circuit region, as shown in Figure 2 and Figure 3 shown. After that, inFigure 3 A mask layer 30 is formed on the basis of [description above], and the mask layer 30 in the array region and the isolation region is patterned, that is, a channel 31 is formed on the mask layer 30 in the array region and the isolation region. As shown in Figure 4 and Figure 5 shown, using the patterned mask layer 30 as a mask, the target layer 110 on the substrate is etched along the channel 31 to synchronously form a plurality of bit lines 10 arranged at intervals in the first direction in the array region and the isolation region. As shown in Figure 6 shown, since the bit lines 10 in the array region and the bit lines 10 in the isolation region are synchronously formed by the same manufacturing process, the characteristic dimensions (such as width) of the portion of the bit line 10 in the array region in the first direction and the characteristic dimensions of the portion of the bit line 10 in the isolation region in the first direction are the same, that is, the width of the portion of the bit line 10 in the array region and the width of the portion of the bit line 10 in the isolation region are the same. As shown in Figure 6 shown, after forming a plurality of spaced bit lines 10, a dielectric layer, such as a material like silicon dioxide, is usually filled between adjacent bit lines 10.

[0069] However, as the characteristic dimensions of DRAM devices continue to shrink, the critical dimensions of the bit lines 10 are also continuously decreasing, that is, as shown in Figure 6 the characteristic dimensions of the bit line 10 in the first direction are continuously decreasing, while the dimensions of the contact structure formed in the isolation region and connected to the bit line 10 remain unchanged. Therefore, when preparing the trench 32, due to the decrease in the characteristic dimensions of the bit line 10 and the characteristic dimensions of the trench 32 being larger than those of the bit line 10, over-etching is likely to occur in the dielectric layer exposed on both sides of the trench 32 during the etching to form the trench 32, and slits 34 are formed on both sides of the bit line 10 due to over-etching. As shown in Figure 7 shown; after forming the contact structure 33 in the trench 32, the slits 34 are also filled with a conductive material, as shown in Figure 8 shown, resulting in a relatively large electric field at the slits 34; in addition, the spacing between adjacent bit lines 10 also decreases as the characteristic dimensions of DRAM devices continue to shrink. In the case of a high electric field, perforation is likely to occur between adjacent bit lines 10, resulting in a short circuit between adjacent bit lines 10. Moreover, when the characteristic dimensions of the bit line 10 decrease as the characteristic dimensions of DRAM devices continue to shrink, there will also be a technical problem of an increase in the contact resistance between the contact structure 33 and the bit line 10, leading to poor reliability of the electrical performance of the semiconductor structure.

[0070] In view of this, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same. By separately manufacturing the part of the bit line in the array region and the part in the isolation region through two processes, the characteristic size of the bit line in the isolation region in the first direction (for example, the width of the bit line in the first direction) is made larger than the characteristic size of the bit line in the array region in the first direction. The characteristic size of the bit line in the isolation region can be prevented from decreasing as the characteristic size of the DRAM decreases, so that the characteristic size of the bit line in the isolation region in the first direction is not less than the characteristic size of the first contact structure in the first direction. In this way, when manufacturing the second trench, the phenomenon of over-etching or even perforation caused by the etching rate of the dielectric layer exposed on both sides of the bit line being greater than the etching rate of the bit line can be avoided. In addition, increasing the characteristic size of the bit line in the isolation region can also increase the contact area between the first contact structure and the bit line, thereby reducing the contact resistance between the first contact structure and the bit line, and further improving the reliability of the electrical performance of the semiconductor structure.

[0071] In order to make the above objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0072] Figure 9 Schematic flow chart of a method for manufacturing a semiconductor structure provided in another embodiment of the present application; Figure 10 Top view schematic diagram of forming a first pattern during the manufacturing process of a semiconductor structure provided in another embodiment of the present application; Figure 11 Cross-sectional structure schematic diagram of forming a first pattern during the manufacturing process of a semiconductor structure provided in another embodiment of the present application; Figure 12 Top view schematic diagram of forming a first mask layer during the manufacturing process of a semiconductor structure provided in another embodiment of the present application; Figure 13 Cross-sectional structure schematic diagram of forming a first mask layer and patterning the first mask layer in the array region during the manufacturing process of a semiconductor structure provided in another embodiment of the present application; Figure 14 Cross-sectional structure schematic diagram of forming a second pattern during the manufacturing process of a semiconductor structure provided in another embodiment of the present application; Figure 15 Top view schematic diagram of forming a second trench during the manufacturing process of a semiconductor structure provided in another embodiment of the present application;

[0073] Figure 16 Cross-sectional structure schematic diagram of forming a second trench during the manufacturing process of a semiconductor structure provided in another embodiment of the present application; Figure 17Schematic cross-sectional view of forming a first contact structure in a second trench in a semiconductor structure provided by another embodiment of the present application.

[0074] Please refer to Figure 9 As shown, the method for manufacturing a semiconductor structure provided by an embodiment of the present application includes:

[0075] Step S101: Provide a substrate, the substrate having an array region, an isolation region, and a peripheral circuit region, the isolation region being located between the array region and the peripheral circuit region.

[0076] Among them, the substrate 100 can provide a structural basis for subsequent structures and processes, and the material of the substrate 100 can include any one or more of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator substrate, and germanium-on-insulator substrate. In this embodiment, at least part of the substrate is a silicon substrate, and the silicon material can be single-crystalline silicon. The substrate can be prepared by chemical vapor deposition (CVD for short).

[0077] Please refer to Figure 1 As shown, the substrate 100 includes an array region, an isolation region, and a peripheral circuit region. Among them, the array region and the peripheral circuit region are respectively adjacent to the isolation region, that is, the isolation region is disposed between the array region and the peripheral circuit region.

[0078] Among them, the isolation region can include a first region and a second region. Among them, the first region is disposed close to the array region, and the second region is disposed close to the peripheral circuit region.

[0079] For the convenience of description, in the embodiment of the present application, the array region can be represented by I, the first region in the isolation region by II, the second region by III, and the peripheral circuit region by IV.

[0080] In subsequent processes, devices such as bit lines, capacitors, and transistors are formed on the substrate 100. Among them, the bit lines can be arranged at intervals along Figure 1 a first direction in, and extend along a second direction, and a first contact structure 160 is formed on the bit lines in the isolation region, thereby electrically connecting the bit lines to the capacitors.

[0081] Step S102: Form a target layer on the array region and the isolation region.

[0082] Refer to Figure 10 and Figure 11As shown, in the step of forming the target layer on the array region and the isolation region, it includes: the first conductive layer 111, the second conductive layer 112, the third conductive layer 113, and the insulating layer 114 which are stacked in sequence can be formed on the substrate 100 through a CVD process or an atomic layer deposition (ALD) process; wherein, the first conductive layer 111, the second conductive layer 112, the third conductive layer 113, and the insulating layer 114 together form the target layer 110, and the first conductive layer 111 is disposed on the side close to the substrate 100.

[0083] In the embodiment of the present application, taking the preparation of the bit line through the target layer 110 as an example for illustration; exemplarily, the first conductive layer 111, the second conductive layer 112, and the third conductive layer 113 can be a bit line contact layer, a bit line barrier layer, and a bit line conductive layer in sequence. The bit line contact layer can be electrically connected to the source region or the drain region of the active region in the substrate 100, and the material of the bit line contact layer can be polysilicon, etc.; the material of the bit line barrier layer can include but is not limited to titanium nitride to prevent the conductive material in the bit line conductive layer from diffusing into the substrate 100, and at the same time, it also has conductivity; the bit line conductive layer can include but is not limited to conductive materials such as tungsten; the material of the bit line insulating layer 114 can be an insulating material such as silicon nitride to achieve electrical isolation between the bit line conductive layer and other devices on the substrate 100.

[0084] In addition, while forming the target layer 110 in the array region and the isolation region, the target layer 110 is synchronously formed in the peripheral circuit region, so as to etch the target layer 110 in the peripheral circuit region in subsequent processes to form the gate of the transistor.

[0085] Step S103: Pattern the target layer in the isolation region to form a plurality of first patterns arranged at intervals along the first direction in the isolation region, and the first patterns extend along the second direction; the first direction and the second direction are perpendicular to each other.

[0086] Specifically, after synchronously forming the target layer 110 in the array region, the isolation region, and the peripheral circuit region, it further includes:

[0087] A second mask layer (not shown in the figure) is formed on the target layer 110, and the second mask layer in the isolation region is patterned to form a plurality of third trenches 171 arranged at intervals along the first direction in the second mask layer, wherein the third trenches 171 extend along the second direction; then, using the patterned second mask layer as a mask, the target layer 110 is etched along the third trenches 171 to pattern the target layer 110 in the isolation region, so that the remaining target layer 110 in the isolation region is formed into a plurality of first patterns 120 arranged at intervals along the first direction, as Figure 10 and Figure 11 shown; it can be understood that the first pattern 120 can be the part of the bit line in the isolation region.

[0088] In addition, when patterning the target layer 110 in the isolation region to form a plurality of first patterns 120 arranged at intervals in the first direction in the isolation region, the target layer 110 in the peripheral circuit region is simultaneously patterned to form a third pattern 180 extending in the second direction in the target layer 110 of the peripheral circuit region. Among them, the third pattern 180 can be the gate of a transistor, as Figure 11 shown in

[0089] Specifically, after forming the second mask layer on the target layer 110, while patterning the second mask layer in the isolation region, the second mask layer in the peripheral circuit region is simultaneously patterned, and using the patterned second mask layer as a mask, while etching the target layer 110 in the isolation region, the target layer 110 in the peripheral circuit region is etched, so that the remaining target layer 110 in the peripheral circuit region is formed into the gate of a transistor.

[0090] In some embodiments, as shown in combination with Figure 12 and Figure 13 after forming the first pattern 120 in the isolation region and the third pattern 180 in the peripheral circuit region, it further includes:

[0091] A dielectric layer is formed between any two adjacent first patterns 120, and a dielectric layer is simultaneously formed in the peripheral circuit region; the material of the dielectric layer can be silicide, etc.

[0092] Step S104: Form a first mask layer covering the target layer and the first pattern on the array region and the isolation region.

[0093] Please continue to combine Figure 12 and Figure 13 shown in, after forming the first pattern 120 in the isolation region, a first mask layer 130 covering the target layer 110 and the first pattern 120 can be formed on the array region and the isolation by chemical vapor deposition (CVD) process or atomic layer deposition (ALD for short) process. Simultaneously, a first mask layer 130 covering the substrate 100 and the gate is formed in the peripheral circuit region. Among them, the first mask layer 130 can be one layer or multiple layers, and can be adaptively designed according to specific requirements.

[0094] Step S105: Pattern the first mask layer in the array region to form a first trench in the first mask layer of the array region, and etch the target layer along the first trench, so that the target layer in the array region forms a plurality of second patterns arranged at intervals in the first direction. The second patterns extend in the second direction. In the second direction, the first pattern and the second pattern in the same extension direction are in contact connection; among them, the feature size of the first pattern in the first direction is greater than the feature size of the second pattern in the first direction.

[0095] Please continue to combine with Figure 12 and Figure 13 As shown, after forming the first mask layer 130 covering the target layer 110 and the first pattern 120 on the array region and the isolation region, the first mask layer 130 in the array region is patterned to form first trenches 131 in the first mask layer 130 of the array region. Among them, there can be multiple first trenches 131, and the multiple first trenches 131 can be arranged at intervals along the first direction; using the patterned first mask layer 130 as a mask, the target layer 110 in the array region is etched along the first trenches 131. In this way, the target layer 110 covered by the patterned first mask layer 130 in the array region is retained, and the retained target layer 110 is formed into multiple second patterns 140 arranged at intervals along the first direction, as Figure 14 shown in, among which, the second pattern 140 extends along the second direction, and in the second direction, the first pattern 120 and the second pattern 140 in the same extension direction are in contact connection; among them, the feature size of the first pattern 120 in the first direction is greater than the feature size of the second pattern 140 in the first direction.

[0096] It can be understood that the second pattern 140 can be a part of the bit line in the array region. In this way, the second pattern 140 in the array region and the first pattern 120 in the isolation region in the same extension direction together form a complete bit line. And in subsequent processes, a first contact structure 160 in contact connection with the bit line is fabricated on the bit line in the isolation region, so that the bit line can be electrically connected to the capacitor in the semiconductor device through the first contact structure 160, so as to read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0097] Step S106: Pattern the first mask layer in the isolation region, and use the patterned first mask layer as a mask to form a second trench in the isolation region, and the second trench exposes the first pattern.

[0098] In some embodiments, after forming the second pattern 140 in the array region, the first mask layer 130 in the isolation region can be continuously patterned, and using the patterned first mask layer 130 as a mask, a second trench 150 is formed in the isolation region, so that the second trench 150 exposes the first pattern 120. Among them, before patterning the first mask layer 130 in the isolation region, a third mask layer for protecting the array region can be formed in the array region.

[0099] Alternatively, in some other embodiments, after the second pattern 140 is formed in the array region, the first mask layer 130 in the array region, isolation region, and peripheral circuit region may be removed, and a third mask layer 210 may be formed in the array region, isolation region, and peripheral circuit region. Then, the third mask layer 210 in the isolation region is patterned. Using the patterned third mask layer 210 as a mask, a second trench 150 exposing the first pattern 120 is formed in the isolation region, as Figure 15 and Figure 16 shown in

[0100] It should be noted that the second trench 150 may expose the third conductive layer 113 in the first pattern 120, so that the first contact structure 160 formed in the subsequent process is in contact connection with the third conductive layer 113 in the first pattern 120, thereby enabling the first pattern 120 to be electrically connected to the relevant devices in the semiconductor structure through the first contact structure 160.

[0101] In addition, while the second trench 150 is formed in the isolation region, a fourth trench 190 may be simultaneously formed in the peripheral circuit region, where the fourth trench 190 may expose the source / drain electrodes in the transistor.

[0102] Exemplarily, while patterning the first mask layer 130 in the isolation region, the first mask layer 130 in the peripheral circuit region may be simultaneously patterned. Using the patterned first mask layer 130 as a mask, the second trench 150 and the fourth trench 190 are respectively formed in the isolation region and the peripheral circuit region simultaneously, as Figure 15 and Figure 16 shown in

[0103] Step S107: Form a first contact structure in the second trench that is in contact connection with the first pattern; wherein, the characteristic dimension of the first contact structure in the first direction is not greater than the characteristic dimension of the first pattern in the first direction.

[0104] After the second trench 150 exposing the first pattern 120 is formed in the isolation region, a conductive material may be deposited in the second trench 150 through a CVD process or an atomic layer deposition (ALD) process, etc., to form the first contact structure 160 in the second trench 150, as Figure 17 shown in

[0105] In addition, while depositing the conductive material in the second trench 150, the conductive material is simultaneously deposited in the fourth trench 190, so that the conductive material deposited in the fourth trench 190 forms a second contact structure 200, as Figure 17As shown, the second contact structure 200 is in contact connection with the source / drain of the transistor. For example, the drain of the transistor is electrically connected to the bit line through its corresponding second contact structure 200, and the source of the transistor is electrically connected to the capacitor through its corresponding second contact structure 200.

[0106] In the embodiment of the present application, the part of the bit line in the array region and the part in the isolation region are fabricated separately through two processes, so that the feature size of the bit line in the isolation region in the first direction (e.g., the width of the bit line in the first direction) is greater than the feature size of the bit line in the array region in the first direction. The feature size of the bit line in the isolation region may not decrease with the decrease of the feature size of the DRAM, so that the feature size of the bit line in the isolation region in the first direction is not less than the feature size of the first contact structure 160 in the first direction. In this way, when fabricating the second trench 150, it is possible to avoid over-etching or even perforation caused by the etching rate of the dielectric layer exposed on both sides of the bit line being greater than the etching rate of the bit line. In addition, increasing the feature size of the bit line in the isolation region can also increase the contact area between the first contact structure 160 and the bit line, thereby reducing the contact resistance between the first contact structure 160 and the bit line, and further improving the reliability of the electrical performance of the semiconductor structure.

[0107] Please continue to refer to Figure 17 As shown, the embodiment of the present application further provides a semiconductor structure, which can be fabricated by using the preparation method of the above semiconductor structure. The semiconductor structure includes a substrate 100, a first pattern 120, a second pattern 140, and a first contact structure 160. The substrate 100 has an array region, an isolation region, and a peripheral circuit region. The isolation region is located between the array region and the peripheral circuit region; there are multiple first patterns 120, and the multiple first patterns 120 are arranged at intervals in the first direction in the isolation region, and the first pattern 120 extends in the second direction; the first direction is perpendicular to the second direction; there are multiple second patterns 140, and the multiple second patterns 140 are arranged at intervals in the first direction in the array region, and the second pattern 140 extends in the second direction; in the second direction, the first pattern 120 is in contact connection with the second pattern 140 in the same extension direction, wherein the feature size of the first pattern 120 in the first direction is greater than the feature size of the second pattern 140 in the first direction; the first contact structure 160 is disposed in the isolation region, and the first contact structure 160 is in contact connection with the first pattern 120; wherein, the feature size of the first contact structure 160 in the first direction is not greater than the feature size of the first pattern 120 in the first direction.

[0108] It can be understood that, taking the bit line as an example, the first pattern 120 can be the part of the bit line in the isolation region, and the second pattern 140 can be the part of the bit line in the array region.

[0109] In the embodiment of the present application, by making the feature size of the first pattern 120 in the isolation region in the first direction greater than the feature size of the second pattern 140 in the array region in the first direction, and making the feature size of the first pattern 120 in the first direction not less than the feature size of the first contact structure 160 in the first direction, in this way, the part of the bit line in the isolation region is equivalent to a pad for the first contact structure 160, so that the phenomenon that short circuit is likely to occur due to perforation between adjacent bit lines in the isolation region when the electric field is too large can be avoided. In addition, the contact resistance between the first contact structure 160 and the bit line in the isolation region can also be reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0110] In some optional embodiments, the feature size of the first pattern 120 (for example, the part of the bit line in the isolation region) in the first direction is greater than the feature size of the first contact structure 160 in the first direction. In this way, the first pattern 120 is equivalent to the shape of a pad relative to the first contact structure 160, which can further prevent the phenomenon of over-etching or even perforation that is likely to occur when manufacturing the first contact structure 160. In addition, the contact resistance between the first contact structure 160 and the first pattern 120 can be reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0111] Exemplarily, the feature size of the first pattern 120 in the first direction may include but is not limited to 1.2 to 1.8 times the feature size of the first contact structure 160 in the first direction. Exemplarily, the feature size of the first pattern 120 in the first direction may be 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, 1.8 times, etc. of the feature size of the first contact structure 160 in the first direction. Specifically, it can be adaptively set according to actual requirements and will not be specifically limited here.

[0112] In some embodiments, the feature size of the first pattern 120 in the first direction may include but is not limited to 2 to 5 times the feature size of the second pattern 140 in the first direction. In this way, the feature size of the first pattern 120 is large enough, so that while reducing the contact resistance between the first contact structure 160 and the first pattern 120, the problem of over-etching or even perforation between adjacent bit lines caused during the manufacture of the first contact structure 160 can be avoided, and thus the reliability of the electrical performance of the semiconductor structure can be improved.

[0113] In some alternative embodiments, an insulating layer covering the sidewalls of the second pattern 140 in the array region may be formed on the sidewalls of the second pattern 140, and a dielectric layer may be formed between adjacent second patterns 140 to achieve electrical isolation between the second pattern 140 and other devices through the insulating layer; in addition, insulating layers may be provided on the sidewalls of the gates in the peripheral circuit region and the sidewalls of the first pattern 120 to achieve electrical isolation between the second pattern 140 and the gates and other devices through the insulating layers.

[0114] Among them, the insulating layer may be prepared from insulating materials such as silicon nitride.

[0115] In the semiconductor structure and its manufacturing method provided by the embodiments of the present application, by separately manufacturing the part of the bit line in the array region and the part in the isolation region through two processes, the feature size of the bit line in the isolation region in the first direction (for example, the width of the bit line in the first direction) is greater than the feature size of the bit line in the array region in the first direction. The feature size of the bit line in the isolation region may not decrease with the decrease of the feature size of the DRAM, so that the feature size of the bit line in the isolation region in the first direction is not less than the feature size of the first contact structure in the first direction. In this way, when manufacturing the second trench, the phenomenon of over-etching or even perforation caused by the etching rate of the dielectric layer exposed on both sides of the bit line being greater than the etching rate of the bit line can be avoided. In addition, increasing the feature size of the bit line in the isolation region can also increase the contact area between the first contact structure and the bit line, thereby reducing the contact resistance between the first contact structure and the bit line, and further improving the reliability of the electrical performance of the semiconductor structure.

[0116] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0117] In the description of this specification, the description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manners", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, comprising: providing a substrate having an array region, an isolation region and a peripheral circuit region, wherein the isolation region is located between the array region and the peripheral circuit region; forming a target layer on the array region and the isolation region; performing patterning on the target layer of the isolation region to form a plurality of first patterns spaced apart in a first direction in the isolation region, the first patterns extending in a second direction; the first direction is perpendicular to the second direction; forming a first mask layer covering the target layer and the first patterns on the array region and the isolation region; patterning the first mask layer of the array region to form a first trench in the first mask layer of the array region, and etching the target layer along the first trench, so that the target layer of the array region forms a plurality of second patterns spaced apart in the first direction, the second patterns extending in the second direction, and in the second direction, the first pattern and the second pattern in the same extension direction are in contact connection; wherein, the feature size of the first pattern in the first direction is greater than the feature size of the second pattern in the first direction; patterning the first mask layer of the isolation region, and using the patterned first mask layer as a mask to form a second trench in the isolation region, the second trench exposing the first pattern; forming a first contact structure in contact connection with the first pattern in the second trench; wherein, the feature size of the first contact structure in the first direction is not greater than the feature size of the first pattern in the first direction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, in the step of performing patterning on the target layer of the isolation region to form a plurality of first patterns spaced apart in a first direction in the isolation region, the first patterns extending in a second direction, the method includes: forming a second mask layer on the target layer; patterning the second mask layer of the isolation region to form a plurality of third trenches spaced apart in a first direction in the second mask layer; etching the target layer along the third trenches to perform patterning on the target layer of the isolation region, so that the isolation region forms a plurality of first patterns spaced apart in a first direction, the first patterns extending in a second direction.

3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, in the step of forming a target layer on the array region and the isolation region, the method includes: forming a first conductive layer, a second conductive layer, a third conductive layer and an insulating layer on the substrate in sequence from bottom to top along the thickness of the substrate; wherein, the first conductive layer, the second conductive layer, the third conductive layer and the insulating layer together form the target layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming a plurality of first patterns arranged at intervals in a first direction in the isolation region, before forming a first mask layer covering the target layer and the first patterns on the array region and the isolation region, it further includes: Filling a dielectric layer between any two adjacent first patterns.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein, it further includes: While forming a target layer on the array region and the isolation region, simultaneously forming a target layer on the peripheral circuit region.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein, after forming a target layer on the peripheral circuit region, it further includes: Performing patterning on the target layer in the isolation region, while forming a plurality of first patterns arranged at intervals in a first direction in the isolation region, simultaneously performing patterning on the target layer in the peripheral circuit region to form third patterns extending in a second direction in the target layer of the peripheral circuit region.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, it further includes: While forming a first mask layer covering the target layer and the first patterns on the array region and the isolation region, simultaneously forming the first mask layer covering the third patterns on the peripheral circuit region.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, it further includes: Patterning the first mask layer in the isolation region, while forming second trenches in the first mask layer in the isolation region, simultaneously patterning the first mask layer in the peripheral circuit region to form fourth trenches in the first mask layer in the peripheral circuit region, and the fourth trenches expose the source / drain electrodes of the transistors in the peripheral circuit region.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, in the step of forming a first contact structure in contact connection with the first pattern in the second trench, it includes: Simultaneously filling a conductive material in the second trench and the fourth trench, the conductive material in the second trench forms a first contact structure in contact connection with the first pattern; the conductive material in the fourth trench forms a second contact structure in contact connection with the source / drain electrode.

10. A semiconductor structure, wherein, it includes: A substrate having an array region, an isolation region, and a peripheral circuit region; The isolation region is located between the array region and the peripheral circuit region; First patterns, there are a plurality of the first patterns, and the plurality of first patterns are arranged at intervals in a first direction in the isolation region, and the first patterns extend in a second direction; The first direction is perpendicular to the second direction; Second patterns, there are a plurality of the second patterns, and the plurality of second patterns are arranged at intervals in the first direction in the array region, and the second patterns extend in the second direction; In the second direction, the first pattern and the second pattern in the same extension direction as it are in contact connection, wherein a characteristic dimension of the first pattern in the first direction is greater than a characteristic dimension of the second pattern in the first direction; A first contact structure is disposed in the isolation region, and the first contact structure is in contact connection with the first pattern; wherein a characteristic dimension of the first contact structure in the first direction is not greater than a characteristic dimension of the first pattern in the first direction.

11. The semiconductor structure according to claim 10, wherein, the characteristic dimension of the first pattern in the first direction is greater than the characteristic dimension of the first contact structure in the first direction.

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