Component package and semiconductor device

Abstract

An element package (40) includes a semiconductor element (41), a rewiring layer (42), and a sealing resin body (45). The semiconductor element (41) includes a semiconductor substrate (410) having an element region (412) and a scribe region (413), a source electrode and a pad formed on one face (410a) of the semiconductor substrate, and a protective film (411) disposed on the element region in the one face. The sealing resin body includes a sealing resin body (45S) disposed on the one face of the scribe region (413) in such a manner as to have a height not exceeding a rim (411d) of an upper surface of the protective film. The rewiring layer is disposed in a range of the sealing resin body on the protective film to the scribe region.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-146986, filed on September 1, 2020, and incorporates the contents of the base application by reference in its entirety. Technical Field

[0003] The disclosure in this specification relates to component packages and semiconductor devices having such component packages. Background Technology

[0004] Patent Document 1 discloses a component package comprising a semiconductor element, a redistribution layer, and a sealing resin body. The contents of prior art documents are incorporated herein by reference as an explanation of technical elements.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2020-77743 Summary of the Invention

[0008] Semiconductor devices such as power devices have main electrodes and pads on one side of a semiconductor substrate. The main electrodes and pads are exposed from an opening in a protective film disposed on one side, in a manner that allows for connection with a redistribution layer. The protective film is not disposed in the scribe area of ​​the semiconductor device. According to Patent Document 1, a redistribution layer must be formed in the step structure between the upper surface of the protective film and the scribe area in one side of the semiconductor substrate. Based on the above viewpoints or other viewpoints not mentioned, further improvements are required for device packaging.

[0009] In view of such issues, the present disclosure aims to provide a device package and a semiconductor device that can improve the flatness of the redistribution layer.

[0010] The component package disclosed herein includes: a semiconductor component; a semiconductor substrate having a component region for forming the component and a scribe region provided within a predetermined range from the end of the substrate and surrounding the component region; a main electrode and pads formed on one side of the semiconductor substrate; a protective film disposed on the component region in one side such that the main electrode and pads are exposed; a sealing resin body sealing the semiconductor component such that the main electrode and pads are exposed; a redistribution layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor component; and an insulating portion disposed on the scribe region in one side of the semiconductor component such that it has a height not exceeding the outer peripheral edge of the upper surface of the protective film on the component region; the redistribution layer is disposed in the range from the protective film to the insulating portion.

[0011] According to the disclosed component package, the insulating portion is disposed on the scribed area. The insulating portion has a height not exceeding the outer peripheral edge of the upper surface of the protective film. Furthermore, the redistribution layer is disposed within the range from the protective film to the insulating portion. Therefore, compared to a structure without an insulating portion, the flatness of the redistribution layer can be improved.

[0012] Another component package disclosed herein includes: a semiconductor component; a semiconductor substrate having a component region for forming the component and a scribe region provided within a defined range from the end of the substrate and surrounding the component region; a main electrode and a pad formed on one side of the semiconductor substrate; a sealing resin body for sealing the semiconductor component to expose the main electrode and the pad; and a redistribution layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor component; the insulator is in contact with one side of the semiconductor substrate in the range from the component region to the scribe region.

[0013] According to the disclosed device package, the insulator of the redistribution layer contacts one side of the semiconductor substrate in the range from the device region to the scribing region. That is, the protective film is removed from the semiconductor device. Therefore, the flatness of the redistribution layer can be improved.

[0014] The semiconductor device disclosed herein includes a device package, a heat dissipation component, and signal terminals. The device package includes: a semiconductor device, comprising: a semiconductor substrate having a device region for forming the device and a scribing region provided within a predetermined range from the end of the substrate and surrounding the device region; a main electrode and a pad formed on one side of the semiconductor substrate; and a protective film disposed on the device region in one side such that the main electrode and the pad are exposed; a sealing resin body sealing the semiconductor device such that the main electrode and the pad are exposed; a redistribution layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor device; and an insulating portion disposed on the scribing region in one side of the semiconductor device such that it has a height not exceeding the outer peripheral edge of the upper surface of the protective film on the device region; the redistribution layer is disposed in the range from the protective film to the insulating portion; the wiring includes signal wiring connected to the pads; the signal wiring extends across the boundary between the device region and the scribing region in a plan view in the thickness direction of the semiconductor substrate; a heat dissipation component is disposed sandwiching the semiconductor device in the thickness direction; and the signal terminals are engaged with terminal portions exposed from the insulator in the signal wiring and electrically connected to corresponding pads via the signal wiring.

[0015] According to the disclosed semiconductor device, an insulating portion is disposed on the scribing area. The insulating portion has a height not exceeding the outer peripheral edge of the upper surface of the protective film. Furthermore, the redistribution layer is disposed within the range from the protective film to the insulating portion. Therefore, compared to a structure without an insulating portion, the flatness of the redistribution layer can be improved. Moreover, by improving flatness, thinning or breakage of signal traces can be suppressed around the edge directly above the boundary. Bonding wires can be eliminated, simplifying the connection structure and improving the reliability of the electrical connection between the pads and signal terminals.

[0016] Another semiconductor device disclosed herein includes a device package, a heat dissipation component, and signal terminals. The device package includes: a semiconductor element; a semiconductor substrate having an element region for forming the element and a scribe line region provided within a predetermined range from the end of the substrate and surrounding the element region; a main electrode and a pad formed on one side of the semiconductor substrate; a sealing resin body sealing the semiconductor element to expose the main electrode and the pad; and a redistribution layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor element; the insulator is in contact with one side of the semiconductor substrate in the range from the element region to the scribe line region; the wiring has signal wiring connected to the pads, the signal wiring extending across the boundary between the element region and the scribe line region in a plan view in the thickness direction of the semiconductor substrate; a heat dissipation component is disposed to sandwich the semiconductor element in the thickness direction; and the signal terminals are engaged with terminal portions exposed from the insulator in the signal wiring and electrically connected to corresponding pads via the signal wiring.

[0017] According to the disclosed semiconductor device, the insulator of the redistribution layer contacts one side of the semiconductor substrate in the range from the device region to the scribing region. That is, the protective film is removed from the semiconductor device. Therefore, the flatness of the redistribution layer can be improved. Furthermore, by improving flatness, the thinning or breakage of signal wiring can be suppressed around the edge directly above the boundary. Bonding wires can be eliminated, simplifying the connection structure and improving the reliability of the electrical connection between the pads and signal terminals.

[0018] The various embodiments disclosed in this specification employ different technical means to achieve their respective purposes. The reference numerals within parentheses in the claims and their items illustratively indicate the correspondence with portions of the embodiments described later, and are not intended to limit the scope of the technology. The purposes, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a diagram showing the circuit structure of the power conversion device using the semiconductor device of the first embodiment.

[0020] Figure 2 This is a plan view showing the semiconductor device of the first embodiment.

[0021] Figure 3 It is along Figure 2 A cross-sectional view of line III-III.

[0022] Figure 4 It is a planar diagram representing a semiconductor element.

[0023] Figure 5 It is a plan view representing the component package.

[0024] Figure 6 It is along Figure 5 A cross-sectional view of the VI-VI line.

[0025] Figure 7 It is Figure 6 The diagram showing region VII is an enlarged version.

[0026] Figure 8 It is a cross-sectional view showing the manufacturing method of component packaging.

[0027] Figure 9 This is a cross-sectional view representing a reference example.

[0028] Figure 10 This is a cross-sectional view showing a modified example.

[0029] Figure 11 This is a cross-sectional view representing a reference example.

[0030] Figure 12 This is a cross-sectional view showing the component package in the semiconductor device of the second embodiment.

[0031] Figure 13 This is a cross-sectional view showing the component package in the semiconductor device of the third embodiment.

[0032] Figure 14 This is a cross-sectional view showing the component package in the semiconductor device of the fourth embodiment.

[0033] Figure 15 This is a cross-sectional view showing a modified example.

[0034] Figure 16 This is a cross-sectional view showing a manufacturing method for a component package in a semiconductor device according to the fifth embodiment.

[0035] Figure 17 This is a cross-sectional view showing the component package in the semiconductor device of the fifth embodiment.

[0036] Figure 18 This is a cross-sectional view showing a modified example.

[0037] Figure 19 This is a cross-sectional view showing the component package in the semiconductor device of the sixth embodiment.

[0038] Figure 20 This is a cross-sectional view showing the component package in the semiconductor device of the seventh embodiment.

[0039] Figure 21 This is a cross-sectional view showing a manufacturing method for a component package in a semiconductor device according to the eighth embodiment. Detailed Implementation

[0040] Hereinafter, several embodiments are described with reference to the accompanying drawings. In several embodiments, the same reference numerals are sometimes used for functionally and / or structurally corresponding and / or related parts. For details regarding corresponding and / or related parts, please refer to the description of other embodiments.

[0041] The semiconductor device described in this embodiment is, for example, a power conversion device suitable for mobile bodies driven by a rotary electric motor. Examples of mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs), fuel cell vehicles (FCVs), flying vehicles such as drones, ships, construction machinery, and agricultural machinery. Hereinafter, examples suitable for vehicles will be described.

[0042] (First Embodiment)

[0043] First, according to Figure 1 This describes the general structure of the vehicle's drive system.

[0044] <Vehicle drive system>

[0045] like Figure 1 As shown, the vehicle's drive system 1 includes a DC power supply 2, an electric generator 3, and a power conversion device 4.

[0046] DC power supply 2 is a DC voltage source composed of rechargeable and discharging secondary batteries. Examples of secondary batteries include lithium-ion batteries and nickel-metal hydride batteries. Electric generator 3 is a three-phase AC rotating electric motor. Electric generator 3 functions as the vehicle's driving force, i.e., an electric motor. When regenerating, electric generator 3 functions as a generator. Power conversion device 4 performs power conversion between DC power supply 2 and electric generator 3.

[0047] <Power Conversion Device>

[0048] Next, according to Figure 1 The circuit structure of the power conversion device 4 is explained below. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 as the power conversion circuit.

[0049] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the high-potential side power line (P-line 7) and the low-potential side power line (N-line 8). P-line 7 is connected to the positive terminal of the DC power supply 2, and N-line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to P-line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to N-line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power supply 2.

[0050] Inverter 6 is a DC-AC conversion circuit. Controlled by a control circuit (not shown), inverter 6 converts DC voltage into three-phase AC voltage, which is then output to the electric generator 3. This drives the electric generator 3 to produce the specified torque. During regenerative braking of the vehicle, inverter 6 is subjected to the rotational force from the wheels, and the three-phase AC voltage generated by the electric generator 3 is converted back to DC voltage by the control circuit and output to line P 7. Thus, inverter 6 performs bidirectional power conversion between the DC power supply 2 and the electric generator 3.

[0051] Inverter 6 is configured with three-phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P-line 7 and the N-line 8, with the upper arm 9H as the P-line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the corresponding phase winding 3a of the generator 3 via the output line 10. Inverter 6 has six arms. Each arm is configured with switching elements. At least a portion of each of the P-line 7, N-line 8, and output line 10 is constructed from conductive components such as a bus bar.

[0052] In this embodiment, an n-channel MOSFET 11 is used as the switching element constituting each arm. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P-line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N-line 8. Furthermore, the source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are interconnected.

[0053] For each MOSFET 11, a freewheeling diode 12 is connected in anti-parallel. The diode 12 can be a parasitic diode (body diode) of the MOSFET 11, or a diode configured differently from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0054] The power conversion device 4 may also include a converter as a power conversion circuit. The converter is a DC-DC converter circuit that converts DC voltage into DC voltages of different values. The converter is located between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the aforementioned upper and lower arm circuits 9. With this configuration, step-up and step-down voltage conversion can be achieved. The power conversion device 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is located between the DC power supply 2 and the converter.

[0055] The power conversion device 4 may include a drive circuit for switching elements that constitute the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the corresponding arm of the MOSFET 11 according to the drive command from the control circuit. By applying the drive voltage, the drive circuit drives the corresponding MOSFET 11 to either turn on or off. The drive circuit is sometimes referred to as a driver.

[0056] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates drive commands to operate the IGBT 11 and outputs them to the drive circuit. The control circuit generates drive commands based on torque requests input from a higher-level ECU (not shown) and signals detected by various sensors.

[0057] Various sensors are used, such as current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the electric generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured, for example, with a microcomputer. ECU is short for Electronic Control Unit. PWM is short for Pulse Width Modulation.

[0058] Semiconductor Devices

[0059] Next, according to Figure 2 , Figure 3 and Figure 4 This section provides a general description of the overall structure of the semiconductor device. Figure 2 It is a plan view representing a semiconductor device. Figure 2 This is a plan view of the top surface of a semiconductor device. Figure 3 It is along Figure 2 A cross-sectional view of line III-III. Figure 3 The simplified structure of the component package is illustrated in the diagram. Figure 4 It is a plan view showing the schematic structure of the semiconductor components contained in the component package. Figure 4 In the diagram, the area enclosed by the dashed line is the component area.

[0060] Hereinafter, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. The direction orthogonal to the Z direction and for extending external connection terminals is defined as the Y direction. The direction orthogonal to both the Z and Y directions is defined as the X direction. Unless otherwise stated, the shape obtained from planar observation in the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Planar observation in the Z direction is simply represented as planar observation.

[0061] Figure 2 and Figure 3 The semiconductor device 20 shown constitutes one of the arms described above. That is, two semiconductor devices 20 constitute the upper and lower arm circuits 9 of one phase. The semiconductor device 20 includes a sealing resin body 30, a component package 40, heat dissipation components 50 and 60, and main terminals 70 and 71 and signal terminals 72 as external connection terminals.

[0062] The sealing resin body 30 seals a portion of other elements constituting the semiconductor device 20. The remainder of the other elements is exposed outside the sealing resin body 30. The sealing resin body 30 is made of, for example, an epoxy resin. The sealing resin body 30 is formed, for example, by transfer molding. Figure 2 As shown, the planar shape of the sealing resin body 30 is roughly rectangular.

[0063] The component package 40 is obtained by encapsulating the switching element constituting the arm, as well as the wiring connecting the switching element and other elements of the semiconductor device 20. For example... Figures 2-4 As shown, the component package 40 includes a semiconductor component 41, a redistribution layer 42, and a sealing resin body 45.

[0064] Semiconductor element 41 is obtained by forming a switching element in a semiconductor substrate 410 made of silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. Semiconductor element 41 is sometimes referred to as a power element or a semiconductor chip.

[0065] The semiconductor element 41 in this embodiment is obtained by forming the aforementioned n-channel MOSFET 11 in a semiconductor substrate 410 made of SiC. The MOSFET 11 is vertically oriented so that a main current flows in the thickness direction (Z direction) of the semiconductor element 41 (semiconductor substrate 410). The semiconductor element 41 has main electrodes on each surface of the semiconductor substrate 410. The semiconductor element 41 has a gate electrode (not shown). The gate electrode is, for example, in a trench configuration.

[0066] In semiconductor element 41, a source electrode 41S formed on one side of semiconductor substrate 410 and a drain electrode 41D formed on the back side opposite to the one side serve as the main electrode. In the case where diode 12 is a parasitic diode, the source electrode 41S also serves as the anode electrode, and the drain electrode 41D also serves as the cathode electrode. Diode 12 can also be configured on a different chip than MOSFET 11.

[0067] A drain electrode 41D is formed on approximately the entire back side of the semiconductor substrate 410. A source electrode 41S is formed on a portion of one side of the semiconductor substrate 410. On one side of the semiconductor substrate 410, in a region different from the region where the source electrode 41S is formed, a pad 41P is formed as a signal electrode. The pad 41P is electrically isolated from the source electrode 41S.

[0068] Pad 41P is formed in the Y direction near the end opposite to the formation region of source electrode 41S. Pad 41P and source electrode 41S are arranged in the Y direction. Pad 41P includes at least a pad for the gate electrode. The semiconductor element 41 of this embodiment has five pads 41P. Specifically, it includes pads for the gate electrode, a Kelvin source electrode for detecting the potential of source electrode 41S, a current sensing pad, a pad for the anode potential of a temperature-sensing diode (temperature-sensing element) for detecting the temperature of semiconductor element 41, and a pad for the cathode potential of the temperature-sensing diode. The five pads 41P are uniformly formed on one end side in the Y direction in the semiconductor element 41, which has a generally rectangular planar shape, and are arranged in the X direction.

[0069] A redistribution layer 42 is disposed on one side of the semiconductor element 41, namely the source electrode 41S side. The redistribution layer 42 is in contact (closely connected) with one side of the semiconductor element 41. The redistribution layer 42 has a surface on the semiconductor element 41 side, namely the mounting surface 42a, and a surface opposite to the mounting surface 42a in the Z direction, namely the back surface 42b. The semiconductor element 41 is disposed on the mounting surface 42a of the redistribution layer 42.

[0070] The redistribution layer 42 has an insulator 43 and wiring 44 disposed on the insulator 43. The insulator 43 is formed of a resin material such as polyimide. The wiring 44 is formed of a metal with good conductivity such as Cu. The wiring 44 includes source wiring 44S electrically connected to the source electrode 41S and signal wiring 44P electrically connected to the pad 41P. A portion of each of the source wiring 44S and the signal wiring 44P is exposed from the insulator 43 on the back side 42b of the redistribution layer 42. The exposed portion of the signal wiring 44P from the insulator 43 becomes a terminal portion 440P for external connection. The redistribution layer 42 of this embodiment has five signal wirings 44P corresponding to the pad 41P. That is, it has five independent terminal portions 440P.

[0071] The sealing resin body 45 seals at least a portion of the mounting surface 42a of the redistribution layer 42 and the semiconductor element 41. The sealing resin body 45 is formed, for example, from an epoxy resin. The epoxy resin may contain fillers such as silicon dioxide (not shown). The sealing resin body 45 is formed, for example, by compression molding. The sealing resin body 45 is a primary molded body that seals the semiconductor element 41, and the sealing resin body 30 is a secondary molded body that seals the element package 40.

[0072] The sealing resin body 45 has a surface 45a and a back surface 45b opposite to the surface 45a in the Z direction. The surface 45a is a side surface of the semiconductor substrate 410. The sealing resin body 45 together with the semiconductor element 41 constitutes a molded element. The redistribution layer 42 is disposed on the molded element, that is, disposed in the range from the semiconductor element 41 to the sealing resin body 45.

[0073] In this embodiment, the drain electrode 41D is covered by a conductive electrode protector 46. That is, the electrode protector 46 is exposed from the back side 45b. The drain electrode 41D of the semiconductor element 41 may also be exposed from the back side 45b. That is, the element package 40 may also be configured without the electrode protector 46. Details of the element package 40 will be described later.

[0074] Heat sinks 50 and 60 dissipate heat generated by the semiconductor element 41 to the outside of the semiconductor device 20 on both sides in the Z direction. Heat sinks 50 and 60 are sometimes referred to as heat collectors. Heat sinks 50 and 60 are configured to sandwich a portion of the component package 40 containing the semiconductor element 41. Heat sinks 50 and 60 are configured to face each other in the Z direction. In plan view, heat sinks 50 and 60 include the semiconductor element 41 and source wiring 44S. In plan view, heat sinks 50 and 60 also include a portion of signal wiring 44P. In this embodiment, signal wiring 44P extends from pad 41P to an outer region that does not overlap with heat sinks 50 and 60 in plan view. Terminal portion 440P is located outside heat sinks 50 and 60 in plan view. Alternatively, terminal portion 440P may be positioned in an area that overlaps with heat sinks 50 and 60 in plan view.

[0075] As heat dissipation components 50 and 60, for example, metal plates made of Cu, Cu alloys, etc., metal-ceramic substrates such as DBC substrates and AMB substrates, or metal resin substrates with metal and high thermal conductivity resin laminated on them in the same way as metal-ceramic substrates can be used. The metal plate is sometimes called a lead frame. DBC is short for Direct Bonded Copper. AMB is short for Active MetalBrazed. Heat dissipation components 50 and 60 may also have Ni, Au, etc., coatings on the metal surface.

[0076] In this embodiment, the heat dissipation components 50 and 60 are AMB substrates. The heat dissipation component 50 includes an insulating substrate 51 and metal bodies 52 and 53. The insulating substrate 51 is made of nitride ceramic. The metal bodies 52 and 53 are provided as Cu plates or Cu foils. The metal bodies 52 and 53 are bonded to the insulating substrate 51 by a solder containing an active metal such as titanium (Ti).

[0077] Metal body 52 is disposed on the side of the insulating substrate 51 facing the component package 40. Metal body 53 is disposed on the side of the insulating substrate 51 opposite to metal body 52. ​​Metal body 52 is bonded to source wiring 44S via solder 80. Metal body 52 functions as wiring for source electrode 41S. Therefore, heat dissipation component 50 is sometimes referred to as wiring component. Metal body 53 is electrically isolated from metal body 52 via insulating substrate 51. Heat generated by semiconductor device 41 is transferred to metal body 53 via solder 80, metal body 52, and insulating substrate 51. Metal body 53 provides heat dissipation function.

[0078] The heat dissipation component 50 has a generally rectangular planar shape. The heat dissipation component 50 has a face facing the component package 40, i.e., an opposing face 50a, and a face opposite to the opposing face 50a, i.e., a back face 50b. The face of the metal body 52 opposite to the insulating substrate 51 is called the opposing face 50a, and the face of the metal body 53 opposite to the insulating substrate 51 is called the back face 50b. In this embodiment, the back face 50b of the heat dissipation component 50 is exposed from one side 30a of the sealing resin body 30. The back face 50b is sometimes referred to as the heat dissipation surface or the exposed surface. One side 30a is the face of the semiconductor element 41 in the Z direction, i.e., the source electrode 41S side. One side 30a is, for example, a flat surface. The back face 50b is substantially coplanar with one side 30a of the sealing resin body 30.

[0079] Heat sink 60 has the same structure as heat sink 50. Heat sink 60 includes an insulating substrate 61 and metal bodies 62 and 63. Metal body 62 is located on the side of the insulating substrate 61 facing the device package 40. Metal body 62 is bonded to the electrode protector 46 via solder 81. Metal body 62 functions as wiring for the drain electrode 41D. Therefore, heat sink 60 is sometimes referred to as a wiring component. Metal body 63 is located on the side of the insulating substrate 61 opposite to the metal body 62. Metal body 63 is electrically separated from metal body 62 by the insulating substrate 61. Heat generated by the semiconductor device 41 is transferred to metal body 63 via solder 81, metal body 62, and insulating substrate 61. Metal body 63 provides heat dissipation.

[0080] The heat dissipation component 60 has a generally rectangular planar shape. The heat dissipation component 60 has a face facing the component package 40, i.e., an opposing face 60a, and a face opposite to the opposing face 60a, i.e., a back face 60b. The face of the metal body 62 opposite to the insulating substrate 61 is called the opposing face 60a, and the face of the metal body 63 opposite to the insulating substrate 61 is called the back face 60b. In this embodiment, the back face 60b of the heat dissipation component 60 is exposed from the back face 30b of the sealing resin body 30. The back face 60b is sometimes referred to as the heat dissipation surface or the exposed surface. The back face 30b is the back side of the semiconductor element 41, i.e., the drain electrode 41D side. The back face 30b is the face opposite to face 30a in the Z direction. The back face 30b is, for example, a flat surface. The back face 60b is substantially coplanar with the back face 30b of the sealing resin body 30.

[0081] Main terminals 70 and 71, and signal terminal 72, are external connection terminals used to electrically connect the semiconductor device 20 to external devices. Main terminals 70 and 71 are electrically connected to the main electrode. Main terminal 70 is electrically connected to the source electrode 41S. Main terminal 70 is sometimes referred to as the source terminal. Main terminal 71 is electrically connected to the drain electrode 41D. Main terminal 71 is sometimes referred to as the drain terminal.

[0082] The main terminal 70 is connected to the source electrode 41S via the heat sink 50. The main terminal 70 is connected to one end of the metal body 52 of the heat sink 50 in the Y direction. The thickness of the main terminal 70 is, for example, thinner than the metal body 52. ​​The main terminal 70 can be integrally connected to the heat sink 50 (metal body 52) or it can be provided as another component and connected thereto. The main terminal 70 extends from the heat sink 50 in the Y direction and protrudes outward from the side surface 30c of the sealing resin body 30. The main terminal 70 has a bend in the middle of the portion covered by the sealing resin body 30 and protrudes from near the center in the Z direction in the side surface 30c.

[0083] The main terminal 71 is connected to the drain electrode 41D via the heat sink 60. The main terminal 71 is connected to one end of the metal body 62 of the heat sink 60 in the Y direction. The thickness of the main terminal 71 is, for example, thinner than the metal body 62. The main terminal 71 can be integrally connected to the heat sink 60 (metal body 62), or it can be provided as another component and connected thereto. The main terminal 71 extends from the heat sink 60 in the Y direction and protrudes outward from the same side 30c as the main terminal 70. The main terminal 71 also has a bend in the middle of the portion covered by the sealing resin body 30 and protrudes from near the center in the Z direction in the side 30c. Two main terminals 70 and 71 are arranged in the X direction.

[0084] Signal terminals 72 are electrically connected to pads 41P of semiconductor element 41. In this embodiment, signal terminals 72 are connected to terminal portions 440P of redistribution layer 42 via solder 82. That is, signal terminals 72 are electrically connected to pads 41P via solder 82 and signal wiring 44P including terminal portions 440P. Signal terminals 72 extend in the Y direction and protrude outward from side surface 30d of sealing resin body 30. Side surface 30d is the surface opposite to side surface 30c in the Y direction. The semiconductor device 20 of this embodiment has five signal terminals 72 corresponding to pads 41P. Signal terminals 72 are connected to corresponding pads 41P via signal wiring 44P. Solder 80, 81, and 82 are, for example, multi-element lead-free solders containing Cu, Ni, etc., in addition to Sn. Alternatively, conductive bonding agents other than solder, such as sintered silver, can be used instead of solder 80, 81, and 82.

[0085] As described above, in the semiconductor device 20, the semiconductor element 41, which forms one arm, is sealed by the sealing resin body 30. The sealing resin body 30 integrally seals the element package 40, a portion of the heat sink 50, a portion of the heat sink 60, a portion of each of the main terminals 70 and 71, and a portion of each of the signal terminals 72 that have the semiconductor element 41.

[0086] In the Z direction, a semiconductor element 41 is disposed between heat dissipation components 50 and 60. The semiconductor element 41 is held between the opposing heat dissipation components 50 and 60. This allows heat from the semiconductor element 41 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a two-sided heat dissipation structure. The back surface 50b of the heat dissipation component 50 is substantially coplanar with one surface 30a of the sealing resin body 30. The back surface 60b of the heat dissipation component 60 is substantially coplanar with the back surface 30b of the sealing resin body 30. Since the back surfaces 50b and 60b are exposed, heat dissipation is improved.

[0087] In the semiconductor device 20, the semiconductor element 41 is packaged together with the redistribution layer 42. The redistribution layer 42 has signal wiring 44P that electrically relays the pads 41P of the semiconductor element 41 to the signal terminals 72. The signal terminals 72 are soldered to the terminal portions 440P of the signal wiring 44P. This eliminates the need for bonding wires. Furthermore, terminals (metal blocks) can be disposed between the semiconductor element 41 and the heat sink 50 without ensuring the height of the bonding wires. Therefore, the size in the Z-direction can be miniaturized. Furthermore, the structure and manufacturing process can be simplified.

[0088] <Component Package>

[0089] Next, according to Figure 4 , Figure 5 , Figure 6 and Figure 7The details of the component package 40 are explained. Figure 5 It is a plan view representing the component package. Figure 5 For convenience, double-dotted lines are used to represent rewiring layer 42. Figure 6 It is along Figure 5 A cross-sectional view of the VI-VI line. Figure 7 It is Figure 6 The area VII, represented by a single-dotted line, is shown in an enlarged version of the diagram. Figure 7 The structure of component package 40 is simplified by omitting electrodes and other components.

[0090] like Figures 4-6 As shown, the semiconductor device 41 has a protective film 411. The protective film 411 is an electrically insulating film disposed on one side 410a of the semiconductor substrate 410 in such a way as to cover the periphery of the electrode. The protective film 411 is not disposed on the back side 410b of the semiconductor substrate 410. The protective film 411 is sometimes referred to as the device insulating film.

[0091] The protective film 411 has an opening 411a formed at a position overlapping with the source electrode 41S in a plan view. The protective film 411 also has an opening 411b formed at a position overlapping with the pad 41P in a plan view. The opening 411b is provided for each pad 41P. The source electrode 41S and the pad 41P are exposed to the outside through the corresponding openings 411a and 411b. The openings 411a and 411b are through holes that penetrate the protective film 411 in the Z direction. The protective film 411 covers the periphery of the source electrode 41S and the periphery of the pad 41P. In this embodiment, the protective film 411 is made of polyimide.

[0092] Semiconductor substrate 410 has a device region 412 and a scribing region 413. Device region 412 includes the device formation region, i.e., the active region, and an outer peripheral voltage-resistant region. The active region is sometimes referred to as the main region. In the active region, a portion of one side of the MOSFET 11 is formed, such as a trench gate, a base region, and a source region. The outer peripheral voltage-resistant region is the region outside the device region 412, surrounding the device region 412 in a plan view. In the outer peripheral voltage-resistant region, a voltage-resistant structure, such as a guard ring 414, is formed on the surface layer of one side 410a of the semiconductor substrate 410. A source electrode 41S and a pad 41P are formed on the device region 412.

[0093] The scribing region 413, in a plan view, is a region defined from the outer periphery of the semiconductor substrate 410. The scribing region 413 surrounds the component region 412 in the plan view. The scribing region 413 is the cutting region used when the semiconductor substrate is chip-shaped (monolithically processed) from a wafer state. A chip-shaped semiconductor substrate 410 is obtained by cutting a wafer-shaped semiconductor substrate along the scribing region 413. In this embodiment, the protective film 411 is disposed only on the component region 412. The protective film 411 is not disposed on the scribing region 413.

[0094] The redistribution layer 42 is configured in a plan view to overlap with the molded element, namely the semiconductor element 41, and the sealing resin body 45. The insulator 43 of the redistribution layer 42 includes insulating films 431 and 432 configured as multiple layers. The insulating film 431 is stacked on one side of the semiconductor element 41 and on one side 45a of the sealing resin body 45. The insulating film 432 is stacked on the insulating film 431. In this embodiment, the insulating films 431 and 432 are formed using the same material as the protective film 411, specifically polyimide.

[0095] The first insulating film 431 has openings 431a and 431b. Opening 431a is formed in a plan view at a position overlapping with the source electrode 41S. Opening 431a overlaps with at least a portion of opening 411a in the plan view. Opening 431b is formed in a plan view at a position overlapping with the pad 41P. Opening 431b overlaps with at least a portion of opening 411b in the plan view. Opening 431b is provided for each pad 41P.

[0096] The second insulating film 432 has openings 432a and 432b. Opening 432a is formed in a plan view at a position overlapping with the source electrode 41S. Opening 432b is formed at a position overlapping with the terminal portion 440P of the signal wiring 44P.

[0097] Wiring 44 can be formed, for example, by plating, spraying, or printing. In this embodiment, wiring 44 is formed by plating. Source wiring 44S is formed directly above source electrode 41S. Source wiring 44S is at least stacked on the exposed portion of source electrode 41S. Source wiring 44S includes a first layer of wiring disposed on insulating film 431, such that it covers the exposed portion of source electrode 41S within opening 431a. The periphery of the first layer of wiring is covered by insulating film 432. Source wiring 44S may also include a second layer of wiring. The second layer of wiring is stacked on top of the first layer of wiring within opening 432a.

[0098] Signal trace 44P is stacked on the exposed portion of pad 41P. Signal trace 44P comprises a first layer of trace disposed on insulating film 431, such that it covers the exposed portion of pad 41P within opening 431b. A portion of the first layer of trace is exposed through opening 432b, while the remainder is covered by insulating film 432. The exposed portion of the first layer of trace forms the terminal portion 440P of signal trace 44P. The first layer of trace extends from the corresponding pad 41P to the terminal portion 440P in the Y direction, crossing the boundary between component region 412 and scribing region 413.

[0099] The signal wiring 44P may include a second layer of wiring. The second layer of wiring is stacked on top of the first layer of wiring within the opening 432b. The second layer of wiring and the first layer of wiring together constitute the terminal portion 440P. In the wiring 44 of this embodiment, the first layer of wiring is a Cu-based plating. The second layer of wiring is a Ni-based plating, which improves adhesion to solder.

[0100] The sealing resin body 45 seals the semiconductor element 41 as described above. The sealing resin body 45 covers the side surface 410c of the semiconductor substrate 410. The sealing resin body 45 is in contact (close contact) with the side surface 410c. The side surface 410c is a surface that is generally parallel to the Z direction, connecting one side surface 410a and the back surface 410b. In this embodiment, the sealing resin body 45 covers the entire side surface 410c.

[0101] The sealing resin body 45 covers the scribing region 413 in one side 410a of the semiconductor substrate 410. The sealing resin body 45 is laminated on one side 410a in the scribing region 413. The sealing resin body 45 is in contact (close contact) with the scribing region 413. Hereinafter, in the plan view, the sealing resin body 45 disposed on one side 410a of the semiconductor substrate 410, i.e., on the scribing region 413, is referred to as sealing resin body 45S. Figure 6 and Figure 7 As shown, the sealing resin body 45S contacts the side surface 411c of the outer peripheral end of the defined protective film 411. The lower end of the side surface 411c defines the boundary between the element region 412 and the scribing region 413.

[0102] The sealing resin body 45S covers the entire surface of the side surface 411c. The sealing resin body 45S is in contact (close contact) with the side surface 411c. One side surface 45a of the sealing resin body 45S is substantially coplanar with at least the outer peripheral edge 411d of the upper surface of the protective film 411 disposed on the element region 412. The upper surface of the protective film 411 is the side opposite to the semiconductor element 41. The edge 411d of the upper surface is the portion of the protective film 411 disposed on the element region 412 within a defined range from the outer peripheral end. The edge 411d is connected to the side surface 411c. The edge 411d corresponds to the outer peripheral edge. One side surface 45a of the sealing resin body 45 corresponds to the upper surface of the sealing resin body.

[0103] The sealing resin body 45 does not cover the upper surface of the included edge portion 411d of the protective film 411. The insulator 43 of the redistribution layer 42 is in close contact with the upper surface of the included edge portion 411d of the protective film 411 and one side 45a of the sealing resin body 45 containing the sealing resin body 45S.

[0104] <Component Package Manufacturing Method>

[0105] Next, an example of the manufacturing method of the above-described component package 40 will be described. Figure 8 It is a cross-sectional view showing the manufacturing process. Figure 8 and Figure 7 Correspondingly, semiconductor element 41 is simplified and illustrated.

[0106] First, prepare semiconductor components 41 and... Figure 8 The support substrate 100 is shown. The support substrate 100 has an adhesive layer (not shown) on one side. Semiconductor elements 41 are attached to one side of the support substrate 100 with the source electrode 41S facing each other. The support substrate 100 is wafer-shaped, and multiple semiconductor elements 41 are attached to a single support substrate 100. The semiconductor elements 41 are attached such that the upper surface of the protective film 411, including the edge portion 411d, is in close contact with the support substrate 100, and a gap is formed between the side surface 411c and the scribe area 413 of the side surface 410a and the support substrate 100. Furthermore, an electrode protector 46 is attached to the drain electrode 41D of the semiconductor element 41. Figure 8 Electrode protection component 46 is omitted in the text.

[0107] Next, the sealing resin body 45 is formed. For example, by compression molding, multiple semiconductor elements 41 are sealed together with one side of the support substrate 100. In this way, the sealing resin body 45 is formed together for multiple semiconductor elements 41. Figure 8As shown, resin enters the gap defined by the support substrate 100, the side surface 411c of the protective film 411, and the scribed area 413 in one surface 410a. The gap is filled with resin. Furthermore, the back surface 410b side of the semiconductor substrate 410, i.e., the electrode protector 46, is also covered by the sealing resin body 45. After molding, the support substrate 100 is peeled off. Thus, a molded wafer is formed.

[0108] Next, a redistribution layer 42 is formed. The redistribution layer 42 is formed on the molded wafer. That is, the redistribution layer 42 is formed on multiple semiconductor elements 41 together. First, a first insulating film 431 is formed to cover one side of the semiconductor element 41 and one side 45a of the sealing resin body 45, and openings 431a and 431b are formed by patterning. After patterning the insulating film 431, a first layer of wiring 44 is formed by plating. Next, a second insulating film 432 is formed, and openings 432a and 432b are formed by patterning. After patterning the insulating film 432, a second layer of wiring 44 is formed by plating as needed. Through the above, a wafer-shaped redistribution layer 42 having wiring 44 corresponding to each semiconductor element 41 is formed.

[0109] Next, the sealing resin body 45 is thinned. The sealing resin body 45 is ground from the back side 45b until it reaches the middle of the electrode protector 46. As a result, the electrode protector 46 is exposed from the back side 45b.

[0110] Next, the wafer-shaped sealing resin body 45 and redistribution layer 42 formed together are cut. Thus, the sealing resin body 45 and redistribution layer 42 are monolithically assembled for each semiconductor element 41. Through the above, the device package 40 can be obtained.

[0111] <Summary of the First Implementation>

[0112] Figure 9 This is a cross-sectional view representing a reference example. In the reference example, elements that are the same as or related to elements in this embodiment are indicated by adding 'r' to the end of the reference numerals in this embodiment. Figure 9 and Figure 7 correspond.

[0113] In the reference example, the protective film 411r is not disposed on the scribing region 413r. Furthermore, the sealing resin body 45r is not disposed on one side 410ar of the semiconductor substrate 410r. The molding element has a stepped structure between the edge 411dr of the upper surface of the protective film 411r and the scribing region 413r in one side 410ar of the semiconductor substrate 410r.

[0114] A redistribution layer 42r is formed on the semiconductor element 41r and the sealing resin body 45. The thickness of the signal wiring 44Pr and other wirings 44r, and / or the insulator 43r, becomes uneven on the stepped structure portion of the molded element compared to the flat structure portion. On the stepped structure portion, for example, the thickness of the wiring 44r becomes thinner, which may cause wire breakage. In addition, the thinning of the insulator 43r may reduce the insulation (withstand voltage).

[0115] In particular, when the semiconductor element 41r is used in a power conversion circuit, the thickness of the protective film 411r is tens of micrometers. Therefore, due to the large step difference, defects in the redistribution layer 42 are prone to occur. In applications other than power devices, the thickness of the protective film is several micrometers.

[0116] Furthermore, if a support substrate in which the semiconductor substrate 410r and the sealing resin 45r are substantially coplanar is used, it is possible that during bonding, the semiconductor element 41r may be recessed into the support substrate side, creating a stepped structure at the end of one side 410r between it and the other side 45ar of the sealing resin 45r. This step is smaller than the step on the protective film 411r side, and is on the order of a few μm. Defects may occur in the redistribution layer 42 directly above and around this stepped structure.

[0117] In this embodiment, as described above, a sealing resin body 45S is disposed on a surface 410a of the semiconductor substrate 410 in the scribing region 413. The sealing resin body 45S has a height on the scribing region 413 that does not exceed the height of the edge 411d above the upper surface of the protective film 411. The sealing resin body 45S does not protrude upwards beyond the edge 411d in the scribing region 413. The distance between the surface 45a of the sealing resin body 45S and the surface 410a of the semiconductor substrate 410 is less than or equal to the distance between the edge 411d and the surface 410a of the protective film 411. The sealing resin body 45S largely fills the step difference between the edge 411d and the surface 410a of the scribing region 413.

[0118] The redistribution layer 42 is disposed on the upper surface of the protective film 411, including the edge portion 411d, and on one side 45a of the sealing resin body 45, including the sealing resin body 45S. For example... Figure 7 As shown, the redistribution layer 42 is disposed across the boundary between the protective film 411 and the sealing resin body 45S, spanning the boundary between the component region 412 and the scribing region 413. Figure 7 In this diagram, the boundary is represented by a single-dot dashed line. Therefore, compared to the structure in which the sealing resin body 45S is not disposed on the dashed area 413, i.e., the structure shown in the reference example, the flatness of the redistribution layer 42 can be improved. Specifically, the flatness of the redistribution layer 42 can be improved in the periphery directly above the boundary between the component area 412 and the dashed area 413.

[0119] Furthermore, since the sealing resin 45S covers the scribing area 413, no step structure is formed between the sealing resin 45 and the end of one side 410a of the semiconductor substrate 410. As a result, the flatness of the redistribution layer 42 can also be improved in the periphery directly above the end of one side 410a of the semiconductor substrate 410.

[0120] In this embodiment, the sealing resin body 45S constitutes an insulating portion stacked on the scribed region 413. The sealing resin body 45S contacts the side surface 411c of the protective film 411. Since components other than the sealing resin body 45S can be omitted, the structure of the component package 40 can be simplified. Furthermore, the manufacturing process can be simplified.

[0121] In this embodiment, one side 45a of the sealing resin body 45S is substantially coplanarly connected to the edge 411d of the upper surface of the protective film 411. The one side 45a of the sealing resin body 45S and the edge 411d of the protective film 411 are continuously flat. The height in the Z direction, based on one side 410a, is approximately equal at one side 45a and the edge 411d of the sealing resin body 45S. With this substantially coplanar structure, the wiring layer 42 is substantially flat around the periphery directly above the boundary between the element region 412 and the scribing region 413. That is, flatness can be further improved.

[0122] In this embodiment, the signal wiring 44P, which is connected to the pad 41P of the semiconductor element 41, extends across the boundary between the element region 412 and the scribing region 413 in a plan view. However, since a sealing resin body 45S is disposed on the scribing region 413, thinning or breakage of the signal wiring 44P can be suppressed around the periphery directly above the boundary. This simplifies the connection structure by eliminating bonding wires and improves the reliability of the electrical connection between the pad 41P and the signal terminal 72. By eliminating bonding wires, lead deformation and breakage do not occur during the molding of the sealing resin body 30.

[0123] In this embodiment, a MOSFET 11, which is a power switching element, is formed in the semiconductor element 41. The semiconductor element 41 constitutes an inverter 6 as a power conversion circuit. Therefore, the protective film 411 is relatively thick, with a thickness of several tens of micrometers. However, since a sealing resin body 45S is disposed on the scribing region 413, the flatness of the redistribution layer 42 can be improved even if there is a large step difference between the edge 411d and the surface 410a.

[0124] <Variation Example>

[0125] This illustrates an example where one side 45a of the sealing resin body 45S disposed on the scribed area 413 is substantially coplanarly connected to the edge 411d of the upper surface of the protective film 411, but is not limited thereto. For example, it may also be as follows: Figure 10 As shown, the sealing resin body 45S is arranged such that one side 45a is positioned lower than the edge portion 411d. Figure 10 For simplicity, the redistribution layer 42 is omitted in the diagram.

[0126] Regarding the distance to surface 410a, surface 45a of the sealing resin body 45S is shorter than edge 411d. The sealing resin body 45S contacts only the lower portion of the side surface 411c in the Z direction, and not the upper portion. Even with this structure, the flatness of the redistribution layer 42 can be improved compared to a structure where the sealing resin body 45S is not disposed on the scribing region 413. Specifically, the flatness of the redistribution layer 42 can be improved in the periphery directly above the boundary between the component region 412 and the scribing region 413.

[0127] (Second Implementation)

[0128] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the size of the filler contained in the sealing resin body was not specifically mentioned. Instead, the size of the filler may be specified.

[0129] Figure 11 This is a cross-sectional view showing a reference example of a component package. Figure 11 and Figure 7 Correspondingly, in a structure where the sealing resin body 45r is disposed on the scribe line region 413r, during the molding of the sealing resin body 45r, filler may be disposed on the scribe line region 413r. In this case, due to... Figure 11 As shown, a redistribution layer 42 is formed on the filler 450r, so the flatness of the insulator 43r and / or signal wiring 44Pr (wiring 44r) decreases around the top of the filler 450r.

[0130] If the thickness of the insulator 43r, such as the insulating film 431r, becomes thinner, the insulation distance from the wiring 44r to the outside of the rewiring layer 42r becomes shorter. This can lead to a decrease in withstand voltage and short circuits. Because the portion of the sealing resin 45Sr between the filler 450r and the rewiring layer 42r is thinner, cracks are more likely to form. Since the insulator 43r (insulating film 431r) directly above is also thinner, cracks may propagate towards the insulator 43r.

[0131] If the thickness of the sealing resin body 45r directly below the filler 450r becomes thinner, the peeling of the sealing resin body 45r relative to the semiconductor element 41r can proceed easily. Specifically, it can easily proceed from the side 410cr side through the thinner side 410ar to the side 411cr side of the protective film 411r.

[0132] In this embodiment, such as Figure 12 As shown, the particle size (diameter) of the filler 450 included in the sealing resin body 45 is larger than the step difference between the edge 411d of the upper surface of the protective film 411 and the scribe region 413 in one side 410a of the semiconductor substrate 410. The filler was screened by using only fillers 450 with particle sizes larger than the step difference. Therefore, the filler 450 does not enter the area opposite to the scribe region 413 and the redistribution layer 42. The sealing resin body 45S on the scribe region 413 does not contain filler 450, while the sealing resin bodies 45 other than the sealing resin body 45S contain filler 450. This other structure is the same as the structure described in the prior embodiment.

[0133] <Summary of the Second Implementation>

[0134] As described above, in this embodiment, only filler 450 with a particle size larger than the step difference between the edge 411d of the upper surface of the protective film 411 and the scribe region 413 in one side 410a of the semiconductor substrate 410 is used. Therefore, as in the previous embodiment... Figure 8 When the sealing resin body 45 is formed as shown, it is possible to prevent the filler 450 from entering the opposing region of the scribe region 413 of the support substrate 100 and the semiconductor substrate 410. Therefore, it is possible to prevent the filler 450 from being disposed within the sealing resin body 45S on the scribe region 413. Thus, the scribe region 413 can be covered with the sealing resin body 45S, and the flatness of the redistribution layer 42 can be improved.

[0135] Preferably, a filler 450 with a particle size more than twice the step size can be used. This can more effectively prevent the filler 450 from being disposed in the opposite region of the scribing region 413 and the redistribution layer 42.

[0136] The structure of this embodiment can also be modified from the previous embodiments (see reference). Figure 10 In a structure where the sealing resin body 45S on the marked area 413 is lower than the edge portion 411d, it is possible to prevent the filler 450 from being disposed within the sealing resin body 45S.

[0137] (Third Implementation)

[0138] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, a sealing resin body is disposed on the scribing area. Alternatively, a protective film may be disposed on the scribing area.

[0139] Figure 13 This is a cross-sectional view showing the structure of the element package 40 in the semiconductor device 20 of this embodiment. Figure 13 and Figure 7 Corresponding. For example, Figure 13 As shown, a protective film 411 is disposed on one side 410a of the semiconductor substrate 410, on the scribing region 413. The protective film 411 is disposed not only on the element region 412, but also on the scribing region 413.

[0140] Hereinafter, the portion of the protective film 411 that overlaps with the component region 412 in the plan view, i.e., the portion on the component region 412, is referred to as protective film 411E. Furthermore, the portion of the protective film 411 that overlaps with the scribing region 413 in the plan view, i.e., the portion on the scribing region 413, is referred to as protective film 411S. Protective film 411S covers the entire surface 410a of the scribing region 413. Protective film 411S is in close contact with surface 410a of the scribing region 413.

[0141] The upper surface 411e of the protective film 411S and the edge 411d of the upper surface of the protective film 411E are connected approximately coplanarly. The edge 411d of the protective film 411E is the portion within a defined range from the boundary of the protective film 411S, i.e., from the outer peripheral end of the protective film 411E. The protective films 411E and 411S are integrally formed using the same material. Specifically, polyimide is used, and the film is formed in a single process by spin coating.

[0142] On one side of the semiconductor element 41, only the source electrode 41S and the pad 41P are exposed from the protective film 411. One side 410a of the semiconductor substrate 410 is not exposed from the protective film 411. The sealing resin body 45 is in contact (closely connected) with the protective film 411S. The sealing resin body 45 is in contact (closely connected) with the outer peripheral end of the protective film 411S, i.e., the side surface 411c of the outer peripheral side of the protective film 411. One side 45a of the sealing resin body 45 is substantially coplanarly connected to the upper surface 411e of the protective film 411S. Other than this, the structure is the same as that described in the prior embodiment.

[0143] <Summary of the Third Implementation>

[0144] The component package 40 and semiconductor device 20 of this embodiment can achieve the same effects as the structure described in the first embodiment. Specifically, as described above, a protective film 411S is provided on the scribing region 413 in one side 410a of the semiconductor substrate 410. The protective film 411S has a height not exceeding the edge 411d of the upper surface of the protective film 411E on the component region 412. The protective film 411S largely fills the step difference between the edge 411d and the one side 410a of the scribing region 413. The redistribution layer 42 is disposed across the boundary between the component region 412 and the scribing region 413, in the area from the upper surface of the protective film 411E including the edge 411d to the upper surface 411e of the protective film 411S.

[0145] Therefore, compared to a structure in which no protective film 411S is disposed on the scribing region 413, the flatness of the redistribution layer 42 can be improved. Specifically, the flatness of the redistribution layer 42 can be improved in the periphery directly above the boundary between the component region 412 and the scribing region 413.

[0146] By configuring the protective film 411S, as in the prior embodiment... Figure 8 When the sealing resin body 45 is formed as shown, it is possible to prevent the sealing resin body 45 (filler 450) from entering the opposing region of the scribe region 413 between the support substrate 100 and the semiconductor substrate 410. Therefore, even if a sealing resin body 45 containing filler 450 is used, the flatness of the redistribution layer 42 can be improved.

[0147] In this embodiment, the protective film 411S covers the scribing area 413, and the sealing resin body 45 contacts the side surface 411c of the protective film 411S. Therefore, no step structure is formed between the semiconductor element 41 and the sealing resin body 45 at the end of one side surface 410a of the semiconductor substrate 410. This also improves the flatness of the redistribution layer 42 around the area directly above the end of one side surface 410a of the semiconductor substrate 410.

[0148] In this embodiment, the protective film 411S forms an insulating portion stacked on the scribed region 413. The protective film 411S is connected to the protective film 411E. Since components other than the protective film 411S can be omitted, the structure of the component package 40 can be simplified. Furthermore, the manufacturing process can be simplified. In addition, the protective film 411S, made of polyimide, has better adhesion to the sealing resin body 45 than the semiconductor substrate 410. Therefore, even if the sealing resin body 45 is peeled off from the side 410c, the protective film 411S can suppress the peeling process.

[0149] In this embodiment, the upper surface 411e of the protective film 411S and the edge 411d of the upper surface of the protective film 411E are connected approximately coplanarly. The height in the Z direction, based on surface 410a, is approximately equal at the upper surface 411e and the edge 411d. With this approximately coplanar structure, the wiring layer 42 is approximately flat around the periphery directly above the boundary between the element region 412 and the scribing region 413. That is, flatness can be further improved.

[0150] In this embodiment, the signal wiring 44P extends across the boundary between the component region 412 and the scribing region 413 in a plan view. However, since a protective film 411S is disposed on the scribing region 413, thinning or breakage of the signal wiring 44P can be suppressed around the periphery directly above the boundary. This simplifies the connection structure by eliminating bonding wires and improves the reliability of the electrical connection between the pad 41P and the signal terminal 72. By eliminating bonding wires, lead deformation and breakage do not occur during the molding of the sealing resin body 30.

[0151] In this embodiment, a MOSFET 11, which is a power switching element, is formed in the semiconductor element 41, and the protective film 411E is relatively thick, about tens of μm. However, a protective film 411S is disposed on the scribing region 413. As a result, even if there is a large step difference between the edge 411d and the surface 410a, the flatness of the redistribution layer 42 can be improved.

[0152] <Variation Example>

[0153] An example is shown where the upper surface 411e of the protective film 411S disposed on the scribing region 413 is substantially coplanarly connected to the edge 411d of the upper surface of the protective film 411E, but this is not the only example. Although the illustration is omitted, it can also be compared with... Figure 10 Similarly, the protective film 411S is provided in such a way that the upper surface 411e is positioned lower than the edge portion 411d. Even with this structure, the flatness of the redistribution layer 42 can be improved compared to a structure in which the protective film 411S is not provided on the scribing area 413.

[0154] (Fourth implementation)

[0155] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, a sealing resin body and a protective film are provided on the scribed area. Alternatively, a resin film other than the sealing resin body and the protective film may be provided.

[0156] Figure 14 This is a cross-sectional view showing the structure of the element package 40 in the semiconductor device 20 of this embodiment. Figure 14 and Figure 7 Corresponding. For example, Figure 14 As shown, the semiconductor element 41 has a resin film 415 in addition to the protective film 411 on one side 410a of the semiconductor substrate 410 in the scribing region 413. The resin film 415 is not formed integrally with the protective film 411 in a single process, but is formed additionally after the formation of the protective film 411.

[0157] The resin film 415 can be formed using the same material as the protective film 411 (e.g., polyimide). The resin film 415 can also be formed using a different resin material than the protective film 411. Preferably, the resin material has a coefficient of linear expansion similar to that of the protective film 411. In this embodiment, the resin film 415 is made of the same material as the protective film 411 (polyimide). The resin film 415 is formed, for example, by a spray coating method.

[0158] The resin film 415 covers the entire surface of one side 410a of the scribing area 413. The resin film 415 is in close contact with one side 410a of the scribing area 413. The resin film 415 is in contact (closely contacted) with the side 411c of the protective film 411. The upper surface 415a of the resin film 415 and the edge 411d of the upper surface of the protective film 411 are connected substantially coplanarly.

[0159] The sealing resin body 45 is in contact (close contact) with the resin film 415. The sealing resin body 45 is in contact (close contact) with the outer peripheral side 415b of the resin film 415. One side 45a of the sealing resin body 45 is substantially coplanarly connected to the upper surface 415a of the resin film 415. Other than this, the structure is the same as that described in the prior embodiment.

[0160] <Summary of Implementation Method 4>

[0161] The component package 40 and semiconductor device 20 of this embodiment can achieve the effects of the structure described in the third embodiment. Specifically, as described above, an additional resin film 415 is provided on the scribing region 413 in one side 410a of the semiconductor substrate 410. The resin film 415 has a height not exceeding the edge 411d of the upper surface of the protective film 411. The resin film 415 largely fills the step difference between the edge 411d and one side 410a of the scribing region 413. The redistribution layer 42 is disposed across the boundary between the component region 412 and the scribing region 413, in the area from the upper surface of the protective film 411 including the edge 411d to the upper surface 415a of the resin film 415.

[0162] Therefore, compared to a structure where the resin film 415 is not disposed on the scribing region 413, the flatness of the redistribution layer 42 can be improved. Specifically, the flatness of the redistribution layer 42 can be improved in the periphery directly above the boundary between the component region 412 and the scribing region 413. Through the arrangement of the resin film 415, as in the prior embodiment... Figure 8 When the sealing resin body 45 is formed as shown, it is possible to prevent the sealing resin body 45 (filler 450) from entering the opposing region between the scribe region 413 of the support substrate 100 and the semiconductor substrate 410. Therefore, even if a sealing resin body 45 containing filler 450 is used, the flatness of the redistribution layer 42 can be improved.

[0163] In this embodiment, the resin film 415 covers the scribing area 413, and the sealing resin body 45 contacts the side surface 415b of the resin film 415. Therefore, no step structure is formed between the semiconductor element 41 and the sealing resin body 45 at the end of one side surface 410a of the semiconductor substrate 410. This also improves the flatness of the redistribution layer 42 around the area directly above the end of one side surface 410a of the semiconductor substrate 410.

[0164] In this embodiment, the resin film 415 forms an insulating portion stacked on the scribing region 413. The resin film 415 contacts the side surface 411c of the protective film 411. Since the resin film 415 is made of the same material as the protective film 411, the structure of the component package 40 can be simplified. The adhesion between the resin film 415 and the sealing resin body 45 is higher than that between the resin film 415 and the sealing resin body 45. In particular, the resin film 415, made of polyimide, has high adhesion to the sealing resin body 45. Therefore, even if the sealing resin body 45 is peeled off from the side surface 410c, the progress of peeling can be suppressed by the resin film 415.

[0165] In this embodiment, the upper surface 415a of the resin film 415 and the edge 411d of the upper surface of the protective film 411 are connected approximately coplanarly. The height in the Z direction, based on surface 410a, is approximately equal at the upper surface 415a and the edge 411d. With this approximately coplanar structure, the wiring layer 42 is approximately flat around the periphery directly above the boundary between the element region 412 and the scribing region 413. That is, flatness can be further improved.

[0166] In this embodiment, in a plan view, the signal wiring 44P extends across the boundary between the component region 412 and the scribing region 413. However, since a resin film 415 is disposed on the scribing region 413, thinning or breakage of the signal wiring 44P can be suppressed around the periphery directly above the boundary. This simplifies the connection structure by eliminating bonding wires and improves the reliability of the electrical connection between the pad 41P and the signal terminal 72. By eliminating bonding wires, lead deformation and breakage do not occur during the molding of the sealing resin body 30.

[0167] In this embodiment, a MOSFET 11, which is a power switching element, is formed in the semiconductor element 41, and the protective film 411 is relatively thick, about tens of micrometers. However, a resin film 415 is disposed on the scribing region 413. As a result, even if there is a large step difference between the edge 411d and the surface 410a, the flatness of the redistribution layer 42 can be improved.

[0168] <Variation Example>

[0169] An example is shown where the upper surface 415a of the resin film 415 disposed on the scribing region 413 is substantially coplanarly connected to the edge 411d of the upper surface of the protective film 411, but this is not the only example. Although the illustration is omitted, it can also be compared with... Figure 10 Similarly, the resin film 415 is arranged such that the upper surface 415a is positioned lower than the edge portion 411d. This structure also improves the flatness of the redistribution layer 42 compared to a structure in which no resin film 415 is disposed on the scribing area 413.

[0170] like Figure 15 As shown, a resin film 415 can also be provided to cover a portion of the side surface 410c of the semiconductor substrate 410. The resin film 415 integrally covers one side surface 410a of the scribing region 413 and a portion of the side surface 410c connected to the one side surface 410a. As described above, the resin film 415 has a high adhesion to the sealing resin body 45, so the progress of peeling of the sealing resin body 45 can be suppressed in the middle of the side surface 410c.

[0171] (Fifth Embodiment)

[0172] This embodiment is a variation based on the prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the surface condition of the molded element was not specifically mentioned. Instead, in the molded element, a roughened portion can be provided on the surface on the redistribution layer side.

[0173] Figure 16 This is a cross-sectional view showing the state of the sealed resin body 45 after molding. Figure 17 This is a cross-sectional view showing the structure of the element package 40 in the semiconductor device 20 of this embodiment. Figure 16 and Figure 17 and Figure 7 correspond. Figure 17 For convenience, the redistribution layer 42 has been omitted.

[0174] like Figure 16As shown, when the sealing resin body 45 is formed such that at least the edge portion 411d of the upper surface of the protective film 411 is covered, a process is performed to cut the sealing resin body 45 from the side of surface 45a. For example, a laser is irradiated towards the side of surface 45a. As a result, the sealing resin body 45 on the protective film 411 is cut away. Furthermore, a laser is irradiated towards the protective film 411 and the sealing resin body 45 in such a way that at least the edge portion 411d of the upper surface of the protective film 411 is substantially coplanar with at least one surface 45a of the sealing resin body 45.

[0175] Therefore, as Figure 17 As shown, a roughened portion 47 is formed at least at the edge 411d and the surface 45a of the sealing resin body 45 on the upper surface of the protective film 411 and the surface 45a of the sealing resin body 45. The molded element has the roughened portion 47 on the surface on the side of the redistribution layer 42. The roughened portion 47 is continuously formed from the edge 411d of the protective film 411 to the surface 45a of the sealing resin body 45. The edge 411d of the protective film 411 and the surface 45a of the sealing resin body 45 are connected substantially coplanarly in a roughened state. In this embodiment, the sealing resin body 45 also has the same roughened portion 47 on the surface 45a of the portion other than the sealing resin body 45S. The other structures are the same as those described in the prior embodiments.

[0176] <Summary of Implementation Method 5>

[0177] In this embodiment, in a plan view, the upper surface of the protective film 411 and one side 45a of the sealing resin body 45S are continuously roughened across the boundary between the element region 412 and the scribing region 413. Even if a non-flat structure with roughened portions 47 is made, the same effect as the structure described in the prior embodiment can be achieved. Furthermore, since the surface roughened portions 47 are present, the adhesion between the molded element and the redistribution layer 42 can be improved.

[0178] <Variation Example>

[0179] The method of forming roughened part 47 is not limited to laser irradiation.

[0180] like Figure 18 As shown, the roughened portion 47 of this embodiment can be compared with that of the prior embodiment. Figure 10The structure shown is as follows. The sealing resin body 45 is positioned such that one side 45a of the sealing resin body 45S is lower than the edge 411d. The roughening portion 47 is continuously formed from the protective film 411 to one side 45a of the sealing resin body 45S. The roughening portion 47 is also formed on the side 411c of the protective film 411, and the edge 411d, the upper part of the side 411c, and one side 45a are continuously roughened. By irradiation of the protective film 411 with a laser, the slope of the upper part of the side 410c becomes gentle. As a result, the flatness of the redistribution layer 42 can be improved near the boundary between the component region 412 and the scribing region 413.

[0181] (Sixth Embodiment)

[0182] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the flatness of the redistribution layer is improved by providing insulating portions on the scribed areas. Alternatively, it is also possible to prevent step differences from occurring.

[0183] Figure 19 This is a cross-sectional view showing the structure of the element package 40 in the semiconductor device 20 of this embodiment. Figure 19 Will Figure 6 The area VII shown is magnified to the pad 41P side. That is, it is... Figure 7 The diagram extends towards pad 41P. Figure 19 The drain electrode 41D and electrode protection element 46 are omitted from the diagram. For convenience, the redistribution layer 42 is shown flatly around the top of the pad 41P.

[0184] like Figure 19 As shown, semiconductor element 41 does not have the protective film 411 shown in the previous embodiment. The insulator 43 of the redistribution layer 42 is made of polyimide. The insulating film 431 constituting the first layer of the insulator 43 functions as the protective film 411. The insulating film 431 covers the periphery of the pad 41P. The pad 41P is exposed from the opening 431b of the insulating film 431. Although not shown in the figure, the insulating film 431 covers the periphery of the source electrode 41S. The source electrode 41S is exposed from the opening 431a of the insulating film 431.

[0185] The insulating film 431 covers one side 410a of the semiconductor substrate 410, excluding the electrode forming portion. Within side 410a, the insulating film 431 also covers the element region 412, the scribing region 413, and their boundary portions. One side 45a of the sealing resin body 45 is substantially coplanar with one side 410a of the semiconductor substrate 410. The sealing resin body 45 contacts (closely contacts) only one side 410c of the surface of the semiconductor substrate 410. The sealing resin body 45 is in close contact with the entire side 410c. Other than this, the structure is the same as that described in the prior embodiment.

[0186] <Summary of Implementation Method 6>

[0187] As described above, in this embodiment, the protective film 411 is excluded from the semiconductor element 41. Therefore, the step structure between the upper surface of the protective film 411 and one side 410a of the scribing region 413 is not formed. During the molding of the sealing resin body 45, no gaps are created for resin to enter the scribing region 413. Consequently, the insulator 43 of the redistribution layer 42 contacts one side 410a of the semiconductor substrate 410 in the range from the element region 412 to the scribing region 413. That is, the redistribution layer 42 is substantially flat around the periphery directly above the boundary between the element region 412 and the scribing region 413. Therefore, the flatness of the redistribution layer 42 can be effectively improved around the periphery directly above the boundary between the element region 412 and the scribing region 413. Since the protective film 411 is excluded, the improved flatness of the redistribution layer 42 can be achieved with a simple structure.

[0188] In this embodiment, one side 410a of the semiconductor substrate 410 is connected to one side 45a of the sealing resin body 45 in a substantially coplanar manner. As a result, the flatness of the redistribution layer 42 can also be improved around the edge directly above the end of one side 410a of the semiconductor substrate 410.

[0189] In this embodiment, the signal wiring 44P, which is connected to the pad 41P of the semiconductor element 41, extends across the boundary between the element region 412 and the scribing region 413 in a plan view. However, by removing the protective film 411, thinning or breakage of the signal wiring 44P can be suppressed around the periphery directly above the boundary. This simplifies the connection structure by eliminating bonding wires and improves the reliability of the electrical connection between the pad 41P and the signal terminal 72. By eliminating bonding wires, lead deformation and breakage do not occur during the molding of the sealing resin body 30.

[0190] In this embodiment, a MOSFET 11, which is a power switching element, is formed in the semiconductor element 41. The semiconductor element 41 constitutes an inverter 6 as a power conversion circuit. Since the insulator 43 of the redistribution layer 42 functions as a protective film 411, the step difference caused by the protective film 411 as described above is not generated. As a result, the flatness of the redistribution layer 42 can be improved.

[0191] (Seventh Embodiment)

[0192] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, a sealing resin body is actively disposed on the scribing area. Alternatively, the sealing resin body on the scribing area may be removed.

[0193] The sealing resin 45 disposed on the scribing area 413 may crack or fall off as resin flash. In this embodiment, the sealing resin 45 on the scribing area 413 is cut away by means of laser irradiation or the like. Accordingly, the surrounding protective film 411 and a portion of the sealing resin 45 outside the scribing area 413 are also removed.

[0194] Specifically, laser light is irradiated from one side 45a of the sealing resin body 45 on the scribing region 413 and the sealing resin body 45 opposite to that on the scribing region 413 across the end of the semiconductor substrate 410. In this way, laser light is irradiated into a predetermined area across the end of the semiconductor substrate 410, removing the sealing resin body 45. Furthermore, laser light is irradiated into at least a portion of the side surface 411c and edge 411d of the protective film 411.

[0195] Figure 20 This is a cross-sectional view showing the structure of the element package 40 in the semiconductor device 20 of this embodiment. Figure 20 and Figure 10 correspond. Figure 20 In, with Figure 10 In contrast, the sealing resin body is extended to the 45th side. Figure 20 The image shows the state after the processing has been removed.

[0196] On one side 410a of the semiconductor substrate 410, the sealing resin 45 on the scribing region 413 is completely removed. The sealing resin 45 is not positioned overlapping the semiconductor substrate 410 in the plan view. A roughened portion 47 is formed on one side 410a of the scribing region 413 by laser irradiation. The protective film 411 becomes a gently tapered shape compared to before irradiation by laser irradiation. The protective film 411 may also have a roughened portion 47 on the laser-irradiated surface. For example, a roughened portion 47 may also be present on the side 411c.

[0197] With reference to the end (side surface 410c) of the semiconductor substrate 410, the sealing resin 45 on the opposite side of the scribing region 413 is also removed in the same manner as on the scribing region 413. The sealing resin 45 has a recess 45c formed at the end on the semiconductor element 41 side in one side surface 45a. The bottom surface of the recess 45c is substantially coplanar with one side surface 410a of the semiconductor substrate 410. A roughened portion 47 is formed on the bottom surface. The side surface of the recess 45c is tapered. The sealing resin 45 may also have a roughened portion 47 on the side surface of the recess 45c.

[0198] At least the edge 411d of the upper surface of the protective film 411 is in the same position in the Z direction as one side 45a of the sealing resin body 45, excluding the wall surface of the recess 45c. The side surface 411c of the protective film 411, the scribed area 413 of one side 410a of the semiconductor substrate 410, and the recess 45c of the sealing resin body 45 are bowl-shaped.

[0199] <Summary of Implementation Method 7>

[0200] In this embodiment, the sealing resin body 45 on the scribing area 413 is removed, thus suppressing the occurrence of resin flash cracking and peeling. Furthermore, no filler 450 is disposed in the area opposite the redistribution layer 42 and the scribing area 413. As described in the previous embodiment, this suppresses defects in the redistribution layer 42 caused by the filler 450.

[0201] In this embodiment, by removing the sealing resin body 45, one side 410a of the semiconductor substrate 410 and one side 45a of the sealing resin body 45 are connected substantially coplanarly in the component package 40. As a result, the flatness of the redistribution layer 42 can be improved around the edge directly above the end of one side 410a of the semiconductor substrate 410.

[0202] In this embodiment, the slope of the side surface 411c of the protective film 411 becomes gentler compared to before processing by removing the processing. As a result, compared to the sharp slope before processing, the flatness of the redistribution layer 42 can be improved near the boundary between the component region 412 and the scribing region 413.

[0203] In this embodiment, roughened portions 47 are formed on the semiconductor substrate 410 and the sealing resin body 45. This improves the adhesion between the molded element and the redistribution layer 42. For example, it can suppress the peeling of the insulator 43 from the molded element.

[0204] An example of removal processing by laser irradiation is shown, but it is not limited to this. Etching, etc., can also be used.

[0205] (Eighth Embodiment)

[0206] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, a portion of the sealing resin body is removed after molding. Alternatively, a support substrate may be used during the molding of the sealing resin body.

[0207] Figure 21 This is a cross-sectional view showing the manufacturing method of the component package 40 in the semiconductor device 20 of this embodiment. Figure 21 and Figure 8 Corresponding. For example, Figure 21 As shown, the support substrate 100 has a base 100a and a protrusion 100b protruding from the base 100a toward the semiconductor element 41. A portion of the protrusion 100b may be made of an adhesive layer, or the entire protrusion 100b may be made of an adhesive layer.

[0208] The base 100a contacts the upper surface of the protective film 411, including the edge 411d. The front end face of the protrusion 100b is a surface substantially parallel to the XY plane. A portion of the front end face of the protrusion 100b contacts a scribe region 413 in one side 410a of the semiconductor substrate 410. The protrusion 100b contacts at least a portion of the scribe region 413 extending from the end of one side 410a. The protrusion 100b contacts the scribe region 413 without gaps over its entire circumference. The remaining portion of the front end face of the protrusion 100b is disposed on the forming region side of the sealing resin body 45 to define one side 45a of the sealing resin body 45.

[0209] <Summary of Implementation Method 8>

[0210] In this embodiment, a support substrate 100 with protrusions 100b is used. As described above, the protrusions 100b contact the scribing region 413 without gaps throughout the entire circumference. Therefore, during the molding of the sealing resin body 45, resin leakage in the scribing region 413 can be suppressed. Thus, the occurrence of resin flash cracking, peeling, etc., can be suppressed. Furthermore, since no filler 450 is disposed in the area opposite to the redistribution layer 42 and the scribing region 413, defects in the redistribution layer 42 due to filler 450 can be suppressed.

[0211] In this embodiment, the front end face of the protrusion 100b is flat, and a portion of the front end face defines one side 45a of the sealing resin body 45. Thus, the formed sealing resin body 45 has one side 45a that is substantially coplanar with the scribed region 413. Consequently, the flatness of the redistribution layer 42 can be improved in the periphery directly above the end of the semiconductor substrate 410's side 410a.

[0212] (Other implementation methods)

[0213] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and modifications made by those skilled in the art based on them. For example, the disclosure is not limited to combinations of components and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional portions that can be added to the embodiments. The disclosure includes forms after omitting components and / or elements of the embodiments. The disclosure includes substitutions or combinations of components and / or elements between one embodiment and other embodiments. The scope of the disclosed technology is not limited to the description of the embodiments. Some of the scope of the disclosed technology is indicated by the description of the claims, and it should be understood that this includes all modifications within the meaning and scope equivalent to the description of the claims.

[0214] The disclosure in the specification and drawings is not limited to the claims. The disclosure includes the technical ideas described in the claims, and thus relates to a wider and more diverse range of technical ideas than those described in the claims. Therefore, it is not limited to the claims; diverse technical ideas can be extracted from the disclosure in the specification and drawings.

[0215] In the context of this specification, the term "and / or" includes any and all combinations relating to one or more of the associated listed items.

[0216] The spatially relative terms "inner," "outer," "further," "lower," "upper," and "higher," etc., are used here to facilitate the description of the relationship between an element or feature and other elements or features, as illustrated in the figures. In addition to the orientation depicted in the figures, the spatially relative terms can also imply different orientations of the device in use or operation. For example, if the device in the figure is inverted, the element described as "lower" or "directly below" other elements or features faces "upper" of those other elements or features. Therefore, the term "lower" can encompass both upper and lower orientations. The device may also face other directions (rotating 90 degrees or other directions), and the spatially relative descriptions used in this specification are interpreted accordingly.

[0217] The vehicle's drive system 1 is not limited to the structure described above. For example, an example with one electric generator 3 is shown, but it is not limited to this. Multiple electric generators may also be included. An example of a power conversion device 4 having an inverter 6 as a power conversion circuit is shown, but it is not limited to this. For example, it may be configured to have multiple inverters. It may also be configured to have at least one inverter and a converter. It may also only have a converter.

[0218] The example shown is of a semiconductor device 20 having only one semiconductor element 41 constituting one arm, but it is not limited thereto. Multiple semiconductor elements 41 constituting an upper and lower arm circuit 9 of one phase may also be provided. Multiple semiconductor elements 41 constituting upper and lower arm circuits 9 of multiple phases may also be provided. In the case where multiple semiconductor elements 41 are connected in parallel to form one arm, for example, multiple semiconductor elements 41 may be arranged in a single component package 40.

[0219] An example of semiconductor element 41 having MOSFET 11 as a switching element is shown, but it is not limited to this. For example, IGBT can also be used.

[0220] An example is shown where a semiconductor element 41 has a source electrode 41S formed on one side of a semiconductor substrate 410 and a drain electrode 41D formed on the back side as main electrodes, but it is not limited to this. It is also possible to have a main electrode on only one side.

[0221] An example is shown where the terminal portion 440P of the signal wiring 44P is exposed on the back side 42b of the redistribution layer 42, but this is not the only example. The formation area of ​​the sealing resin body 45 may also be limited so that the terminal portion 440P is exposed from the unsealed portion of the mounting surface 42a.

[0222] An example is shown where the back surfaces 50b and 60b of the heat dissipation components 50 and 60 are exposed from the sealing resin body 30, but this is not the only example shown. It is also possible to construct a structure in which at least one of the back surfaces 50b and 60b is covered by the sealing resin body 30. It is also possible to construct a structure in which at least one of the back surfaces 50b and 60b is covered by an insulating component (not shown) other than the sealing resin body 30. An example is shown where the semiconductor device 20 includes the sealing resin body 30, but this is not the only example shown. It is also possible to construct a structure without the sealing resin body 30. The semiconductor device 20 may at least include a component package 40.

Claims

1. A component package, characterized in that, have: A semiconductor device includes: a semiconductor substrate having a device region for forming the device and a scribing region provided within a predetermined range from the end of the substrate and surrounding the device region; a main electrode and a pad formed on one side of the semiconductor substrate; and a protective film disposed on the device region in the one side of the substrate such that the main electrode and the pad are exposed. A sealing resin body is used to seal the semiconductor device in a manner that exposes the main electrode and the pad. A rewiring layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor element; and An insulating portion is disposed on the scribed area in one side of the semiconductor element such that it has a height not exceeding the height of the outer peripheral edge of the upper surface of the protective film on the element area. The aforementioned redistribution layer is disposed within the range from the aforementioned protective film to the aforementioned insulating portion; The aforementioned insulating portion is the part of the aforementioned sealing resin body disposed on the aforementioned marked area; The aforementioned sealing resin body is in contact with the side of the aforementioned protective film.

2. The component package as described in claim 1, characterized in that, The insulating portion is arranged in a coplanar manner with respect to the outer peripheral edge portion of the protective film.

3. The component package as described in claim 1, characterized in that, The aforementioned sealing resin body contains filler; The particle size of the filler is greater than the step difference between the outer peripheral edge of the protective film and the scribing area on the surface.

4. The component package as described in claim 1, characterized in that, In a plan view along the thickness direction of the semiconductor substrate, the outer peripheral edge of the protective film and the upper surface of the sealing resin are continuously roughened across the boundary between the element region and the scribing region.

5. The component package as described in claim 1 or 2, characterized in that, The above-mentioned components are power-type switching components.

6. The component package as described in claim 1 or 2, characterized in that, The above wiring includes signal wiring that connects to the above pads; In a plan view along the thickness of the semiconductor substrate, the signal wiring extends across the boundary between the component region and the scribed region.

7. A component package, characterized in that, have: A semiconductor device includes: a semiconductor substrate having a device region for forming the device and a scribing region provided within a predetermined range from the end of the substrate and surrounding the device region; a main electrode and a pad formed on one side of the semiconductor substrate; and a protective film disposed on the device region in the one side of the substrate such that the main electrode and the pad are exposed. A sealing resin body is used to seal the semiconductor device in a manner that exposes the main electrode and the pad. A rewiring layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor element; and An insulating portion is disposed on the scribed area in one side of the semiconductor element such that it has a height not exceeding the height of the outer peripheral edge of the upper surface of the protective film on the element area. The aforementioned redistribution layer is disposed within the range from the aforementioned protective film to the aforementioned insulating portion; The aforementioned insulating portion is a resin film that is provided differently from the aforementioned sealing resin body and the aforementioned protective film; The resin film covers the marked area on one side and is in contact with the side of the protective film.

8. The component package as described in claim 7, characterized in that, The insulating portion is arranged in a coplanar manner with respect to the outer peripheral edge portion of the protective film.

9. The component package as described in claim 7, characterized in that, The above-mentioned components are power-type switching components.

10. The component package as described in claim 7, characterized in that, The above wiring includes signal wiring that connects to the above pads; In a plan view along the thickness of the semiconductor substrate, the signal wiring extends across the boundary between the component region and the scribed region.

11. A semiconductor device, characterized in that, have: Component packaging; Heat dissipation components; and signal terminal; The above-mentioned component package includes: A semiconductor device includes: a semiconductor substrate having a device region for forming the device and a scribing region provided within a predetermined range from the end of the substrate and surrounding the device region; a main electrode and a pad formed on one side of the semiconductor substrate; and a protective film disposed on the device region in the one side of the substrate such that the main electrode and the pad are exposed. A sealing resin body is used to seal the semiconductor device in a manner that exposes the main electrode and the pad. A rewiring layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor element; and An insulating portion is disposed on the scribed area in one side of the semiconductor element such that it has a height not exceeding the height of the outer peripheral edge of the upper surface of the protective film on the element area. The aforementioned redistribution layer is disposed within the range from the aforementioned protective film to the aforementioned insulating portion; The above wiring includes signal wiring that connects to the above pads; In a plan view along the thickness of the semiconductor substrate, the signal wiring extends across the boundary between the component region and the scribed region. The aforementioned heat dissipation component is configured such that the aforementioned semiconductor element is sandwiched in the aforementioned plate thickness direction; The aforementioned signal terminals are coupled to the terminal portions exposed from the insulator in the aforementioned signal wiring, and are electrically connected to the corresponding pads via the aforementioned signal wiring. The aforementioned insulating portion is the part of the aforementioned sealing resin body disposed on the aforementioned marked area; The aforementioned sealing resin body is in contact with the side of the aforementioned protective film.

12. A semiconductor device, characterized in that, have: Component packaging; Heat dissipation components; and signal terminal; The above-mentioned component package includes: A semiconductor device includes: a semiconductor substrate having a device region for forming the device and a scribing region provided within a predetermined range from the end of the substrate and surrounding the device region; a main electrode and a pad formed on one side of the semiconductor substrate; and a protective film disposed on the device region in the one side of the substrate such that the main electrode and the pad are exposed. A sealing resin body is used to seal the semiconductor device in a manner that exposes the main electrode and the pad. A rewiring layer having an insulator and wiring disposed on the insulator, disposed on one side relative to the semiconductor element; and An insulating portion is disposed on the scribed area in one side of the semiconductor element such that it has a height not exceeding the height of the outer peripheral edge of the upper surface of the protective film on the element area. The aforementioned redistribution layer is disposed within the range from the aforementioned protective film to the aforementioned insulating portion; The above wiring includes signal wiring that connects to the above pads; In a plan view along the thickness of the semiconductor substrate, the signal wiring extends across the boundary between the component region and the scribed region. The aforementioned heat dissipation component is configured such that the aforementioned semiconductor element is sandwiched in the aforementioned plate thickness direction; The aforementioned signal terminals are coupled to the terminal portions exposed from the insulator in the aforementioned signal wiring, and are electrically connected to the corresponding pads via the aforementioned signal wiring. The aforementioned insulating portion is a resin film that is provided differently from the aforementioned sealing resin body and the aforementioned protective film; The resin film covers the marked area on one side and is in contact with the side of the protective film.

Images