Current sensing in switching electronics

Abstract

Embodiments of the present disclosure relate to current sensing in switching electronics. The present disclosure provides a circuit including a switching transistor having a control terminal configured to receive a control signal and having a current path through the terminal. The switching transistor becomes conductive in response to the control signal having a first value. The current path through the switching transistor provides a current path between two nodes. In a non-conductive state, a voltage drop stress exists across the switching transistor. The circuit includes a sensing transistor and a scaled replica coupled to the switching transistor. The sensing transistor has a sense current. The sense current is representative of the current of the switching transistor. The circuit includes a coupling circuit arrangement configured to apply a voltage drop stress on the sensing transistor in response to the switching transistor being non-conductive. In the non-conductive state, the voltage drop stress is replicated between the switching transistor and the sensing transistor.

Description

Technical Field

[0001] This disclosure relates to circuitry for sensing current. For example, one or more embodiments may be adapted to measure the current flowing through an inductive load in an electronic device, such as a switching (or alternating) converter.

[0002] One or more embodiments can be used in applications such as the automotive industry, where maintaining operational accuracy throughout the lifespan of electronic devices is an ideal feature. Background Technology

[0003] Power field-effect transistors (FETs) are currently used in matched sensing / power structures.

[0004] In this context, accurately sensing the current in the inductive load of a switching converter circuit can involve a sensing transistor, which is a miniature replica of the switching converter's (e.g., high / low side) power transistor.

[0005] Therefore, current sensing can utilize precise relationships between the parameters of the sensing transistor and the power transistor, such as the same on-resistance value or a specific ratio between corresponding on-resistance values.

[0006] The power transistor structure may be affected by stress conditions in the task profile: the task profile describes the loads and stresses that the product will face in actual use.

[0007] Variations in temperature, temperature profiles, vibration, and working conditions in the electromechanical field or other environmental factors are examples of such loads and stresses.

[0008] These conditions can cause the electrical parameters in power transistors to degrade (i.e., the values ​​of these electrical parameters age over time).

[0009] This may be due to various phenomena, such as high temperature reverse bias (HTRB) and hot carrier injection (HCI), which exhibit different (and sometimes even opposite) behaviors in terms of temperature, current, and voltage application curves.

[0010] The aging of parameters in the power transistor is not reflected in the associated sensing transistor, which may lead to a mismatch in the on-resistance Ron ratio and a mismatch in the threshold voltage Vth between the power transistor and the sensing transistor, resulting in a loss of accuracy in current sensing.

[0011] This could have (highly) adverse consequences, especially for vehicle power circuits. Summary of the Invention

[0012] One or more embodiments provide a circuit including at least one power switch having an associated sensing transistor, the power switch being configured to allow current to flow through the switch during a first time interval and to be subjected to electrical stress during a second time interval, wherein the circuit includes a coupling circuit means configured to apply the electrical stress to the sensing transistor during the second time interval and during the first time interval, the circuit serving as an example of such a circuit.

[0013] One or more embodiments may relate to a corresponding switching electronic converter (e.g., an onboard telematics control unit).

[0014] A converter circuit that includes at least one pair of matched power / sensing transistors (e.g., n-MOSFETs) can serve as an example of such a circuit.

[0015] One or more embodiments help to obtain a ratio between the on-resistance value Ron being stable over time and not changing due to aging of the converter device.

[0016] One or more embodiments contribute to achieving very high current accuracy performance in current-controlled PWM drivers throughout the system's lifespan.

[0017] One or more embodiments can improve silicon footprint, for example, by reducing the impact of silicon area on footprint.

[0018] One or more embodiments help to relax automotive design restrictions, thereby increasing the gross margin of automotive applications accordingly.

[0019] One or more embodiments may utilize relatively simple and cost-effective arrangements, such as diodes and switches.

[0020] In one or more embodiments, the sensitivity to HCI and HTRB phenomena in a high-voltage matched sensing / power structure may be reduced due to different voltage and / or current distributions applied during the system lifetime.

[0021] In one or more embodiments, the mismatch between the sensed / supply current mirror during PWM activity can be bypassed, for example, by using diodes and switches in a current sensing architecture.

[0022] One or more embodiments may have a negligible impact on control system complexity and silicon area. Attached Figure Description

[0023] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0024] Figure 1 This is an example circuit diagram of a converter circuit.

[0025] Figure 2 yes Figure 1 Timing diagram of converter circuit signals.

[0026] Figure 3 This is a circuit diagram example of one or more embodiments.

[0027] Figure 4 It is a timing diagram of signals in one or more embodiments.

[0028] Figure 5 yes Figure 3 The circuit diagram examples of one or more alternative embodiments shown are as follows:

[0029] Figure 6 This is a circuit diagram example of one or more embodiments.

[0030] Figure 7 yes Figure 6 The circuit diagram examples of one or more alternative embodiments shown are as follows:

[0031] Figure 8 This is a circuit diagram example of one or more embodiments.

[0032] Figure 9 It is based on Figure 8 Timing diagrams of signals from one or more embodiments,

[0033] Figure 10 This is a system example diagram according to one or more embodiments. Detailed Implementation

[0034] In the following description, one or more specific details are set forth to provide a thorough understanding of the exemplary embodiments described herein. Embodiments may be obtained without one or more of these specific details, or may be obtained through other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in detail so as not to obscure certain aspects of the embodiments.

[0035] Within the framework of this description, references to "one embodiment" or "a specific embodiment" are intended to indicate that a particular configuration, structure, or feature described in relation to that embodiment is included in at least one specific embodiment. Therefore, phrases such as "in one embodiment" or "in one embodiment" that may appear at one or more points in this description do not necessarily refer to the same embodiment.

[0036] Furthermore, a particular conformation, structure, or feature may be combined in any suitable manner in one or more embodiments.

[0037] The attached diagram is simplified and not to scale.

[0038] Throughout the drawing, similar parts or components are represented by similar reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0039] The references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0040] For simplicity, the same reference numerals may be used in the following detailed description to designate nodes / lines in the circuit and the signals that may appear on those nodes or lines.

[0041] like Figure 1 As shown, the switch (or switch converter) circuit 10 includes:

[0042] Power node VI is configured to receive a DC power supply voltage (e.g., voltage level V) from ground PGND. S =12V, from Figure 1 (Provided by an invisible battery)

[0043] First switching transistor Q LS (For example, a metal-oxide-semiconductor (MOS) field-effect transistor (FET), such as an n-channel or p-channel MOSFET) and a second switching transistor Q. HS (e.g., a FET used as a recirculating diode), a switching transistor Q LS Q HS Coupled between the two (e.g., connected to the recirculating diode Q) HS The first switching transistor Q of the anode LS The drain node VO), and has via the first Q LS Second Q HS The switching node VO in the middle of the switching transistor is connected in series in the corresponding current path between the input node VI and ground PGND. The switching node VO is configured to be coupled to a load with a reference voltage (e.g., ground or VI) to provide the output voltage.

[0044] An inductor component L, such as a coil inductor having an inductance L and a resistance R, has one end coupled (e.g., directly coupled) to a switching node VO and the other end coupled to a power supply node VI.

[0045] For simplicity, the following discussion of the basic principles of one or more embodiments will primarily refer to the arrangement of the inductor assembly L coupled between the switching node VO and the power supply node VI. It should be understood that this is purely exemplary and has no limitations.

[0046] For example, in another case, the inductive load L is coupled between the switching node VO and ground, while the load Z... L It is coupled between the input node VI and the output node VO.

[0047] like Figure 1 As shown, the switch converter 10 also includes a coupling to the first Q. LS The transistor's control node (e.g., low-voltage side) driver 11, configured to direct power to the first switching transistor Q... LS The control node provides control / drive signals X LS .

[0048] like Figure 1 As shown, the driver signal X LS Based on the control signal X received from the control circuit 12 configured to operate the converter circuit 10, such as the pulse width modulation (PWM) control signal X generated in a known manner.

[0049] In one or more alternative configurations, the driver circuit 11 is configured to directly generate a first control signal X to the driver circuit 11. LS This allows the first switching transistor Q to be switched between a first (e.g., conductive or ON) state and a second (e.g., non-conductive or OFF) state. LS .

[0050] like Figure 1 As shown, converter 10 also includes a first switching transistor Q. LS Associated sensing transistor M LS And it has a common control node associated with it, sensing transistor M LS In the first (e.g., drain) sensing node V MS and coupled to ground PGND and with transistor Q LS There is a current path between the corresponding nodes and the second (e.g., the source) node.

[0051] exist Figure 1 In one or more of the cases shown, the sensing transistor M LS It is the first switching transistor Q LS A smaller copy. For example, a sensing transistor M. LS This includes the corresponding junction area, which is a fraction (e.g., 1 / N times) of the junction area of ​​the first switching transistor QS associated with it.

[0052] like Figure 1 As shown, circuit 10 also includes a buffer circuit 13BS, such as an op-amp voltage follower known per se, comprising (e.g., operational) amplifier circuit 13 having a corresponding first (e.g., non-inverting) input node coupled to the switching node VO, coupled to the sensing transistor M. LS The first sensing node V MSThe second input node (e.g., in reverse) and the output node coupled to the buffer switch BS, the buffer circuit 13 is configured to apply an output voltage at its output node that replicates the voltage at its first input node.

[0053] like Figure 1 As shown, the buffer circuit 13BS is biased to a bias voltage V lower than the supply voltage level VI. B (e.g. V) B =5V and V S =12V). Therefore, if the first input node BS of the buffer device 13 is floated at the open-circuit voltage (the maximum voltage level that the output node of the buffer circuit 13 can replicate), then BS is limited to the bias level V. B .

[0054] like Figure 2 As shown, under the initial conditions before the first time point T1, the control signal X provided to the driver circuit 11 has a first value (e.g., higher than the value of switch Q). LS The gate-source threshold V of a transistor GS The voltage level (e.g., 5V) is used to switch transistor Q. LS It is in the ON state, and the current I QLS A steady current I flows through. QLS Equal to the current flowing through the inductor component L (e.g., I QLS =I L ).

[0055] like Figure 2 As shown, before the first time point T1, it is still in the initial state, serving as the first switching transistor Q. LS Medium current I QLS The sensing current I of the reduced copy MS In the relevant sensing transistor M LS Medium-stability flow (e.g., I) MS =I QLS / N=I L / N).

[0056] like Figure 1 and Figure 2 As shown, in the initial stage before the first time point T1, the buffer circuit 13, BS holds the sensing transistor M. LS Sensing node V MS The voltage level is equal to the voltage level at the switching node VO, for example, VO = 0.7V.

[0057] like Figure 2 As shown, under exemplary initial conditions before the first time point T1, the switching transistor Q... LS and associated sensing transistor M LSBoth terminals experience the same electrical operating conditions and voltage drop stress.

[0058] like Figure 1 As shown, the buffer circuit 13 is optionally coupled to an analog-to-digital (A / D) converter 14, which is configured to input the first sensing transistor M... LS The sensed current signal I flowing in MS Digitalization.

[0059] For example, A / D converters 14A and 14B provide a digital signal D, indicating the initial stage of switching transistor Q. LS Current I flowing in MS This represents the current intensity in coil L. For example, this digital signal D can be fed back to control circuit 12 to create a feedback loop, thereby adjusting the control signal accordingly, for example, in a manner known per se.

[0060] It is worth noting that the sensing current I MS The digitization behavior is purely exemplary and has no limitations. For example, it is suitable for processing sensed current signals I. MS Mixed digital / analog or purely analog circuits can be coupled to sensing transistor M LS .

[0061] like Figure 2 As shown, at the first time T1, the control signal X asserts with a second value (e.g., X = 0V); in response to this, the switching transistor Q... LS It begins to transition from the on state to the off state, thus reaching the off state at time T2.

[0062] like Figure 2 As shown, during the on / off state transition of the time interval T1-T2, the switching transistor Q is... LS The current path is non-conductive, therefore the first current value I QLS From the coil current value I L Reduced to zero, while the recirculating diode Q HS The second current value I in QHS Increasing from zero to the coil current value I L .

[0063] like Figure 1 and Figure 2 As shown, due to the current I QLS With the input node BS of buffer stage 13 remaining floating at zero, the signal is sent to the sensing transistor M. LS Apply a voltage limited by its bias voltage level (e.g., V). B =5V), while the switching transistor Q LS The voltage is the switching node VO (for example, VO = VS + 0.7V).

[0064] like Figure 2 As shown, due to buffer 13, the sensed current I MS If the voltage becomes zero, for example, during the on / off transition in time interval T1-T2, BS cannot track the output voltage VO at a voltage level higher than the bias voltage VB.

[0065] like Figure 2 As shown, the HCI phenomenon affects the switching transistor Q over time. LS and sensing transistor M LS The effects differ because each component experiences different operating conditions and corresponding electrical stimulation.

[0066] like Figure 2 As shown, at the second time T2, the switching transistor Q... LS The system reaches a stable OFF state and maintains it, and as long as the control signal X has a second value (e.g., X = 0V), that is, until the third time T3, the control signal X asserts with a first value (e.g., X = 5V).

[0067] like Figure 2 As shown, during the rest period T2-T3, the switching transistor Q... LS Current signal I in QLS The current I flowing into the inductive load L is zero. L Pull the voltage at the switching node VO to the power supply voltage level V. S Above, the pull-up amount is equal to the Q value across the diode. HS voltage drop V QHS For example, 12.7 volts.

[0068] like Figure 2 As shown, during the rest phase T2-T3, the sensing transistor M LS Sensing node V MS bias voltage V B It floats in the surrounding high impedance, for example, due to the limited rated voltage of the buffer device 13BS.

[0069] like Figure 2 As shown, due to the different voltage stresses VO, during the steady-state time interval T2-T3, the two transistors Q LS M LS It will still experience V MS Similarly, these imbalances can occur in the HTRB phenomenon, affecting the two electrical components and causing a mismatch between them.

[0070] like Figure 2 As shown, in the third time interval T3, the control signal X LS Assuming the first value, therefore the switching transistor Q...LS Initiate the reverse transition from the OFF state to the ON state, thereby generating a mirror-symmetric operating condition related to the transition in the time interval T1-T2.

[0071] like Figure 1 and Figure 2 As shown, Figure 1 As shown, the switching transistor Q of circuit 10 LS and associated sensing transistor M LS Different electrical stresses under different operating conditions may cause the sensing transistor M to be affected. LS Accurately replicate the switching transistor Q LS The current sensing capability is degraded, thereby reducing the accuracy of the current sensing signal D.

[0072] HCI and HTRB degradation in power transistors is highly relevant to vehicle braking and transmission applications, where less than 1% current error is permissible in terms of setpoints after the life cycle.

[0073] like Figure 3 As shown, according to this disclosure, the improved converter circuit 30 includes a sensing transistor M LS Circuits 13, BS, S1, S2, S3, and S4 are coupled to at least one switching transistor Q. LS The coupling circuit devices 13, BS, S1, and S4 are configured to respond to at least one switching transistor Q. LS It is switched to the OFF state, while the sensing transistor M LS Applying a voltage drop stress, wherein the response is to at least one switching transistor Q LS When switched to the OFF state, the voltage drop stress crosses at least one switching transistor Q. LS Copy and cross the sensing transistor M LS copy.

[0074] like Figure 3 As shown, the coupling circuit devices 13, BS, S1, S2, S3, and S4 include a collection of buffer devices 13, BS, and switches S1, S2, S3, and S4 (e.g., implemented using MOS transistors, diodes, or back-to-back switches, which are known in themselves).

[0075] For simplicity, the basic principles of one or more embodiments will be discussed below with reference to the concept of the drive signal S used to operate the switches in the set of switches S1, S2, S3, and S4.

[0076] In one or more embodiments, such a drive signal S can be obtained based on other signals and is entirely optional. For example, it can be based on a control signal X. LS X HSObtain the drive signal S. As illustrated herein, in a purely exemplary and non-limiting scenario, for example, the drive signal S can be used as a control signal X via logic circuitry. LS X HS The combination of these can be obtained, optionally, with an indicator output node VO or at least one switching transistor Q. LS Q HS The monitoring signal (e.g., generated by an optional comparator circuit in a manner known per se) is obtained together with the voltage level at the control node that is higher or lower than a certain threshold.

[0077] For example, the set of switches S1, S2, S3, and S4 includes:

[0078] A first subset of switches S1, S3, and S4, when driven to a first (e.g., ON) state (e.g., in response to a respective drive signal S having a first value), is configured to conduct to couple the input node of amplifier 13 to the sensing node V. MS and the first sensing transistor M S And when a first subset of switches S1, S3, S4 is driven to a second (e.g., OFF) state (e.g., in response to a corresponding drive signal S with a first value), they are configured to be non-conductive to connect the input node of amplifier 13 to the first sensing transistor M. S Sensing node V MS Decoupling, as described below, and

[0079] The second subset S2 of the switch is configured to conduct when driven to a first (e.g., ON) state (e.g., in response to a corresponding drive signal S with a second value) to couple the sensing transistor M. LS Sensing node V MS and the first switching transistor Q LS The switching node VO, when driven to a second (e.g., OFF) state (e.g., in response to a corresponding drive signal S with a first value), is configured to be non-conductive to decouple the sensing transistor M. LS Sensing node V MS and the first switching transistor Q LS The switch node VO.

[0080] like Figure 3 As shown, the first subset of switches S1, S3, and S4 includes:

[0081] The first switch S1 is configured to selectively couple or decouple the switching node VO of amplifier 13 from the first input node (e.g., non-inverting).

[0082] The third switch S3 is configured to selectively couple the sensing node V of the first sensing transistor MS. MS(e.g., drain node) and the second input node of amplifier 13 (e.g., inverting node), and

[0083] The fourth switch S4 is configured to selectively couple the first sensing transistor M via switch BS. S Sensing node V MS And the output node of amplifier 13.

[0084] like Figure 3 As shown, the second subset of switches may include a second switch S2, configured to selectively connect the output node VO to the first sensing transistor M. LS (e.g., drain) sensing node V MS coupling.

[0085] In one or more embodiments, such as Figure 3 The arrangement 30 shown helps prevent mismatch, thereby eliminating the need for mismatch in the first switching transistor Q. LS and corresponding sensing M S Imbalance in voltage drop stress between transistors under any operating conditions (e.g., off state, on state, and state transition).

[0086] like Figure 3 and Figure 4 As shown, due to the function of the coupling circuit device, the sensing transistor M... LS Sensing current I MS The mirror image (mirror image ratio of 1 / N) flows into the first switching transistor Q. LS The corresponding current I QLS As a result, for example, in the sensing transistor M LS Sensing node V MS The voltage V detected at the location MS It has an amplitude and waveform that are essentially equal to the output voltage at the switching node VO.

[0087] like Figure 3 and Figure 4 As shown, under the initial conditions prior to T1, the control signal X has a first value (e.g., higher than that of switch Q). LS The gate-source threshold V of a transistor GS The voltage level (e.g., 5V) is used to switch transistor Q. LS It has a stable current I flowing through it QLS Current I QLS Equal to the current flowing through the inductor component L (e.g., I QLS =I L Simultaneously, the sensing current I MS Stable at the relevant sensing transistor M LS In the flow (e.g., I) MS =I QLS / N=IL / N); In this stage, the drive signal S of the switches in the coupling circuit devices 13, BS, S1, S2, S3, and S4 has a first value, so the first set of switches S1, S3, and S4 is turned on, and switch S2 in the second subset of switches is turned off (e.g., ...). Figure 4 As shown at the bottom, the first signal value represents the on state, and the second signal value represents the off state; as a result, the buffer 13BS causes the sensing transistor M to... LS Sensing node V MS Maintain a voltage level equal to the voltage level at the switching node VO.

[0088] like Figure 3 and Figure 4 As shown, at the first time T1, the control signal X of the switching transistor is asserted with a second value (e.g., X...). LS =0V), and the drive signal S asserts with a second value; in response to these events:

[0089] Switching transistor Q LS The process begins to transition from the on state to the off state, thus reaching the off state at the second time T2, and...

[0090] The second switch S2 is turned on, while the other switches S1, S3, and S4 are turned off, causing the switching node VO to be connected to the sensing node V. MS Buffer 13, BS decoupling, and sensing node V MS Coupled with the switching node VO.

[0091] like Figure 4 As shown, during the on / off state transition of the switching transistor Q in time interval T1-T2, LS and related sensing transistor M LS Apply the same pressure drop stress.

[0092] Therefore, even in Figure 4 Under the different operating conditions shown, the HCI phenomenon also affects the switching transistor Q in the same way over time. LS and sensing transistor M LS .

[0093] like Figure 3 and Figure 4 As shown, at the second time T2, the switching transistor Q... LS Achieving a stable OFF state and maintaining that state requires only the control signal X. LS Having a second value (e.g., X) LS =0V), that is, until the third time T3, the control signal X is asserted to be the first value (e.g., X = 0V). LS =5V).

[0094] like Figure 3 and Figure 4 As shown, during the rest phase T2-T3, the sensing node V of the sensing transistor... MS It is also pulled to the voltage level of the switching node VO by the inductive load L, for example, pulled to a level higher than the supply voltage level V. S The voltage across the recirculating diode Q is equal to the pull-up amount. HS voltage drop V QHS For example, 12.7 volts.

[0095] like Figure 4 As shown, during the stationary phase T2-T3, the limiting voltage rating of buffer circuit 13, BS does not affect the switch Q. LS And any of the sensing MS transistors.

[0096] Therefore, due to the aging effect of the two components obtained through the coupling circuit devices 13, BS, S1, S2, S3, S4 used in circuit 30 over time, the risk of one or more embodiments being exposed to mismatch between the two electrical components is reduced (ideally to zero risk).

[0097] like Figure 4 As shown, at the third time interval T3 of the control signal X asserted with the first value, the switching transistor Q is activated. LS The reverse transition from the off state to the on state begins (i.e., it is reached at time T4), thereby generating mirror-symmetric operating conditions corresponding to those operating conditions discussed with respect to transition T1-T2.

[0098] Specifically, at time T4, the first S1, the third S3, and the fourth S4 switches in the first subset of switches S1, S2, S3, and S4 conduct electricity based on a drive signal S with a second value, while the second switch S2 in the second set of switches selectively deconducts based on a drive signal S with a first value.

[0099] like Figure 4 As shown, the drive signal S is asserted with its first value only at the end of the further transition T3-T4, i.e., at the fourth time T4. Therefore, under any possible operating conditions, such as Figure 1 As shown, the switching transistor Q in the circuit LS and related sensing transistor M LS The same electrical stress is still applied.

[0100] In one or more alternative embodiments, the sensing transistor M LS The coupling circuitry can be arranged in different ways, but the operation is basically the same as described in the previous reference. Figure 4 The methods discussed are the same.

[0101] like Figure 5As shown, in the alternative circuit 50, for example:

[0102] Sensing transistor M LS A sensing node V is set up. MS The sensing node and the switching transistor Q LS The switching node VO is coupled, and the sensing transistor M is sensed. LS Another sensing node (e.g., a source node) is provided, which is coupled to a second (e.g., an inverting) node of amplifier 13 via a buffer switch BS, and

[0103] Buffer circuit 13, BS has a first node coupled to ground PGND and a sensing transistor M. LS The second node of another sensing node.

[0104] like Figure 5 As shown, for example:

[0105] Several switches in the first subset of switches S1, S3, and S4 can be reduced, for example, by reducing the number of sensing transistors M. LS The buffer switch BS is intermediated to another detection node as a switch S4.

[0106] The second switch S2 in the second subset of the switches is inserted into the input node of amplifier 13 in the buffer arrangement 13BS, such that when switch S2 is conductive, they are short-circuited to ground.

[0107] For example, such as Figure 5 The alternative embodiment shown can provide a further reduction in area footprint, while also improving the performance of the switching transistor Q. LS and its associated sensing transistor M LS It provides similar performance in terms of stress robustness.

[0108] exist Figure 6 In one or more embodiments shown, another alternative circuit arrangement 60 is envisioned, for example:

[0109] use Figure 3 The first switching transistor Q of the circuit 30 shown LS As a recirculating diode coupled between the switching node VO and ground PGND, and the first switching transistor Q LS It is connected in parallel with the inductor L coupled between the same nodes, and

[0110] The second switching transistor Q is driven using the control signal X received at its control node. HS .

[0111] exist Figure 6 In the alternative shown, the second sensing transistor M HS It is related to the second transistor QHS The associated second transistor Q HS A smaller copy, the second sensing transistor M HS A first node (e.g., a drain node) is arranged, coupled to a power node VI, and coupled to a second switching transistor Q. HS The control node and the sensing node V configured to be alternately coupled to the following: MS (For example, the source node):

[0112] When the second subset S2 of the switch is conductive, switch node VO, or

[0113] When the first subset of switches S1, S3, and S4 is conductive, the buffer device 13, BS.

[0114] For example, Figure 6 The circuit 60 shown in the example is based on Figure 4 relative to Figure 3 The example signal is operated.

[0115] exist Figure 7 In one or more alternative embodiments shown, for example:

[0116] Second sensing transistor M HS Arranged with the second switching transistor Q HS The current paths are connected in series, and

[0117] Buffer circuit 13, BS has a first node coupled to ground PGND (e.g., non-inverting) and coupled to sensing transistor M. HS Sensing node V MS The second node.

[0118] like Figure 7 As shown, for example:

[0119] The number of switches in the first subset of switches S1, S3, and S4 can be reduced, for example, by replacing the second sensing transistor M. HS The other sensing node and buffer switch BS are intermediated into a single switch S4.

[0120] The second switch S2 in the second subset of the switches is inserted into the input node of amplifier 13 in the buffer arrangement 13BS, such that when switch S2 is conductive, they are short-circuited to ground.

[0121] like Figure 8 As shown, across the first Q LS Second Q HS Switching converter devices that perform current sensing with high accuracy using switching transistors include reference transistors. Figure 3 Circuit 30 under discussion and reference Figure 7 Circuit 70 is under discussion.

[0122] like Figure 3 , 7 As shown in Figure 8, the first sensing transistor M LS It is the first switching transistor Q LS A copy, wherein the second sensing transistor M HS It is the second switching transistor Q HS A copy.

[0123] For the sake of simplicity, Figure 8 Reappearance in China Figure 3 The reference numbers and symbols for part of the circuit 30 shown have been modified to be in Figure 8 The suffix "L" is added to it, and Figure 8 Reappearance Figure 7 The reference numbers and symbols in the circuit 70 shown have been modified to include the suffix "H".

[0124] like Figure 8 As shown, the converter circuit 80 optionally includes a first T LS Second T HS Offset transistor (known in itself), first offset transistor T LS There is a current path between the output node VO and the non-inverting node of operational amplifier 13L, and the second offset transistor T HS There is a current path between the input node VI and the second node of the second amplifier 13H.

[0125] like Figure 8 As shown, an optional offset current generator IOFF is configured to provide the offset current level and is coupled to the offset transistors THS and TLS (if present).

[0126] For example, the first T LS Second T HS Offset transistors (along with their respective bias current generators I) OFF The buffers are configured to apply a voltage offset (e.g., non-inverting) to the first input of the respective buffers 13L and 13H to compensate for the inherent offset of the buffers, which may affect the first Q. LS Second Q HS Accurate sensing of the drain-source voltage of a power transistor is crucial when the load current decreases significantly, for example, approaching 0 amperes. For instance, when the load current is close to zero, the power transistor Q... LS Q HS The voltage drop is also close to ground, so the inherent negative offset of buffers 13L and 13H may force the current sensing structure to sense negative voltages on the drain / source terminals that the buffer cannot track. For example, in this case, the first T LS Second T HSThe offset transistor is designed to apply a positive voltage offset that is higher than the inherent offset of the buffers 13L and 13H.

[0127] In the presence of these optional offset compensation components T LS T HS I OFF In one or more embodiments, the switch sets S1, S2, S3 and S4 also help to apply the same stresses HCI and HTRB to these components, thereby improving overall circuit performance and avoiding mismatch.

[0128] like Figure 9 As shown, the operating circuit 80 includes:

[0129] At the first moment T1, the first set of switches S of circuit 30 1L S 2L S 3L S 4L The first S in 1L The third S 3L and the fourth S 3L The switch is based on a first drive signal X having a first (e.g., falling) edge. LS Non-conductive, and only requires the first drive signal X LS If it has a first value (such as "0"), it remains off.

[0130] At the same first time point T1, based on the first drive signal X having a first (e.g., falling edge) edge. LS The second switch S in circuit 30 2L Selective conduction, and only when the first drive signal X is present. LS A first (e.g., "0") value keeps the connection active.

[0131] At the subsequent time T2, the first S in circuit 70 1H The third S 3H and the fourth S 4H The switch is based on a second drive signal X having a second (e.g., rising) edge. HS And it is conductive, and only requires the second driving information X HS Having a second value (e.g., "1") keeps the circuit in the ON state; meanwhile, still at time T2, the second switch S in circuit 70... 2H Based on a second drive signal X having a second (e.g., rising) edge HS Selectively non-conductive, and only when the second driving information X HS Having a second value (e.g., "1") keeps it on.

[0132] In the circuit illustrated in this article, the ADC input provides a first and / or second sensing current I. MSL, I MS H and their respective first and / or second switching transistors Q LS Q HS The corresponding first and / or second currents I in QLS I QHS Proportional, with a stable scaling factor, independent of manufacturing process expansion, and considering temperature and aging phenomena occurring during various on / off steps throughout the lifespan of circuit 80.

[0133] like Figure 8 As shown, the switch converter device 80 includes: Figures 3 to 7 The circuit shown in the diagram, the inductive load L coupled between the intermediate node VO and the reference node VI PGND, the battery configured to provide a voltage supply level to the reference nodes VI and PGND or the ground node configured to provide a ground voltage level to the reference nodes VI and PGND, and the control circuit 12 configured to provide a control signal X LS X HS .

[0134] like Figures 3 to 9 The circuit shown in any of the figures includes: at least one switching transistor Q LS Q HS Its first terminal is configured to receive control signal X LS X HS And a current path between the second terminal VO and the third terminal PGND, VI of at least one switching transistor. For example, the at least one switching transistor is configured to switch to a conducting state in response to respective control signals having a first value, wherein a current flow line I is provided between the switching circuit node VO and the reference nodes VI, PGND through the current path of the at least one switching transistor. QLS I QHS In the circuit illustrated herein, at least one switching transistor in the conductive state has a conduction voltage drop between the second VO and the third VI, PGND terminals, and is configured to switch to a non-conductive state in response to a corresponding control signal having a second value, wherein, in the non-conductive state, a stress voltage drop is applied between the second and third terminals of the at least one switching transistor.

[0135] like Figures 3 to 9 As shown in any of the diagrams, the circuit further includes a sensing transistor M coupled to at least one switching transistor. LS M SH And configured to provide at least one scaled copy of a switching transistor, a sensing transistor having a current sensing flow path, wherein a current I flowing through the current sensing flow path of the sensing transistor is... MS The intensity indicates the current I flowing through the current path of at least one switching transistor. QLS IQHS The intensity.

[0136] like Figures 3 to 9 As shown in any example, the circuit further includes circuit means for coupling the sensing transistor circuits 13, SB, S1, S2, S3, S4 to at least one switching transistor, the coupling circuit means being configured to apply a stress voltage drop across the sensing transistor in response to at least one switching transistor being switched to a non-conductive state, wherein the stress voltage drop is replicated across at least one switching transistor and across the sensing transistor in response to at least one switching transistor being switched to a non-conductive state.

[0137] like Figures 3 to 8 As shown in any of the figures, the sensing transistor M LS M SH Including the junction area, which is at least one switching transistor Q LS Q HS The junction area is 1 / N times, where the current I flowing in the current sensing path of the sensing transistor is... MS It is the current I flowing in the current path that passes through at least one switching transistor. QLS I QHS 1 / N times the strength.

[0138] like Figure 3 , 6 As shown in any of the figures in Figure 8, the sensing transistor M LS MSH has coupling to at least one switching transistor Q. LS Q HS The first sensing terminal of the first terminal, and the second sensing terminal V of the sensing transistor. MS A current sensing path between the sensing transistor and the third sensing terminal, wherein the first sensing terminal of the sensing transistor is coupled to the first terminal of at least one switching transistor, and the third sensing terminal of the sensing semiconductor is coupled to the third terminal PGND,VI of at least one switching transistor.

[0139] like Figure 5 , 7 As shown in any of the figures in Figure 8, the sensing transistor M LS M SH Having coupled to at least one switching transistor Q LS Q HS The first sensing terminal of the first terminal, and the second sensing terminal V of the sensing transistor. MS A current sensing path between the sensing transistor and the third sensing terminal, wherein the sensing transistor has a first sensing terminal coupled to a first terminal of the at least one switching transistor, and the second sensing terminal is coupled to a second terminal of the at least one switching transistor.

[0140] like Figures 3 to 9 As shown in any of the figures, the coupling circuit devices 13, SB, S1, S2, S3, and S4 include an amplifier circuit 13, configured as follows:

[0141] S1, S2, S3, and S4 are coupled to at least one switching transistor and a sensing transistor. Amplifier circuit 13 is configured to sense the conduction voltage drop between the second VO and third VI PGND terminals of the at least one switching transistor in a conductive state.

[0142] In the non-conductive state, it is disconnected from the sensing transistor and at least one switching transistor S1, S2, S3, S4.

[0143] like Figure 3 , 6 As shown in any of Figures 8, the coupling circuit devices 13, SB, S1, S2, S3, and S4 include an amplifier circuit 13 configured to sense the conduction voltage drop between the second VO and third VI, PGND terminals of at least one switching transistor in a conductive state. The feedback loop BS of the amplifier circuit 13 is configured to cross the second sensing terminal V of the sensing transistor. MS The third sensing terminal replicates the conduction voltage drop across the second VO and third VI, PGND terminals of at least one switching transistor.

[0144] like Figure 10 As shown, the control unit (e.g., controller) 1000 includes:

[0145] According to at least one switching electronic converter 80 or at least one circuit of this disclosure,

[0146] The microcontroller 110 coupled to the circuit is configured to provide a control signal X thereto. LS X HS ,

[0147] At least one load Z L It is configured to be coupled to the circuit to receive the regulated output voltage VO.

[0148] As shown in this article, the control unit is installed on vehicle V, preferably an electric vehicle.

[0149] like Figure 10 As shown, the telematics control unit (TCU) 1000 equipped on an in-vehicle (e.g., wheeled and / or autonomous and / or electric) vehicle V includes a microchip 100, for example, for braking applications, including a first 30A and / or a second 30B sensing circuit.

[0150] For example, the TCU 1000 also includes:

[0151] Microcontroller 110 coupled to microchip 100,

[0152] The system base chip 120 is coupled to the microcontroller 110.

[0153] Reverse battery protection circuits 130 and 140 are coupled to the system base chip 120 and configured to be coupled to the battery of vehicle V.

[0154] A signal processing unit (e.g., a signal processor) 150 is configured to be coupled to a sensor SN (e.g., an inertial measurement unit) and a microprocessor 110 on the vehicle to provide sensor signals to them.

[0155] Transceiver unit (e.g., transceiver) 160, for example, a CAN / flex ray unit known per se.

[0156] The system-compatible chip (SCC170) is known in itself.

[0157] A common driver stage 180 is configured to be coupled to microchip 100 (e.g., based on a "group" principle or one per channel), and

[0158] Multiple load circuits Z configured to be coupled to microchip 100 L .

[0159] Additionally, it is understood that the various individual embodiments shown in the accompanying drawings are not necessarily to employ the same combinations shown in the figures. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations of the combinations shown in the figures.

[0160] Without affecting the basic principles, details and embodiments may vary as described by way of example only, without departing from the scope of protection.

[0161] The various embodiments described above can be combined to provide further embodiments.

[0162] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A circuit comprising: at least one switching transistor comprising: a first terminal configured to receive a control signal; and a second terminal and a third terminal, wherein the at least one switching transistor is configured to: selectively provide a first path for a first current, the first path being between the second terminal and the third terminal; switch to a conductive state in response to the control signal having a first value, in which the first path enables the first current to flow through the at least one switching transistor between a switching circuit node and a reference node, wherein in the conductive state the at least one switching transistor has a conductive voltage drop between the second terminal and the third terminal; and switch to a non-conductive state in response to the control signal having a second value, wherein in the non-conductive state a stress voltage drop is applied between the second terminal and the third terminal of the at least one switching transistor; a sense transistor coupled to the at least one switching transistor and configured to: provide a scaled copy of the at least one switching transistor; selectively provide a second path for a sense current through the sense transistor, wherein the sense current is indicative of the first current; and a coupling circuitry configured to: apply a stress voltage drop across the sense transistor in response to the at least one switching transistor being switched to the non-conductive state, wherein the stress voltage drop is replicated across the at least one switching transistor and across the sense transistor in response to the at least one switching transistor being switched to the non-conductive state.

2. The circuit of claim 1, wherein the sense transistor comprises: a junction area that is 1 / Nth of a junction area of the at least one switching transistor, wherein the sense current is 1 / Nth of the first current.

3. The circuit of claim 1, wherein the sense transistor comprises: a first sense terminal coupled to the first terminal of the at least one switching transistor; a second sense terminal; and a third sense terminal coupled to the third terminal of the at least one switching transistor, wherein the second path for the sense current is between the second sense terminal and the third sense terminal.

4. The circuit of claim 1, wherein the sense transistor comprises: a first sense terminal coupled to the first terminal of the at least one switching transistor; a second sense terminal coupled to the second terminal of the at least one switching transistor; and a third sense terminal, wherein the second path for the sense current is between the second sense terminal and the third sense terminal.

5. The circuit of claim 1, wherein the coupling circuitry comprises an amplifier circuit configured to: be coupled to the at least one switching transistor and the sense transistor; sense the conductive voltage drop between the second terminal and the third terminal of the at least one switching transistor in the conductive state; and be decoupled from the sense transistor and the at least one switching transistor in the non-conductive state. ​ ​ ​ 6. The circuit of claim 3, wherein the coupling circuitry comprises an amplifier circuit configured to: sense a conduction voltage drop between the second terminal and the third terminal of the at least one switching transistor in the conductive state, wherein the amplifier circuit has a feedback loop configured to replicate the conduction voltage drop between the second terminal and the third terminal of the at least one switching transistor across the second sense terminal and the third sense terminal of the sense transistor.

7. A switching converter comprising: a circuit comprising: at least one switching transistor comprising: a first terminal configured to receive a control signal; and a second terminal and a third terminal, wherein the at least one switching transistor is configured to: selectively provide a first path for a first current, the first path being between the second terminal and the third terminal; switch to a conductive state in response to the control signal having a first value, the first path enabling the first current to flow through the at least one switching transistor between a switching circuit node and a reference node in the conductive state, wherein the at least one switching transistor has a conduction voltage drop between the second terminal and the third terminal in the conductive state; and switch to a non-conductive state in response to the control signal having a second value, wherein a stress voltage drop is applied between the second terminal and the third terminal of the at least one switching transistor in the non-conductive state; a sense transistor coupled to the at least one switching transistor and configured to: provide a scaled copy of the at least one switching transistor; and selectively provide a second path for a sense current through the sense transistor, wherein the sense current is indicative of the first current; and coupling circuitry configured to: apply the stress voltage drop across the sense transistor in response to the at least one switching transistor being switched to the non-conductive state, wherein the stress voltage drop is replicated across the at least one switching transistor and replicated across the sense transistor in response to the at least one switching transistor being switched to the non-conductive state; an inductive load coupled between the switching circuit node and the reference node; a battery configured to provide a supply voltage to the reference node, or a ground node configured to provide a ground voltage level to the reference node; and control circuitry configured to output the control signal.

8. The switching converter of claim 7, wherein the sense transistor comprises: a junction area that is 1 / Nth the junction area of the at least one switching transistor, wherein the sense current is 1 / Nth the first current.

9. The switching converter of claim 7, wherein the sense transistor comprises: a first sense terminal coupled to the first terminal of the at least one switching transistor; a second sense terminal; and a junction area that is 1 / Nth the junction area of the at least one switching transistor, wherein the sense current is 1 / Nth the first current. a third sense terminal coupled to the third terminal of the at least one switching transistor, wherein the second path for the sense current is between the second sense terminal and the third sense terminal.

10. The switching converter of claim 7, wherein the sense transistor comprises: a first sense terminal coupled to the first terminal of the at least one switching transistor; a second sense terminal coupled to the second terminal of the at least one switching transistor; and a third sense terminal, wherein the second path for the sense current is between the second sense terminal and the third sense terminal.

11. The switching converter of claim 7, wherein the coupling circuitry comprises an amplifier circuit configured to: couple to the at least one switching transistor and the sense transistor; sense the conduction voltage drop between the second terminal and the third terminal of the at least one switching transistor in the conductive state; and decouple from the sense transistor and the at least one switching transistor in the non-conductive state.

12. The switching converter of claim 9, wherein the coupling circuitry comprises an amplifier circuit configured to: sense the conduction voltage drop between the second terminal and the third terminal of the at least one switching transistor in the conductive state, wherein the amplifier circuit has a feedback loop configured to replicate the conduction voltage drop across the second sense terminal and the third sense terminal of the sense transistor across the second terminal and the third terminal of the at least one switching transistor.

13. A controller comprising: circuitry comprising: at least one switching transistor comprising: a first terminal configured to receive a control signal; and a second terminal and a third terminal, wherein the at least one switching transistor is configured to: selectively provide a first path for a first current, the first path being between the second terminal and the third terminal; switch to a conductive state in response to the control signal having a first value, in which the first path enables the first current to flow through the at least one switching transistor between a switching circuit node and a reference node, wherein in the conductive state the at least one switching transistor has a conduction voltage drop between the second terminal and the third terminal; and switch to a non-conductive state in response to the control signal having a second value, in which in the non-conductive state a stress voltage drop is applied between the second terminal and the third terminal of the at least one switching transistor; a sense transistor coupled to the at least one switching transistor and configured to: provide a scaled copy of the at least one switching transistor; and selectively provide a second path for a sense current through the sense transistor, wherein the sense current is indicative of the first current; and coupling circuitry configured to: ​ ​ in response to the at least one switch transistor being switched to the non-conductive state, applying the stress voltage drop across the sense transistor, wherein in response to the at least one switch transistor being switched to the non-conductive state, the stress voltage drop is replicated across the at least one switch transistor and replicated across the sense transistor; a microcontroller coupled to the circuit and configured to output the control signal to the circuit; and at least one load configured to be coupled to the circuit and receive a regulated output voltage from the circuit.

14. The controller of claim 13, wherein the sense transistor comprises: a junction area that is 1 / Nth the junction area of the at least one switch transistor, wherein the sense current is 1 / Nth the first current.

15. The controller of claim 13, wherein the sense transistor comprises: a first sense terminal coupled to the first terminal of the at least one switch transistor; a second sense terminal; and a third sense terminal coupled to a third terminal of the at least one switch transistor, wherein the second path for the sense current is between the second sense terminal and the third sense terminal.

16. The controller of claim 13, wherein the sense transistor comprises: a first sense terminal coupled to the first terminal of the at least one switch transistor; a second sense terminal coupled to the second terminal of the at least one switch transistor; and a third sense terminal, wherein the second path for the sense current is between the second sense terminal and the third sense terminal.

17. The controller of claim 13, wherein the coupling circuitry comprises an amplifier circuit configured to: couple to the at least one switch transistor and the sense transistor; sense the conductive voltage drop between the second terminal and the third terminal of the at least one switch transistor in the conductive state; and decouple from the sense transistor and the at least one switch transistor in the non-conductive state.

18. The controller of claim 15, wherein the coupling circuitry comprises an amplifier circuit configured to: sense the conductive voltage drop between the second terminal and the third terminal of the at least one switch transistor in the conductive state, wherein the amplifier circuit has a feedback loop configured to replicate the conductive voltage drop between the second terminal and the third terminal of the at least one switch transistor across the second sense terminal and the third sense terminal of the sense transistor.

19. The controller of claim 13, wherein the controller is installed on a vehicle.

20. The controller of claim 19, wherein the vehicle is an electric vehicle.

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