A bandgap reference current circuit module

Abstract

The present invention provides a bandgap reference current circuit module, which compensates for temperature curvature by introducing an additional branch current, reduces output power ripple through preset LDO modulation and common-mode cancellation schemes, and further reduces medium and low-frequency power ripple and noise by using a parallel capacitor at the output end.

Description

Technical Field

[0001] The present invention relates to the technical field related to bandgap reference circuits, and in particular to a bandgap reference current circuit module. Background Art

[0002] The bandgap reference circuit module is a basic and important circuit in analog integrated circuits such as power management systems, analog-to-digital / digital-to-analog converters (ADC / DAC), and phase-locked loops (PLLs). Its primary design goal is to maintain an accurate voltage source or current source with minimal temperature impact over a wide temperature range, even though the process parameters of current integrated circuits vary nonlinearly with temperature. In addition to the inevitable deviation in the reference output caused by temperature changes, high-frequency power ripple from the power input voltage and the noise inherent in the device will also reduce the accuracy of the reference voltage and current sources. The accuracy of the reference voltage and current sources affects the power purity of the power management system, the resolution of the high-precision analog-to-digital / digital-to-analog converter, the phase noise of the phase-locked loop, and other circuit parameters.

[0003] Therefore, there is an urgent need to design a bandgap reference current circuit module with small temperature drift, high power supply rejection ratio and low noise to meet the design goals. Summary of the Invention

[0004] In order to solve the problems mentioned above, the present invention provides a bandgap reference current circuit module, which compensates for temperature curvature by introducing additional branch current, reduces output power ripple through preset LDO modulation and common-mode cancellation scheme, and further reduces medium and low frequency power ripple and noise by using parallel capacitors at the output end.

[0005] The technical solution is as follows: a bandgap reference current circuit module, characterized in that: the circuit module includes a resistor R1 and a resistor R2, wherein the resistors R1 and R2 are connected in series and then connected in parallel with an N-type BJT tube Q3, and one end of the parallel connection is connected to the power supply voltage PRE-LDO1, and the other end is connected to the drain of the N-type MOS tube M5, the divided voltage generated by R1 and R2 is input to the base of the N-type BJT tube Q1, and the collector and base of Q3 are connected and then connected to PRE-LDO1, and the emitter is connected to the drain of M5;

[0006] The circuit module further includes a resistor R3, one end of which is connected to the PRE-LDO1, and the other end is connected to the source of the P-type MOS transistor M1, the collector of Q1, and the collector of the N-type BJT transistor Q5. The drain of M1 is connected to the gate and the drain is connected to the drain of the N-type MOS transistor M9.

[0007] The circuit module further includes a resistor R4, one end of which is connected to the PRE-LDO1, and the other end of which is connected to the source of the P-type MOS transistor M2, the collector of the N-type BJT transistor Q2, and the collector of the N-type BJT transistor Q4. The emitters of Q1 and Q2 are connected and then connected to the drain of the N-type MOS transistor M7. The emitters of Q5 and Q4 are connected and then grounded through a resistor R14. The gates of M1 and M2 are connected. The drain and gate of M2 are connected through a capacitor C1, and the drain of M2 is connected to the drain of the N-type MOS transistor M11.

[0008] The circuit module further includes a resistor R5, one end of which is connected to the PRE-LDO1, and the other end is connected to the source of the P-type MOS transistor M3, the gate of M3 is connected to the drain of M2, and the drain of M3 is connected to the drain of the N-type MOS transistor M13;

[0009] The circuit module further includes a resistor R6, one end of which is connected to PRE-LDO1, and the other end is connected to the drain of the N-type MOS transistor M4 and the base of Q2, the gate of M4 is connected to the drain of M3, and the source of M4 is connected to one end of an external resistor RSET and a signal terminal VSET, the other end of RSET is grounded, and RSET is connected in parallel with an external capacitor CSET;

[0010] The circuit module further includes a resistor R17, a resistor R16, and a resistor R15, wherein R17, R16, and R15 are connected in series, one end of which is connected to the power supply voltage PRE-LDO2, and the other end is grounded, and the divided voltage generated by R17 and R16 is input to the base of Q5, and the divided voltage generated by R16 and R15 is input to the base of Q4;

[0011] The gates of M5, M7, M9, and M11 are all connected to PRE-LDO2, the source of M5 is connected to the drain of N-type MOS transistor M6, the source of M7 is connected to the drain of N-type MOS transistor M8, the source of M9 is connected to the drain of N-type MOS transistor M10, and the source of M11 is connected to the drain of N-type MOS transistor M12;

[0012] The circuit module also includes a resistor R7, one end of which is connected to PRE-LDO2, and the other end is connected to the drain of an N-type MOS tube M114. The drain and gate of M14 are connected, and the gate of M14 is also connected to the gates of M6, M8, M10, M12, and M13 respectively; M14 is grounded through a resistor R8, M6 is grounded through a resistor R9, M8 is grounded through a resistor R10, M10 is grounded through a resistor R11, M12 is grounded through a resistor R12, and M13 is grounded through a resistor R13.

[0013] Furthermore, the resistance values ​​of R3 and R4 are equal; the width-to-length ratios of M1 and M2 are equal; the width-to-length ratios of M9 and M11 are equal; and the width-to-length ratios of M10 and M12 are equal.

[0014] Furthermore, the voltages of the input node A and the input node B of the current operational amplifier are equal.

[0015] Furthermore, the ratio of the number of Q1 to Q2 is 1:8; the ratio of the number of Q4 to Q5 is 4:1.

[0016] Furthermore, the output current of the circuit module is: I Ref = [V Q1_BE *R1 / (R1+R2) +V T ln8] / R6; where V Q1_BE is the base-emitter voltage difference of Q1 tube, V T is the thermal voltage, R1, R2, R6 are the resistance values ​​of resistors R1, R2, R6 respectively, and the output current is mainly adjusted by R1, R2, R6.

[0017] Furthermore, the access voltage VIN of PRE-LDO1 and PRE-LDO2 is a voltage provided by the pre-preset LDO negative feedback structure after preliminary filtering of the power ripple. The output voltage value of PRE-LDO2 is a fixed voltage value generated by the bandgap reference voltage. The output voltage value of PRE-LDO1 is the higher value of the output terminal voltage of the bandgap reference current source and the output voltage of PRE-LDO2.

[0018] The beneficial effects of the present invention are:

[0019] 1. The present invention provides a common-mode power ripple cancellation solution. Since this design generates precise current on a precise resistor through a reference voltage, the power ripple associated with the reference voltage determines the accuracy of its output current. The Q2 input needs to be consistent with the power ripple. The current flowing through the M1 and M2 tubes is controlled by a current source. When the current amplifier bandwidth is large enough, the two currents in the bandgap core of this circuit can still be considered equal under the condition of high-frequency power ripple. At the same time, the parallel capacitor CSET at the output end of the bandgap reference current equivalently reduces the mid-frequency pull-down impedance of the set output end VSET, mainly improving the power supply rejection ratio in the 10-100Hz frequency band. The output integral noise of the filter capacitor connected to the output end of the bandgap reference current source and the method of increasing the width-to-length ratio and reducing the gate resistance in the layout design of the M4 power tube can effectively reduce the noise of the reference circuit.

[0020] 2. The present invention also provides a second-order temperature compensation scheme. When the second-order compensation composed of Q4 and Q5 is not included, the curvature of the bandgap reference voltage is less than zero, and the opening direction of the reference temperature change curve is downward. After adding temperature compensation, after reaching the set temperature, the current flowing through Q4 relative to the Q5 branch rises as the temperature rises. Since the sum of the currents in the Q1 and Q5 branches is equal to the sum of the currents in the Q2 and Q4 branches, the Q2 current decreases, and the Q2 base voltage drops to provide a positive temperature coefficient compensation superposition for the reference current; the R16 resistor is mainly responsible for the base voltage difference, R15 and R17 mainly provide common-mode current, and together with R14 determine the current size of the bandgap compensation part. After the compensation current is introduced, the currents in the Q1 and Q2 tubes in the bandgap core are not completely equal, and their current sizes are related to the positive temperature coefficient, and the curvature is reduced; thereby realizing a curvature-corrected bandgap reference voltage, and then obtaining a reference current source with a high power supply rejection ratio through the current operational amplifier structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a circuit diagram of the present invention;

[0022] Figure 2 Schematic diagram of the power supply voltage setting of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described below with reference to the embodiments.

[0024] The following examples are intended to illustrate the present invention but are not intended to limit the scope of protection of the present invention. The conditions in the examples may be further adjusted according to specific conditions. Simple improvements to the method of the present invention within the scope of the present invention are also within the scope of protection claimed in the present invention.

[0025] like Figure 1As shown, a bandgap reference current circuit module includes a resistor R1 and a resistor R2, wherein R1 and R2 are connected in series and then connected in parallel with an N-type BJT tube Q3, and after the parallel connection, one end is connected to the power supply voltage PRE-LDO1, and the other end is connected to the drain of the N-type MOS tube M5. The divided voltage generated by R1 and R2 is input to the base of the N-type BJT tube Q1, and the collector and base of Q3 are connected and then connected to PRE-LDO1, and the emitter is connected to the drain of M5; the circuit module also includes a resistor R3, wherein one end of R3 is connected to PRE-LDO1, and the other end is connected to the source of the P-type MOS tube M1, the collector of Q1, and the collector of the N-type BJT tube Q5, and the drain of M1 is connected to the gate and the drain is connected The circuit module further comprises a resistor R4, one end of which is connected to the PRE-LDO1, and the other end is connected to the source of the P-type MOS tube M2, the collector of the N-type BJT tube Q2, and the collector of the N-type BJT tube Q4. The emitters of Q1 and Q2 are connected and then connected to the drain of the N-type MOS tube M7. The emitters of Q5 and Q4 are connected and then grounded through a resistor R14. The gates of M1 and M2 are connected. The drain and gate of M2 are connected through a capacitor C1, and the drain is connected to the drain of the N-type MOS tube M11. The circuit module further comprises a resistor R5, one end of which is connected to the PRE-LDO1, and the other end is connected to the source of the P-type MOS tube M3. The gate is connected to the drain of M2 and the drain of M3 is connected to the drain of the N-type MOS tube M13; the circuit module also includes a resistor R6, one end of the R6 is connected to PRE-LDO1, and the other end is connected to the drain of the N-type MOS tube M4 and the base of Q2, the gate of M4 is connected to the drain of M3 and the source of M4 is connected to one end of the external resistor RSET and the signal terminal VSET, the other end of the RSET is grounded, and the RSET is connected in parallel with the external capacitor CSET; the circuit module also includes a resistor R17, a resistor R16 and a resistor R15, one end of the R17, R16 and R15 connected in series is connected to the power supply voltage PRE-LDO2, and the other end is grounded, and the voltage divided by R17 and R16 is output. The voltage is input to the base of Q5, and the divided voltage generated by R16 and R15 is input to the base of Q4; the gates of M5, M7, M9, and M11 are all connected to PRE-LDO2, the source of M5 is connected to the drain of N-type MOS transistor M6, the source of M7 is connected to the drain of N-type MOS transistor M8, the source of M9 is connected to the drain of N-type MOS transistor M10, and the source of M11 is connected to the drain of N-type MOS transistor M12; the circuit module also includes a resistor R7, one end of which is connected to PRE-LDO2, and the other end is connected to the drain of N-type MOS transistor M114, the drain and gate of M14 are connected, and the gate of M14 is also connected to the gates of M6, M8, M10, M12, and M13 respectively;The M14 is grounded via a resistor R8, the M6 ​​is grounded via a resistor R9, the M8 is grounded via a resistor R10, the M10 is grounded via a resistor R11, the M12 is grounded via a resistor R12, and the M13 is grounded via a resistor R13.

[0026] The resistance values ​​of R3 and R4 are set to be equal; the width-to-length ratios of M1 and M2 are set to be equal; the width-to-length ratios of M9 and M11 are set to be equal; the width-to-length ratios of M10 and M12 are set to be equal; the voltages of input node A and input node B of the current operational amplifier are set to be equal, so that the currents flowing through resistors R3 and R4 are equal. Since the currents passing through M1 and M2 are equal under stable operation, the currents passing through Q1 and Q5 are also equal to the currents passing through Q2 and Q4. The currents of Q4 and Q5 serve as a bandgap reference error compensation circuit. The resistance values ​​of R14 and R15 are relatively large, so that the magnitudes of their currents are approximately negligible compared with the currents of Q1, Q2, M1 and M2. Therefore, the currents of Q1 and Q2 are approximately equal when calculating the bandgap voltage.

[0027] The ratio of the number of Q1 and Q2 is set to 1:8, that is, MQ1:MQ2 =1:8; the ratio of the number of Q4 and Q5 is set to 4:1, that is, MQ4:MQ5 =4:1.

[0028] Setting V SUPPLY1 To express the size of PRE-LDO1, V Q1B Indicates that the voltage at the input of Q1 is:

[0029] V Q1B =V SUPPLY1 -V Q1_BE *R1 / (R1+R2).

[0030] Since the emitters of Q1 and Q2 are connected, the currents flowing through the two tubes are equal. Since the number of tubes is not equal, the saturation current of Q1 I s1 and Q2 saturation current I s2 The ratio is N, which is the ratio of the number of Q1 and Q2 tubes. Therefore, when the circuit is stable, the base voltage difference between the two tubes is ΔV BE :

[0031] ΔV BE =V T ln(I s1 / I s2 ) = V T lnN=V T ln8.

[0032] V R6 The voltage difference across the resistor R6 is mainly generated by the voltage divider of Q3 and the base voltage difference of Q1 and Q2. Its value is

[0033] V R6 =V Q1_BE *R1 / (R1+R2) +V T ln8.

[0034] Therefore, through I Ref Indicates that the size of the bandgap reference current source is:

[0035] I Ref =[V Q1_BE *R1 / (R1+R2) +V T ln8] / R6.

[0036] It can be seen from the above formula that the bandgap reference current source is mainly adjusted appropriately by R1, R2, and R6.

[0037] Preferably, when the ripple of PRE-LDO1 is large and the voltage variation range is wide, it is recommended that PRE-LDO1 and PRE-LDO2 adopt the following Figure 2 In the power supply scheme shown, the access voltage VIN of PRE-LDO1 and PRE-LDO2 is the voltage provided by the pre-preset LDO negative feedback structure after the power ripple is initially filtered out. The output voltage value of PRE-LDO2 is a fixed voltage value generated by the bandgap reference voltage. The output voltage value of PRE-LDO1 is the higher value of the output voltage of the bandgap reference current source and the output voltage of PRE-LDO2, so that the power supply voltage of the bandgap reference current source circuit has sufficient voltage margin and smaller power ripple.

[0038] Furthermore, the power ripple entering Q1 is: V PR_Q1 =V PR-LDO1 R1 / (R1+R2); where V PR-LDO1 The ripple in the power supply voltage PRE-LDO1 has been fed back by the previous stage pre-regulation LDO, filtering out some low- and medium-frequency ripples. R15, R16, and R17 represent the resistance values ​​of resistors R15, R16, and R17. V PR-LDO2 is the voltage value of the power supply voltage PRE-LDO2, V PR_Q1 Indicates that the voltage difference between Q4 and Q5 is: V PR_Q1 = V PR_LDO2 R16 / (R15+R16+R17).

[0039] When the second-order compensation composed of Q4 and Q5 is not included, the curvature of the bandgap reference voltage is less than zero, and the opening direction of the reference curve with temperature change is downward. After adding temperature compensation, after reaching the set temperature, the current flowing through Q4 relative to the Q5 branch rises as the temperature rises. Since the sum of the currents in the Q1 and Q5 branches is equal to the sum of the currents in the Q2 and Q4 branches, the Q2 current decreases, and the Q2 base voltage drops to provide a positive temperature coefficient compensation superposition for the reference current; the R16 resistor is mainly responsible for the base voltage difference, R15 and R17 mainly provide common-mode current, and together with R14 determine the current size of the bandgap compensation part. After the compensation current is introduced, the currents in Q1 and Q2 tubes in the bandgap core are not completely equal, and their current sizes are related to the positive temperature coefficient, and the curvature is reduced; thereby realizing a curvature-corrected bandgap reference voltage, and then obtaining a reference current source with a high power supply rejection ratio through the current operational amplifier structure.

Claims

1. A bandgap reference current circuit module, characterized in that: The circuit module includes a resistor R1 and a resistor R2. The resistors R1 and R2 are connected in series and then connected in parallel with an N-type BJT transistor Q3. After the parallel connection, one end is connected to the power supply voltage PRE-LDO1, and the other end is connected to the drain of the N-type MOS transistor M5. The divided voltage generated by R1 and R2 is input to the base of the N-type BJT transistor Q1. The collector and base of Q3 are connected and then connected to PRE-LDO1, and the emitter is connected to the drain of M5. The circuit module further includes a resistor R3, one end of which is connected to the PRE-LDO1, and the other end is connected to the source of the P-type MOS transistor M1, the collector of Q1, and the collector of the N-type BJT transistor Q5. The drain of M1 is connected to the gate and the drain is connected to the drain of the N-type MOS transistor M9. The circuit module further includes a resistor R4, one end of which is connected to the PRE-LDO1, and the other end of which is connected to the source of the P-type MOS transistor M2, the collector of the N-type BJT transistor Q2, and the collector of the N-type BJT transistor Q4. The emitters of Q1 and Q2 are connected and then connected to the drain of the N-type MOS transistor M7. The emitters of Q5 and Q4 are connected and then grounded through a resistor R14. The gates of M1 and M2 are connected. The drain and gate of M2 are connected through a capacitor C1, and the drain of M2 is connected to the drain of the N-type MOS transistor M11. The circuit module further includes a resistor R5, one end of which is connected to the PRE-LDO1, and the other end is connected to the source of the P-type MOS transistor M3, the gate of M3 is connected to the drain of M2, and the drain of M3 is connected to the drain of the N-type MOS transistor M13; The circuit module further includes a resistor R6, one end of which is connected to PRE-LDO1, and the other end is connected to the drain of the N-type MOS transistor M4 and the base of Q2, the gate of M4 is connected to the drain of M3, and the source of M4 is connected to one end of an external resistor RSET and a signal terminal VSET, the other end of RSET is grounded, and RSET is connected in parallel with an external capacitor CSET; The circuit module further includes a resistor R17, a resistor R16, and a resistor R15, wherein R17, R16, and R15 are connected in series, one end of which is connected to the power supply voltage PRE-LDO2, and the other end is grounded, and the divided voltage generated by R17 and R16 is input to the base of Q5, and the divided voltage generated by R16 and R15 is input to the base of Q4; The gates of M5, M7, M9, and M11 are all connected to PRE-LDO2, the source of M5 is connected to the drain of N-type MOS transistor M6, the source of M7 is connected to the drain of N-type MOS transistor M8, the source of M9 is connected to the drain of N-type MOS transistor M10, and the source of M11 is connected to the drain of N-type MOS transistor M12; The circuit module also includes a resistor R7, one end of which is connected to PRE-LDO2, and the other end is connected to the drain of an N-type MOS tube M114. The drain and gate of M14 are connected, and the gate of M14 is also connected to the gates of M6, M8, M10, M12, and M13 respectively; M14 is grounded through a resistor R8, M6 is grounded through a resistor R9, M8 is grounded through a resistor R10, M10 is grounded through a resistor R11, M12 is grounded through a resistor R12, and M13 is grounded through a resistor R13.

2. The bandgap reference current circuit module according to claim 1, wherein: The resistance values ​​of R3 and R4 are equal; the width-to-length ratios of M1 and M2 are equal; the width-to-length ratios of M9 and M11 are equal; and the width-to-length ratios of M10 and M12 are equal.

3. The bandgap reference current circuit module according to claim 1, wherein: The voltages at the input node A and the input node B of the current operational amplifier are equal.

4. The bandgap reference current circuit module according to claim 1, wherein: The ratio of the number of Q1 to Q2 is 1:8; the ratio of the number of Q4 to Q5 is 4:

1.

5. The bandgap reference current circuit module according to claim 4, characterized in that: The output current of the circuit module is: I Ref = [V Q1_BE *R1 / (R1+R2) +V T ln8] / R6; where V Q1_BE is the base-emitter voltage difference of Q1 tube, V T is the thermal voltage, R1, R2, R6 are the resistance values ​​of resistors R1, R2, R6 respectively; the output current is adjusted by R1, R2, R6.

6. The bandgap reference current circuit module according to claim 1, wherein: The access voltage VIN of the PRE-LDO1 and PRE-LDO2 is a voltage provided by the pre-preset LDO negative feedback structure after the power ripple is preliminarily filtered out. The output voltage value of PRE-LDO2 is a fixed voltage value generated by the bandgap reference voltage. The output voltage value of PRE-LDO1 is the higher value of the output terminal voltage of the bandgap reference current source and the output voltage of PRE-LDO2.

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