Standard cell library verification method and device, electronic equipment and storage medium

Abstract

The application provides a standard cell library verification method and device, electronic equipment and storage medium, and belongs to the technical field of integrated circuit design. The standard cell library verification method comprises the following steps: obtaining a to-be-verified layout corresponding to a standard cell library, the standard cell library comprising N types of to-be-tested cells with equal height, and the to-be-verified layout comprising N sub-splicing layouts; in the first row and the third row of the i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells are the i-th to-be-tested cell and the mirror image of the i-th to-be-tested cell in the N types of to-be-tested cells; the second row of the i-th sub-splicing layout comprises the i-th to-be-tested cell to the N-th to-be-tested cell, wherein the first row, the second row and the third row of each sub-splicing layout are spliced in the vertical direction in sequence, i is sequentially taken as 1 to N, i and N are positive integers; and the to-be-verified layout is verified to obtain verification results of the N types of to-be-tested cells.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, in particular to a standard cell library verification method and device, electronic equipment and storage medium. BACKGROUND

[0002] In order to check whether the splicing between the layouts of any cells in the standard cell library violates the design rules provided by the foundry, it is necessary to simulate the splicing of all cells in the standard cell library in any real application, and the spliced layout must pass the design rule verification.

[0003] Currently, horizontal splicing and vertical splicing need to be performed on all cells in the standard cell library respectively, and the spliced layouts are verified respectively.

[0004] The existing vertical splicing method of each cell and the corresponding mirror cell is as shown in Figure 1 In the first row and the third row of each splicing cell, any two adjacent cells are the same cell and its mirror. If the standard cell library includes N cells, when the first row of the splicing cell includes the i-th cell in the standard cell library, the second row of the splicing cell includes the i-th cell to the N-th cell in the standard cell library and the mirror of the i-th cell to the N-th cell. When checking the standard cell using the splicing scheme, the second row of each splicing cell needs to be moved in a preset direction by one step multiple times until a preset condition is met. Before the second row of the splicing cell is moved by one step each time, the current layout is saved, and after the preset condition is met, all saved layouts are verified to obtain a verification result. However, due to the large number of cells included in the layout, the verification efficiency is low. SUMMARY

[0005] The present application provides a standard cell library verification method and device, electronic equipment and storage medium to solve the problem of low verification efficiency due to the large number of cells included in the layout in the prior art.

[0006] In a first aspect, the present application provides a standard cell library verification method, comprising: obtaining a to-be-verified layout corresponding to a standard cell library, the standard cell library comprising N types of to-be-tested cells with equal height, the to-be-verified layout comprising N sub-splicing layouts, in a first row and a third row of an i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells are respectively an i-th to-be-tested cell and a mirror image of the i-th to-be-tested cell of the N types of to-be-tested cells, a second row of the i-th sub-splicing layout comprising an i-th to-be-tested cell to an N-th to-be-tested cell, wherein the first row, the second row and the third row of each sub-splicing layout are spliced in sequence in a vertical direction, the length of the first row and the third row of each sub-splicing layout is greater than the length of the second row thereof, i is sequentially taken as 1 to N, i and N are positive integers; and verifying the to-be-verified layout to obtain verification results of the N types of to-be-tested cells.

[0007] In the embodiments of the present application, the second row of each sub-splicing layout only comprises the i-th to-be-tested cell to the N-th to-be-tested cell of the N types of to-be-tested cells, that is, the number of test cells in the second row of each sub-splicing layout in the present solution is only half of that in the prior art. Therefore, the data amount of the layout to be verified in the present solution is less than that of the layout to be verified in the prior art, thereby improving the verification efficiency.

[0008] In combination with the technical solution provided in the above first aspect, in some possible implementation manners, the first row of the i-th sub-splicing layout comprises K i-th to-be-tested cells, K=[X / Y+3], X is the total length of the second row of the i-th sub-splicing layout, Y is the length of the i-th to-be-tested cell, and [X / Y+3] represents rounding X / Y+3.

[0009] In the embodiments of the present application, the number of test cells included in the first row of each sub-splicing layout is determined by the relationship K=[X / Y+3], which can ensure that the first row of each sub-splicing layout is at least two lengths of test cells longer than the second row thereof. Therefore, even if the second row of the sub-splicing layout is moved, it can always be in the vertical projection of the first row of the sub-splicing layout in the subsequent verification process, ensuring that each to-be-tested cell of the second row is always completely spliced with the first row, thereby improving the accuracy of the final test result.

[0010] With the technical solution provided in the first aspect above, in some possible implementation manners, the verifying the to-be-verified layout to obtain the verification result of the N kinds of to-be-tested cells comprises: verifying the to-be-verified layout to obtain a first sub-verification result; moving the second row in each sub-spliced layout by a preset step length in a specified direction, verifying the moved to-be-verified layout to obtain a second sub-verification result, and repeating the above steps until a preset condition is met, wherein the verification result comprises all the obtained sub-verification results.

[0011] In the embodiments of the present application, the second row in each sub-spliced layout is moved by a preset step length in a specified direction, that is, the to-be-verified layout is verified once, so that when the verification result is incorrect, the location of the error can be quickly located.

[0012] With the technical solution provided in the first aspect above, in some possible implementation manners, the preset condition is that the second row in each sub-spliced layout is moved by a preset number of times in a specified direction.

[0013] In the embodiments of the present application, the second row in each sub-spliced layout is moved by a preset number of times in a specified direction as the preset condition, so that the timing of stopping movement can be accurately determined.

[0014] With the technical solution provided in the first aspect above, in some possible implementation manners, the second row of the i-th sub-spliced layout comprises the i-th to-be-tested cell to the N-th to-be-tested cell arranged in sequence.

[0015] With the technical solution provided in the first aspect above, in some possible implementation manners, the length of the first to-be-tested cell to the N-th to-be-tested cell in the standard cell library increases in sequence.

[0016] In a second aspect, the present application provides a standard cell library verification device, comprising: an acquisition module and a verification module, the acquisition module is used to acquire a to-be-verified layout corresponding to a standard cell library, the standard cell library comprises N kinds of to-be-tested cells with equal height, the to-be-verified layout comprises N sub-spliced layouts, in the first row and the third row of the i-th sub-spliced layout of the N sub-spliced layouts, any two adjacent to-be-tested cells are the i-th to-be-tested cell and the mirror image of the i-th to-be-tested cell in the N kinds of to-be-tested cells, the second row of the i-th sub-spliced layout comprises the i-th to-be-tested cell to the N-th to-be-tested cell, wherein the first row, the second row and the third row of each sub-spliced layout are spliced in sequence in the vertical direction, the length of the first row and the third row of each sub-spliced layout is greater than the length of the second row thereof, i takes 1 to N in sequence, and i and N are positive integers; the verification module is used to verify the to-be-verified layout to obtain a verification result of the N kinds of to-be-tested cells.

[0017] With the technical solution provided in the second aspect above, in some possible implementation manners, the verification module is specifically configured to verify the verification layout to obtain a first sub-verification result; move a second row in each sub-spliced layout in a specified direction by a preset step length, verify the moved verification layout to obtain a second sub-verification result, and repeat the above steps until a preset condition is met, wherein the verification result includes all the obtained sub-verification results.

[0018] In a third aspect, the embodiments of the present application further provide an electronic device, comprising a memory and a processor, the memory and the processor being connected; the memory is configured to store a program; and the processor is configured to invoke the program stored in the memory to execute the method provided in the embodiments of the first aspect above and / or any possible implementation manner in combination with the first aspect above.

[0019] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores a computer program, and the computer program is run by a computer to execute the method provided in the embodiments of the first aspect above and / or any possible implementation manner in combination with the first aspect above. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0021] Figure 1 Structure diagram of the to-be-verified layout shown in the prior art;

[0022] Figure 2 Flow diagram of the standard cell library verification method shown in the embodiments of the present application;

[0023] Figure 3 Placement manner diagram of the to-be-tested cell in the standard cell library shown in the embodiments of the present application;

[0024] Figure 4 Structure diagram of the sub-spliced layout shown in the embodiments of the present application;

[0025] Figure 5 Structure diagram of the first to-be-verified layout shown in the embodiments of the present application;

[0026] Figure 6 Structure diagram of the second to-be-verified layout shown in the embodiments of the present application;

[0027] Figure 7 A structure diagram of each sub-tile layout in a to-be-verified layout and a structure diagram of each sub-tile layout after moving, shown by an embodiment of the present application;

[0028] Figure 8 A structure diagram of each sub-tile layout in a to-be-verified layout, shown by an embodiment of the present application;

[0029] Figure 9 A structure block diagram of a standard cell library verification device, shown by an embodiment of the present application;

[0030] Figure 10 A structure block diagram of an electronic device, shown by an embodiment of the present application. DETAILED DESCRIPTION

[0031] The terms "first", "second", "third", and the like, are used only to distinguish descriptions, and do not indicate the arrangement sequence, and cannot be understood as indicating or implying relative importance.

[0032] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0033] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the relationship terms such as "first", "second", and the like, are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or sequence between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a…" does not exclude the existence of another same element in the process, method, article or device including the element.

[0034] Furthermore, in the present application, the term "and / or" is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A existing alone, A and B existing together, and B existing alone.

[0035] The technical solutions of the present application will be described in detail below with reference to the drawings.

[0036] Please refer to Figure 2 , Figure 2A flowchart of a standard cell library verification method provided by an embodiment of the present application is shown in the following. Figure 2 The steps involved will be described.

[0037] S100: Obtain a to-be-verified layout corresponding to a standard cell library.

[0038] The standard cell library includes N types of to-be-tested cells with equal heights, and the to-be-verified layout includes N sub-splicing layouts. In the first row and the third row of the i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells are the i-th to-be-tested cell and the mirror image of the i-th to-be-tested cell of the N types of to-be-tested cells, respectively. The second row of the i-th sub-splicing layout includes the i-th to-be-tested cell to the N-th to-be-tested cell, wherein the first row, the second row, and the third row of each sub-splicing layout are spliced in the vertical direction in sequence, the length of the first row and the third row of each sub-splicing layout is greater than the length of the second row thereof, i takes 1 to N in sequence, and i and N are positive integers.

[0039] As shown in Figure 3 , the placement of each to-be-tested cell in the standard cell library has the following four types: horizontal (R0), vertical mirror image (MY), horizontal mirror image (MX), and counterclockwise rotation by 180 degrees (R180), wherein A1, A2, A3, and A4 represent a vertex of the to-be-tested cell.

[0040] The i-th to-be-tested cell and the mirror image of the i-th to-be-tested cell refer to the horizontal and vertical mirror images of the i-th to-be-tested cell, or the horizontal mirror image and the counterclockwise rotation by 180 degrees of the i-th to-be-tested cell.

[0041] It should be noted that when the i-th to-be-tested cell and the mirror image of the i-th to-be-tested cell refer to the horizontal and vertical mirror images of the i-th to-be-tested cell, the placement of the i-th to-be-tested cell to the N-th to-be-tested cell included in the second row of the i-th sub-splicing layout is also the horizontal or vertical mirror image placement. Similarly, when the i-th to-be-tested cell and the mirror image of the i-th to-be-tested cell refer to the horizontal mirror image and the counterclockwise rotation by 180 degrees of the i-th to-be-tested cell, the placement of the i-th to-be-tested cell to the N-th to-be-tested cell included in the second row of the i-th sub-splicing layout is also the horizontal mirror image or the counterclockwise rotation by 180 degrees.

[0042] It is assumed that the A1A2 side of the to-be-tested unit is used for connecting the power supply, and the A3A4 side is used for grounding. In order to avoid the occurrence of open circuit, when the first row, the second row and the third row of each sub-splicing layout are spliced in the vertical direction in turn, the A1A2 side of the to-be-tested unit in the first row needs to be spliced with the A1A2 side of the to-be-tested unit in the second row, and the A3A4 side of the to-be-tested unit in the second row needs to be spliced with the A3A4 side of the to-be-tested unit in the third row; or, the A3A4 side of the to-be-tested unit in the first row needs to be spliced with the A3A4 side of the to-be-tested unit in the second row, and the A1A2 side of the to-be-tested unit in the second row needs to be spliced with the A1A2 side of the to-be-tested unit in the third row. Therefore, in the first row and the third row of each sub-splicing layout, there should be the to-be-tested unit and the longitudinal mirror image of the to-be-tested unit, or there should be the transverse mirror image of the to-be-tested unit and the counterclockwise rotation of 180° of the to-be-tested unit.

[0043] The length of the first row and the third row of each sub-splicing layout is greater than the length of the second row thereof, which can ensure that, in the subsequent verification process, when the second row of each sub-splicing layout moves in a specified direction, the second row of each sub-splicing layout can always be in the vertical projection of the first row of the sub-splicing layout, so as to ensure that each to-be-tested unit of the second row is always completely spliced with the first row, and thus the accuracy of the final verification result is ensured.

[0044] However, if the number of to-be-tested units included in the first row and the third row of the sub-splicing layout is too large, the verification efficiency may be reduced. Therefore, on the basis of ensuring the accuracy of the final verification result, the number of to-be-tested units included in the first row and the third row of each sub-splicing layout needs to be reduced as much as possible. Based on this, the number of to-be-tested units included in the first row and the third row of each sub-splicing layout can have the following two implementation manners.

[0045] In the first implementation manner, the first row and the third row of each sub-splicing layout are longer than the second row thereof by a preset length.

[0046] The preset length can be set according to actual needs. It should be noted that the longer the preset length is, the more times the second row of each sub-splicing layout can be moved subsequently, and the more accurate the verification result obtained is.

[0047] The preset lengths corresponding to different sub-splicing layouts can be the same or different. For example, the longer the length of the to-be-tested unit included in the first row of the sub-splicing layout is, the longer the preset length corresponding to the sub-splicing layout is. The examples are provided herein only for the convenience of understanding, and should not be regarded as a limitation on the present application.

[0048] In the second implementation, the first row of the i-th sub-tile layout in the N sub-tile layouts includes K i-th to-be-tested units, K = [X / Y+3], X is the total length of the second row of the i-th sub-tile layout, Y is the length of the i-th to-be-tested unit, and [X / Y+3] represents rounding X / Y+3.

[0049] For ease of understanding, it is assumed that a standard cell library includes three to-be-tested units, i.e., a first to-be-tested unit, a second to-be-tested unit, and a third to-be-tested unit, and the length of the first to-be-tested unit is 5, the length of the second to-be-tested unit is 7, and the length of the third to-be-tested unit is 9.

[0050] The second row of the first sub-tile layout includes the first to-be-tested unit, the second to-be-tested unit, and the third to-be-tested unit, and thus the length X of the second row of the first sub-tile layout is 5+7+9=21. Since the length Y of the first to-be-tested unit is 5, K = [21 / 5+3] = 7, that is, the first row of the first sub-tile layout includes 7 first to-be-tested units.

[0051] The second row of the second sub-tile layout includes the second to-be-tested unit and the third to-be-tested unit, and thus the length X of the second row of the second sub-tile layout is 7+9=16. Since the length Y of the second to-be-tested unit is 7, K = [16 / 7+3] = 5, and thus the first row of the second sub-tile layout includes 5 second to-be-tested units.

[0052] The second row of the third sub-tile layout includes the third to-be-tested unit, and thus the length X of the second row of the third sub-tile layout is 9. Since the length Y of the third to-be-tested unit is 9, K = [9 / 9+3] = 4, and thus the first row of the third sub-tile layout includes 4 third to-be-tested units.

[0053] The examples are only for ease of understanding and should not be regarded as a limitation on the present application.

[0054] After the length of the first row and the third row of each sub-tile layout is limited, in order to make the second row of the sub-tile layout move a longer distance, the first row and the third row of each sub-tile layout can be aligned in the vertical direction.

[0055] The first row and the third row of each sub-tile layout can be the same or different. For example, the leftmost of the first row of the target sub-tile layout is a target test unit, and then the target test unit and the mirror image of the target test unit are connected according to the rule of any two adjacent test units. At this time, the leftmost of the third row of the target sub-tile layout can be the target test unit, that is, the first row and the third row of the target sub-tile layout are the same. Or, the leftmost of the third row of the target sub-tile layout can be the mirror image of the target test unit, that is, the first row and the third row of the target sub-tile layout are different.

[0056] The second row of the i-th sub-tile layout includes the i-th test unit to the N-th test unit, that is, N-i+1 test units.

[0057] In an embodiment, the N-i+1 test units included in the second row of the i-th sub-tile layout can be sorted in any order.

[0058] For ease of understanding, the standard cell library includes three test units, the first test unit, the second test unit, and the third test unit.

[0059] Then, in the second row of the first sub-tile layout, the first test unit, the second test unit, and the third test unit can be connected in the following order from left to right: the first test unit, the second test unit, and the third test unit; or the first test unit, the third test unit, and the second test unit; or the second test unit, the first test unit, and the third test unit; or the second test unit, the third test unit, and the first test unit; or the third test unit, the first test unit, and the second test unit; or the third test unit, the second test unit, and the first test unit.

[0060] The second test unit, the third test unit, and the first test unit from left to right; or the third test unit, the first test unit, and the second test unit; or the third test unit, the second test unit, and the first test unit.

[0061] Similarly, in the second row of the second sub-tile layout, the second test unit, the third test unit, and the first test unit can be connected in the following order from left to right: the second test unit, the third test unit; or the third test unit, the second test unit.

[0062] The second row of the third sub-tile layout is the third test unit.

[0063] The examples are only for ease of understanding and should not be considered as a limitation of the present application.

[0064] 5In another embodiment, the second row of the ith sub-tiled layout includes the ith type of test cell to the Nth type of test cell arranged in sequence.

[0065] The test cells in the second row of each sub-tiled layout are arranged in sequence.

[0066] It should be understood that the sequence can be from left to right or from right to left.

[0067] For the purpose of illustration, the standard cell library includes the first type of test cell, the second type of test cell, and the third type of test cell.

[0068] If the ith type of test cell to the Nth type of test cell in the second row of the ith sub-tiled layout are arranged in sequence from left to right, then the first type of test cell, the second type of test cell, and the third type of test cell are arranged in sequence from left to right in the second row of the first sub-tiled layout.

[0069] Similarly, the second type of test cell and the third type of test cell are arranged in sequence from left to right in the second row of the second sub-tiled layout. The third type of test cell is arranged in the second row of the third sub-tiled layout.

[0070] If the ith type of test cell to the Nth type of test cell in the second row of the ith sub-tiled layout are arranged in sequence from right to left, then the third type of test cell, the second type of test cell, and the first type of test cell are arranged in sequence from left to right in the second row of the first sub-tiled layout.

[0071] Similarly, the third type of test cell and the second type of test cell are arranged in sequence from left to right in the second row of the second sub-tiled layout. The third type of test cell is arranged in the second row of the third sub-tiled layout.

[0072] The examples are provided for the purpose of illustration only and should not be construed as limiting the present application.

[0073] In one embodiment, the length of the first type of test cell to the Nth type of test cell in the standard cell library is arranged in sequence from left to right.

[0074] Correspondingly, the length of the test cell in the first row of the first sub-tiled layout to the test cell in the first row of the Nth sub-tiled layout is arranged in sequence from left to right.

[0075] For the purpose of subsequent verification of the verification layout, the movable distance of the second row of each sub-tiled layout needs to be determined. The movable distance of the second row of the sub-tiled layout is the distance between the edge of the second row of the sub-tiled layout in the specified direction and the edge of the first row of the sub-tiled layout in the specified direction.

[0076] For example, if the specified direction is left, the movable distance of the second row of the sub-tile layout is the distance from the left edge of the second row of the sub-tile layout to the left edge of the first row of the sub-tile layout. The example is only for the convenience of understanding and should not be regarded as a limitation to the present application.

[0077] When the first row of the i-th sub-tile layout includes K i-th units to be tested, where K = [X / Y+3], X is the total length of the second row of the i-th sub-tile layout, Y is the length of the i-th unit to be tested, and [X / Y+3] represents rounding X / Y+3. At this time, in order to ensure that the movable distance of the second row of the i-th sub-tile layout is long enough, the edge of the second row of the i-th sub-tile layout in the specified direction can be aligned with the edge of the third i-th unit to be tested in the specified direction in the first row of the i-th sub-tile layout.

[0078] For the convenience of understanding, taking the left side as the specified direction, please refer to Figure 4 The left edge of the second row of the i-th sub-tile layout is aligned with the left edge of the third i-th unit to be tested from left to right in the first row of the i-th sub-tile layout.

[0079] For the convenience of understanding the specific structure of the to-be-verified layout, taking a standard cell library including three units to be tested, i.e., unit A to be tested, unit B to be tested, and unit C to be tested, as an example for illustration. The first unit to be tested is unit A to be tested, the second unit to be tested is unit B to be tested, and the third unit to be tested is unit C to be tested.

[0080] The four vertices of unit A to be tested are marked as A1, A2, A3, and A4, the four vertices of unit B to be tested are marked as B1, B2, B3, and B4, and the four vertices of unit C to be tested are marked as C1, C2, C3, and C4.

[0081] Wherein, Figure 5 The length of unit A to be tested is L1, the length of unit B to be tested is L2, and the length of unit C to be tested is L3. Since the lengths of different units to be tested can be equal, it can be L3 = L2 = L1, at this time, the tiling manner of the to-be-verified layout is as shown in Figure 5 .

[0082] The lengths of different units to be tested can also not be completely equal, for example, it can be L3 = L2 > L1, L3 < L2 = L1, L3 > L2 > L1, etc. The lengths of different units to be tested are not limited here. For the convenience of understanding the tiling manner of the to-be-verified layout when the lengths of different units to be tested are not equal, please refer to Figure 6 .

[0083] As shown in Figure 5 ,Figure 5 The first and third rows of the first sub-spliced layout in the to-be-verified layout shown include the first to-be-tested cell and its mirror image, that is, to-be-tested cell A and the mirror image of to-be-tested cell A, wherein to-be-tested cell A and the mirror image of to-be-tested cell A are symmetrical in the vertical direction.

[0084] Figure 5 The second row of the first sub-spliced layout in the to-be-verified layout shown includes the first to third to-be-tested cells, that is, to-be-tested cell A, to-be-tested cell B, and to-be-tested cell C. The splicing order of to-be-tested cell A, to-be-tested cell B, and to-be-tested cell C can be the splicing order shown, that is, to-be-tested cell A, to-be-tested cell B, and to-be-tested cell C are spliced in sequence, or can be any other splicing order, not limited to Figure 5 the splicing manner shown. Figure 5

[0085] Figure 5 The first and third rows of the second sub-spliced layout in the to-be-verified layout shown include the second to-be-tested cell and its mirror image, that is, to-be-tested cell B and the mirror image of to-be-tested cell B. Figure 5 The second row of the second sub-spliced layout in the to-be-verified layout shown includes the second to third to-be-tested cells, that is, to-be-tested cell B and to-be-tested cell C. The splicing order of to-be-tested cell B and to-be-tested cell C can be the splicing order shown, that is, to-be-tested cell B and to-be-tested cell C are spliced in sequence, or can be to-be-tested cell C and to-be-tested cell B spliced in sequence. Figure 5

[0086] Figure 5 The first and third rows of the third sub-spliced layout in the to-be-verified layout shown include the third to-be-tested cell and its mirror image, that is, to-be-tested cell C and the mirror image of to-be-tested cell C. Figure 5 The second row of the third sub-spliced layout in the to-be-verified layout shown includes the third to-be-tested cell, that is, to-be-tested cell C.

[0087] Figure 7 The to-be-verified layout shown is only one of many embodiments of the present application and should not be considered as a limitation of the present application.

[0088] S200: verifying the to-be-verified layout to obtain verification results of the N to-be-tested cells.

[0089] The verification of the to-be-verified layout can have the following two implementation manners.

[0090] ​​In the first implementation, the specific process of verifying the to-be-verified layout can be: first, verifying the to-be-verified layout to obtain a first sub-verification result; then, moving the second row in each sub-spliced layout by a preset step size in a specified direction, verifying the moved to-be-verified layout to obtain a second sub-verification result, and repeating the above steps until a preset condition is met, wherein the verification result includes all the obtained sub-verification results.

[0091] The second row in each sub-spliced layout is moved by a preset step size in a specified direction, that is, the to-be-verified layout is verified once, so that when the verification result is incorrect, the location of the error can be quickly located.

[0092] In the second implementation, the specific process of verifying the to-be-verified layout can be: first, saving the current to-be-verified layout, then moving the second row in each sub-spliced layout by a preset step size in a specified direction, and saving the to-be-verified layout after moving by a preset step size, repeating the above steps until a preset condition is met. Finally, verifying all the saved to-be-verified layouts to obtain a verification result.

[0093] The preset condition in the above two implementations of verifying the to-be-verified layout can be that the second row in each sub-spliced layout is moved by a preset number of times in a specified direction. The preset number of times can be determined according to the movable distance of the second row of the sub-spliced layout, that is, the preset number of times is the movable distance divided by the preset step size. Wherein, the movable distance of the second row of the sub-spliced layout is the distance from the edge of the second row of the sub-spliced layout in the specified direction to the edge of the first row of the sub-spliced layout in the specified direction.

[0094] Optionally, the preset condition in the above two implementations of verifying the to-be-verified layout can also be that the second row in each sub-spliced layout is moved by a preset distance in a specified direction.

[0095] Wherein, the preset distances corresponding to different sub-spliced layouts can be the same or different.

[0096] When the preset distances corresponding to different sub-spliced layouts are the same, the preset distance can be a distance value set in advance.

[0097] When the preset distances corresponding to different sub-spliced layouts are different, the preset distance corresponding to the i-th sub-spliced layout can be y times the length of the i-th to-be-tested unit. Correspondingly, the longer the length of the to-be-tested unit included in the first row of the sub-spliced layout, the longer the corresponding preset distance.

[0098] It can be understood that the preset step sizes corresponding to different sub-spliced layouts included in the same to-be-verified layout can be the same or different.

[0099] In one embodiment, the preset step length can be the minimum precision for moving the layout in the software program used for verifying the layout to be verified. Alternatively, it can also be a preset value, in which case the preset step length corresponding to different sub-tile layouts included in the same layout to be verified is the same.

[0100] In yet another embodiment, the preset step length can be determined according to the length of the unit to be tested, in which case the preset step length corresponding to the i-th sub-tile layout can be 1 / x of the length of the i-th unit to be tested. Correspondingly, the longer the length of the unit to be tested included in the first row of the sub-tile layout, the longer the preset length corresponding thereto.

[0101] For the convenience of understanding the specific implementation of moving the second row in each sub-tile layout by a preset step length in a specified direction, please refer to Figure 7 .

[0102] As shown in Figure 7 , the initial position of the second row of each sub-tile layout included in the layout to be verified is that the leftmost side of the second row is aligned with the left side of the third unit to be tested on the left side of the first row.

[0103] Then, the second row of the first sub-tile layout is moved to the left by a preset step length H1, the second row of the second sub-tile layout is moved to the left by a preset step length H2, and the second row of the third sub-tile layout is moved to the left by a preset step length H3. The above steps are repeated until a preset condition is met, and a verified layout on the right side of Figure 7 is obtained.

[0104] In which, after the second row of each of the first sub-tile layout, the second sub-tile layout and the third sub-tile layout is moved to the left by a preset step length for the last time, the left edge of the second row of each of the first sub-tile layout, the second sub-tile layout and the third sub-tile layout is respectively away from the left edge of the first row corresponding thereto by a preset step length (H1, H2, H3) as shown in Figure 7 . Even if the second row of each of the first sub-tile layout, the second sub-tile layout and the third sub-tile layout is moved to the left by a preset step length again, the stitching manner of the first row and the second row of each sub-tile layout in the obtained layout is consistent with the initial manner. Therefore, the use of this manner can reduce one movement, thereby improving the efficiency of layout verification.

[0105] For example, after the second row of each sub-tile layout in the verified layout satisfying the preset condition in Figure 8 is moved to the left by a preset step length again, the obtained verified layout is as shown in Figure 8 .

[0106] Figure 7The splicing manner of the part surrounded by the dotted line is consistent with Figure 7 The splicing manner of the part surrounded by the dotted line in the verification layout shown on the left is consistent with Figure 1 On the basis of the to-be-verified layout shown on the right, the second row of each sub-splicing layout is moved to the left by a preset step length again, and the verification result is also the same as that when the second row of each sub-splicing layout is not moved. Therefore, when the movement to the alignment is stopped by one step, a group of sub-splicing layouts can be reduced, and the verification efficiency is further improved.

[0107] Here, examples are only for easy understanding, and should not be regarded as a limitation to the present application.

[0108] In order to better understand the technical effects that can be achieved in the present scheme, taking a standard cell library including n to-be-tested cells as an example, n is a positive integer.

[0109] The length of each to-be-tested cell in the standard cell library is set to w, the preset step length is 1, and the preset condition is that if the second row of each sub-splicing layout is moved to the right by the last step, it is repeated with the initial state, and w is a positive integer.

[0110] The prior art is moved according to the above conditions. For easy understanding, please refer to Figure 9 Therefore, the number of to-be-tested cells included in the first sub-splicing layout is: 6n*2w; the number of to-be-tested cells included in the second sub-splicing layout is: 6(n-1)*2w; and the number of to-be-tested cells included in the nth sub-splicing layout is: 6*2w. Therefore, the number of to-be-tested cells finally spliced by the present scheme is 12w*(1+2+…+n)=6nw(1+n)=6w(n 2 +n).

[0111] The to-be-verified layout in the present scheme is moved according to the above conditions. Therefore, the number of to-be-tested cells included in the first sub-splicing layout is: (3n+6)*2w; the number of to-be-tested cells included in the second sub-splicing layout is: (3(n-1)+6)*2w; and the number of to-be-tested cells included in the nth sub-splicing layout is: (3+6)*2w. Therefore, the number of to-be-tested cells finally spliced by the present scheme is 12nw+6w*(1+2+…+n)=12nw+3nw(1+n)=3w(n 2 +5n).

[0112] Therefore, the number of to-be-tested cells required for verification by the new scheme is less than 3wn(n-9) than the number of to-be-tested cells required for verification by the prior art. That is, when the number of to-be-tested cells in the standard cell library is greater than 9, the number of to-be-tested cells required for verification of the standard cell library by the present scheme is less than the number of to-be-tested cells required for verification of the standard cell library by the prior art.

[0113] Based on the same inventive concept, the embodiment of the present application also provides a standard cell library verification device, as shown in the figure, the standard cell library verification device 100 comprises an acquisition module 110 and a verification module 120. Figure 10

[0114] The acquisition module 110 is used for acquiring a to-be-verified layout corresponding to a standard cell library, the standard cell library comprises N kinds of to-be-tested cells with equal height, the to-be-verified layout comprises N sub-splicing layouts, in a first row and a third row of an i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells are respectively an i-th to-be-tested cell and a mirror image of the i-th to-be-tested cell of the N kinds of to-be-tested cells, a second row of the i-th sub-splicing layout comprises the i-th to-be-tested cell to the N-th to-be-tested cell, wherein the first row, the second row and the third row of each sub-splicing layout are spliced in sequence in a vertical direction, the length of the first row and the third row of each sub-splicing layout is greater than the length of the second row thereof, i is sequentially taken as 1 to N, and i and N are positive integers.

[0115] The verification module 120 is used for verifying the to-be-verified layout to obtain a verification result of the N kinds of to-be-tested cells.

[0116] In an implementation form, the verification module 120 is specifically configured to verify the verification layout to obtain a first sub-verification result, move the second row in each sub-splicing layout to a specified direction by a preset step length, verify the moved verification layout to obtain a second sub-verification result, and repeat the above steps until a preset condition is met, wherein the verification result comprises all the sub-verification results obtained.

[0117] The standard cell library verification device 100 provided by the embodiment of the present application has the same implementation principle and technical effects as the foregoing standard cell library verification method embodiment, and for brief description, the part not mentioned in the device embodiment can refer to the corresponding content in the foregoing standard cell library verification method embodiment.

[0118] Please refer to Figure 9 , which is an electronic device 200 provided by the embodiment of the present application. The electronic device 200 comprises a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0119] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to realize the transmission or interaction of data. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used for transceiving data. The memory 220 is used for storing a computer program, such as storing a computer program that is used for implementing the standard cell library verification method provided by the embodiment of the present application. ​ ​The software function module shown in the middle is the standard cell library verification apparatus 100. The standard cell library verification apparatus 100 includes at least one software function module stored in the memory 220 in the form of software or firmware or solidified in the operating system (OS) of the electronic device 200. The processor 240 is configured to execute the executable modules stored in the memory 220, such as the software function modules or computer programs included in the standard cell library verification apparatus 100. At this time, the processor 240 is configured to obtain a to-be-verified layout corresponding to a standard cell library, the standard cell library including N types of to-be-tested cells with equal heights, and the to-be-verified layout including N sub-splicing layouts. In the first row and the third row of an i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells are the i-th to-be-tested cell and a mirror image of the i-th to-be-tested cell of the N types of to-be-tested cells, respectively. The second row of the i-th sub-splicing layout includes the i-th to-be-tested cell to the N-th to-be-tested cell, wherein the first row, the second row, and the third row of each sub-splicing layout are spliced in the vertical direction in sequence, the length of the first row and the third row of each sub-splicing layout is greater than the length of the second row thereof, i is sequentially taken as 1 to N, and i and N are positive integers. The to-be-verified layout is verified to obtain verification results of the N types of to-be-tested cells.

[0120] The memory 220 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), and the like.

[0121] The processor 240 can be an integrated circuit chip with a processing capability of signals. The processor can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; or can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor 240 can be any conventional processor or the like.

[0122] The electronic device 200 described above includes but is not limited to a personal computer, a server, etc.

[0123] The embodiments of the present application also provide a non-volatile computer readable storage medium (hereinafter referred to as a storage medium) having a computer program stored thereon. When the computer program is run by a computer such as the electronic device 200 described above, the standard cell library verification method shown above is executed. The computer readable storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0124] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A standard cell library verification method, characterized by, The method comprises the following steps: obtaining a to-be-verified layout corresponding to a standard cell library, the standard cell library comprising N types of to-be-tested cells with equal height, the to-be-verified layout comprising N sub-splicing layouts, in a first row and a third row of an i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells being an i-th to-be-tested cell and a mirror image of the i-th to-be-tested cell of the N types of to-be-tested cells respectively, a second row of the i-th sub-splicing layout comprising an i-th to-be-tested cell to an N-th to-be-tested cell, wherein the first row, the second row and the third row of each sub-splicing layout are spliced in sequence in a vertical direction, the length of the first row and the third row of each sub-splicing layout is greater than the length of the second row of each sub-splicing layout, i is sequentially 1 to N, i and N are positive integers; verifying the to-be-verified layout to obtain a verification result of the N types of to-be-tested cells; wherein the verifying the to-be-verified layout to obtain the verification result of the N types of to-be-tested cells comprises: verifying the to-be-verified layout to obtain a first sub-verification result; moving the second row of each sub-splicing layout by a preset step length in a specified direction, verifying the moved to-be-verified layout to obtain a second sub-verification result, and repeating the above steps until a preset condition is met, wherein the verification result comprises all the sub-verification results obtained; or the verifying the to-be-verified layout to obtain the verification result of the N types of to-be-tested cells comprises: saving a current to-be-verified layout; moving the second row of each sub-splicing layout by a preset step length in a specified direction, saving the to-be-verified layout after moving by the preset step length, and repeating the above steps until a preset condition is met; verifying all the saved to-be-verified layouts to obtain the verification result.

2. The method of claim 1, wherein, the first row of the i-th sub-splicing layout comprises K i-th to-be-tested cells, K = [X / Y+3], X is a total length of the second row of the i-th sub-splicing layout, Y is a length of the i-th to-be-tested cell, and [X / Y+3] represents rounding X / Y+3.

3. The method of claim 1, wherein, the preset condition is that the second row of each sub-splicing layout is moved by a preset number of times in a specified direction.

4. The method of claim 1, wherein, the i-th to-be-tested cells to the N-th to-be-tested cells included in the second row of the i-th sub-splicing layout are arranged in sequence.

5. The method of claim 1, wherein, the length of the 1st to-be-tested cell to the length of the Nth to-be-tested cell in the standard cell library increase in sequence.

6. A standard cell library verification apparatus, comprising: The method comprises the following steps: An acquisition module is configured to acquire a to-be-verified layout corresponding to a standard cell library, the standard cell library including N types of to-be-tested cells with equal height, and the to-be-verified layout including N sub-splicing layouts, in a first row and a third row of an i-th sub-splicing layout of the N sub-splicing layouts, any two adjacent to-be-tested cells being an i-th to-be-tested cell and a mirror image of the i-th to-be-tested cell of the N types of to-be-tested cells, and a second row of the i-th sub-splicing layout including an i-th to-be-tested cell to an N-th to-be-tested cell, wherein the first row, the second row and the third row of each sub-splicing layout are spliced in sequence in a vertical direction, the length of the first row and the third row of each sub-splicing layout is greater than the length of the second row thereof, i is sequentially taken as 1 to N, and i and N are positive integers. A verification module is configured to verify the to-be-verified layout to obtain a verification result of the N types of to-be-tested cells. The verification module is specifically configured to verify the to-be-verified layout to obtain a first sub-verification result, move the second row in each sub-splicing layout by a preset step length in a specified direction, verify the to-be-verified layout after the movement to obtain a second sub-verification result, and repeat the above steps until a preset condition is met, wherein the verification result includes all the sub-verification results obtained. Alternatively, the verification module is specifically configured to save a current to-be-verified layout, move the second row in each sub-splicing layout by a preset step length in a specified direction, save the to-be-verified layout after the movement by the preset step length, repeat the above steps until a preset condition is met, and verify all the saved to-be-verified layouts to obtain the verification result.

7. An electronic device, comprising: comprise: a memory and a processor, the memory and the processor being connected; the memory is configured to store a program; the processor is configured to call the program stored in the memory to execute the method in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, a computer program is stored thereon, and the computer program is run by a computer to execute the method in any one of claims 1-5.

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