Alignment method, method of manufacturing a mosaic chip structure / filter

Abstract

The application provides an alignment method and a preparation method of a mosaic chip structure / filter, wherein the alignment method comprises the following steps: if alignment pattern marks on the front surface of a wafer of a pixel photosensitive unit are covered, the covered alignment pattern marks are exposed by using a dry etching method before a current photolithography alignment process; and the photolithography alignment process is performed by using a front surface alignment method. The alignment method is used in the preparation method of the mosaic chip structure / filter. The alignment precision is greatly improved by the method. Under the condition of a commonly used photolithography alignment device, the alignment error is less than 1 micron by using the method, and in the preparation process of a single-chip mosaic spectral imaging chip, the position deviation of a thin film filter structure and an imaging chip photosensitive unit caused by the alignment error can be controlled within 10% of the size of the imaging chip photosensitive unit.

Description

Technical Field

[0001] This invention relates to the field of spectral imaging technology, and to an alignment method and a method for fabricating a mosaic chip structure / filter, particularly an alignment method for a mosaic thin film filter structure and an imaging chip photosensitive element, and a method for fabricating a mosaic chip structure / filter. Background Technology

[0002] Spectral imaging technology is a non-destructive detection technique that relies on the reflection of electromagnetic waves from the target to the environment to obtain two-dimensional spatial information and spectral characteristics of the target. It is widely used in satellite remote sensing, laboratory food safety, and industrial production line quality monitoring. Mosaic spectral imaging involves fabricating a thin-film filter beam-splitting structure on each pixel photosensitive element of the imaging chip. The size of each thin-film filter structure is the same as the size of the pixel photosensitive element. The alignment accuracy between the thin-film filter structure and the pixel photosensitive element greatly affects the performance of the mosaic spectral imager.

[0003] The development of monolithic mosaic spectral imaging microsystems provides an effective solution for advancing the application of spectral imaging technology in low-cost industrialization and civilian applications. Monolithic mosaic spectral imaging microsystems offer low mass production costs, simple structures, and high optical coupling efficiency, making them promising for broad applications. In particular, snapshot-type mosaic spectral imaging chips designed for specific applications can achieve customized response spectral bands, maximizing the accuracy of target application scene classification and identification. However, a key issue needs to be addressed in the fabrication of monolithic mosaic spectral imaging chips and other mosaic filter structures: precise alignment between the mosaic thin-film filter structure and the photosensitive element of the imaging chip. Even a slight misalignment means a positional shift between the mosaic thin-film filter structure and the corresponding photosensitive element of the imaging chip, affecting the chip's imaging quality and the accuracy and completeness of the target spectral information. Based on engineering experience, we believe that the positional deviation caused by alignment errors between the mosaic thin-film filter structure and the photosensitive element of the imaging chip should be controlled within 10% of the size of the photosensitive element of the imaging chip.

[0004] The fabrication of a monolithic mosaic spectral imaging chip requires the preparation of a thin-film filter structure corresponding to each pixel on the front side of the imaging chip. Since a bottom-layer mirror is first prepared on the front side of the pixels, this mirror covers the alignment marks. Alternatively, to address issues such as light transmission and filtering, a transition layer may be prepared on the front side of the pixels before preparing the thin-film filter structure, completely covering the alignment marks. Because the alignment marks are covered, conventional practices do not use front-side alignment during chip fabrication; instead, back-side alignment is typically employed for photolithographic alignment. However, this method introduces alignment errors exceeding 3 micrometers. If the photosensitive element size of the imaging chip is between 5 and 15 micrometers, the positional deviation caused by the alignment error will exceed 20%-60% (some mosaic filter structures also suffer from the same problem). Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0006] Therefore, the present invention provides an alignment method and a method for fabricating a mosaic-style chip structure / filter.

[0007] The technical solution of the present invention is as follows:

[0008] According to one aspect, an alignment method is provided for the fabrication process of a mosaic structure, the alignment method comprising:

[0009] Before the current photolithography alignment process, if the alignment pattern marks on the front side of the wafer of the pixel photosensitive unit are covered, the covered alignment pattern marks are exposed by dry etching.

[0010] The photolithography alignment process is performed using a front-side alignment method.

[0011] Furthermore, the method also includes: if the alignment pattern mark is covered again before the next photolithography alignment process, the covered front alignment pattern is exposed by dry etching, and the photolithography alignment process is performed again by front alignment, and so on, until all process flows are completed.

[0012] According to another aspect, a method for fabricating a mosaic-like chip structure is provided, the method comprising:

[0013] The reflector is fabricated on the front side of the wafer of the pixel photosensitive unit.

[0014] The raw material for the light-transmitting layer is integrally deposited on the lower reflector, and the thickness of the resulting deposited structure is the thickness of the highest step of the light-transmitting layer.

[0015] The deposition structure is subjected to multiple processes including photolithography and etching to obtain a light-transmitting layer with a mosaic pattern, including:

[0016] The first photolithography and etching process includes:

[0017] 1) The alignment pattern marks that were covered on the front side of the wafer were exposed by dry etching.

[0018] 2) The photolithography alignment process is performed using a front-side alignment method;

[0019] 3) Etching;

[0020] A second photolithography and etching process is performed, including:

[0021] Determine whether the alignment mark is covered. If so, complete the second photolithography and etching according to steps 1) to 3).

[0022] The remaining photolithography and etching processes are completed sequentially using the second photolithography and etching method to obtain the desired light-transmitting layer;

[0023] A reflector is fabricated on the light-transmitting layer.

[0024] Furthermore, the method for fabricating the mosaic chip structure further includes firstly depositing a first matching layer integrally on the front side of the pixel photosensitive unit wafer, and then integrally depositing the lower reflector on the first matching layer. The first matching layer transitions the optical admittance between the narrowband filter and the pixel photosensitive unit to improve the peak transmittance of the center wavelength. The upper reflector, the light-transmitting layer, and the lower reflector constitute the narrowband filter.

[0025] Furthermore, the method for fabricating the mosaic chip structure also includes integrally depositing a second matching layer on the upper reflector, the second matching layer being used to improve the center wavelength transmittance of the mosaic chip structure.

[0026] Furthermore, the method for fabricating the mosaic chip structure further includes first integrally depositing a third matching layer on the front side of the pixel photosensitive unit wafer, then integrally depositing the lower reflector on the third matching layer; and also integrally depositing a transition layer on the upper reflector, integrally depositing a first cutoff filter film on the transition layer, fabricating a second cutoff filter film on the first cutoff filter film, and fabricating a third cutoff filter film on the second cutoff filter film, wherein:

[0027] The first cutoff filter film, the second cutoff filter film, and the third cutoff filter film are respectively cut off from the first interference band, the second interference band, and the third interference band, and the first interference band, the second interference band, and the third interference band are all different;

[0028] The transition layer is used to transition between the narrowband filter and the cutoff filter. The third matching layer is used to transition between the optical admittance of the photosensitive unit and the narrowband filter, the transition layer and the cutoff filter to improve the peak transmittance of the center wavelength. The upper reflector, the light-transmitting layer and the lower reflector constitute the narrowband filter.

[0029] Furthermore, the method for fabricating the mosaic chip structure further includes integrally depositing the second cutoff filter film on the first cutoff filter, integrally depositing the third cutoff filter film on the second cutoff filter film, or attaching the third cutoff filter film to the second cutoff filter film.

[0030] Furthermore, the method for fabricating the mosaic chip structure also includes attaching the second cutoff filter film onto the first cutoff filter.

[0031] According to another aspect, a method for fabricating a mosaic-style chip filter is provided. The filter includes a substrate, an anti-reflection film, a pixel modulation film structure, and a bandpass noise reduction film. The anti-reflection film, used to improve the transmittance of a desired spectral band of the pixel modulation film structure, is formed on a first side surface of the substrate. The pixel modulation film structure is formed on the anti-reflection film, and the pixel modulation film structure includes multiple periodically arranged filter unit groups. The filter unit groups are 2*2 mosaic structures, wherein a first interference cutoff film, a second interference cutoff film, and two third interference cutoff films are formed on four pixels respectively. The first and second interference cutoff films are arranged diagonally, and the two third interference cutoff films are simultaneously adjacent to the first and second interference cutoff films. The mid-infrared spectral transmission ranges covered by the first, second, and third interference cutoff films are all different. The bandpass noise reduction film, formed on a second side surface of the substrate opposite to the first side surface, is used to remove interference from interfering spectral bands. The fabrication method includes:

[0032] A bandpass noise reduction film is deposited on the second side surface of the substrate;

[0033] Base flipping;

[0034] An antireflective coating is deposited on the first side surface of the substrate;

[0035] Processing a pixel modulation film structure on the antireflective film includes:

[0036] Processing multiple interference-type cutoff films a, wherein the interference-type cutoff film a is any one of a first interference-type cutoff film, a second interference-type cutoff film, and a third interference-type cutoff film, including:

[0037] 11) Use dry etching to expose the alignment pattern marks that were covered on the front side of the substrate;

[0038] 12) The photolithography alignment process is performed using a front-side alignment method;

[0039] 13) Deposit the raw material of the first interference-type cutoff film on the corresponding position of the antireflection film, remove the photoresist, and complete the processing of multiple first interference-type cutoff films;

[0040] Follow steps 11) to 13) to complete the processing of the remaining interference-type cutoff films.

[0041] Furthermore, in the preparation method, multiple first interference-type cutoff films, multiple second interference-type cutoff films, and multiple third interference-type cutoff films are processed in order of increasing total film thickness.

[0042] By applying the above technical solution, when the alignment markings on the front side of the pixel photosensitive unit (substrate) are covered, a dry etching process is introduced to etch away the coating covering the alignment markings. The relevant process flows are then performed using a front-side alignment method (this alignment method is used for both mosaic chip structures and mosaic filters), significantly improving alignment accuracy. Under current photolithography alignment equipment conditions, the method of this invention can achieve an alignment error of less than 1 micrometer. In the fabrication process of a monolithic mosaic spectral imaging chip, the positional deviation between the thin-film filter structure and the photosensitive element of the imaging chip caused by alignment errors can be controlled within 10% of the size of the photosensitive element of the imaging chip. Attached Figure Description

[0043] The accompanying drawings, which form part of this specification, are provided to further illustrate embodiments of the invention and, together with the textual description, explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0044] Figure 1 A flowchart illustrating an alignment method according to an embodiment of the present invention is shown;

[0045] Figure 2 A schematic diagram of the alignment process of the alignment method provided according to an embodiment of the present invention is shown;

[0046] Figure 3 A schematic flowchart of a method for fabricating a mid-infrared spectral imaging filter according to an embodiment of the present invention is shown;

[0047] Figure 4A schematic diagram of the pixel modulation film structure fabrication process provided according to an embodiment of the present invention is shown.

[0048] Figure 5 A schematic diagram of the cross-sectional structure of a mid-infrared spectral imaging filter provided according to an embodiment of the present invention is shown;

[0049] Figure 6 A two-dimensional structural schematic diagram of a filter unit group provided according to an embodiment of the present invention is shown;

[0050] Figure 7 A three-dimensional structural schematic diagram of a filter unit group provided according to an embodiment of the present invention is shown;

[0051] Figure 8 A schematic diagram simulating the transmittance of a pixel modulation film structure according to an embodiment of the present invention is shown; wherein, (a) 3.5–4.2 μm; (b) 4.4–5 μm; (c) 3.5–5 μm

[0052] Figure 9 A schematic diagram simulating the transmittance of a bandpass noise reduction membrane system provided according to an embodiment of the present invention is shown. Detailed Implementation

[0053] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0055] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0056] like Figure 1-2 As shown, in one embodiment of the present invention, an alignment method is provided for the fabrication process of a mosaic structure, the alignment method comprising:

[0057] S1. Before the current photolithography alignment process, if the alignment pattern mark on the front side of the wafer of the pixel photosensitive unit is covered, the covered alignment pattern mark is exposed by dry etching.

[0058] S2. Photolithography alignment is performed using a front-side alignment method.

[0059] In this embodiment of the invention, Figure 2 (a) shows the alignment pattern markings on the front side of the wafer. If they are not obscured, front alignment can be used directly. Figure 2 (b) shows the wafer front alignment pattern being obscured; Figure 2 (c) shows the process of dry etching away the masking coating to reveal the front alignment pattern marks, followed by a second front alignment.

[0060] In other words, as mentioned in the background section, during the fabrication of mosaic structures, alignment markings may be obscured. In such cases, back-side alignment is usually considered. However, because mosaic structures require high alignment precision, back-side alignment would result in extremely large alignment errors. For example, using back-side alignment for photolithography alignment to fabricate thin-film filter structures on the front side of chip pixels can cause alignment errors exceeding 3 micrometers. If the size of the photosensitive element in the imaging chip is between 5 and 15 micrometers, the positional deviation caused by the alignment error would exceed 20%-60%, which is unacceptable.

[0061] The alignment method in this invention involves introducing a dry etching process when the alignment markings on the front of the pixel photosensitive unit are covered. This process removes the coating covering the alignment markings and uses a front-side alignment method for the relevant processes, significantly improving alignment accuracy. Under current photolithography alignment equipment conditions, the method of this invention can achieve an alignment error of less than 1 micrometer. In the fabrication of a monolithic mosaic spectral imaging chip, the positional deviation between the thin-film filter structure and the photosensitive element of the imaging chip caused by alignment errors can be controlled within 10% of the size of the photosensitive element.

[0062] According to one embodiment of the present invention, such as Figure 2 As shown, the alignment method further includes S3: before the next photolithography alignment process, if the alignment pattern mark is covered again, the dry etching method is used to expose the covered front alignment pattern, and the photolithography alignment process is performed again using the front alignment method. This process is repeated until all process flows are completed.

[0063] In this embodiment of the invention, Figure 2 (d) shows that the wafer front alignment pattern marks are again covered by the plating. Figure 2 (e) shows the masking layer being etched away again using a dry etching process, revealing the front alignment pattern, and then continuing the front alignment. It is evident that by employing the embodiment of the present invention, the front alignment method is consistently used throughout the entire related process, further significantly improving alignment accuracy.

[0064] According to one embodiment of the present invention, before step S1, the alignment method may further include preparing a high-precision alignment pattern at a suitable location on the front side of the wafer when there are no alignment marks on the front side of the wafer.

[0065] According to another embodiment of the present invention, a method for fabricating a mosaic-like chip structure is provided, the method comprising:

[0066] S11, A reflector fabricated on the front side of the wafer of the pixel photosensitive unit;

[0067] S12. The raw material of the light-transmitting layer is deposited integrally on the lower reflector, and the thickness of the resulting deposition structure is the thickness of the highest step of the light-transmitting layer.

[0068] S13. Performing multiple photolithography and etching processes on the deposited structure to obtain a light-transmitting layer with a mosaic-like distribution, including:

[0069] S131. Perform the first photolithography and etching, including:

[0070] 1) The alignment pattern marks that were covered on the front side of the wafer were exposed by dry etching.

[0071] 2) The photolithography alignment process is performed using a front-side alignment method;

[0072] 3) Etching;

[0073] S132. Perform a second photolithography and etching process, including:

[0074] Determine whether the alignment mark is covered. If so, complete the second photolithography and etching according to steps 1) to 3).

[0075] S133. Follow the method in step S132 to complete the remaining number of photolithography and etching steps to obtain the desired light-transmitting layer;

[0076] S14. A reflector is fabricated on the light-transmitting layer.

[0077] Those skilled in the art should know that a mosaic chip structure usually refers to a monolithic mosaic chip structure, which is typically designed to include: a pixel photosensitive unit, and a narrowband filter film integrally deposited on the pixel photosensitive unit. The narrowband filter film is used to achieve tunability at the center wavelength of the desired band. The narrowband filter film includes a lower reflector (bottom Bragg mirror), a light-transmitting layer, and an upper reflector (top Bragg mirror), wherein the light-transmitting layer has a mosaic-like stepped structure.

[0078] Furthermore, those skilled in the art should know that performing multiple processes, including photolithography and etching, on the deposited structure obtained from the raw material of the light-transmitting layer to obtain a light-transmitting layer with a mosaic distribution (i.e., a light-transmitting layer with a stepped structure) is a conventional technique in the art. The difference between the embodiments of the present invention and the prior art is that, in the photolithography process, the prior art is limited by the fact that the alignment pattern marks are covered when preparing the mosaic chip structure, and usually adopts the back alignment method, and then performs the etching process on this basis. However, in this application, when the alignment pattern marks are covered, the dry etching method is used to expose the alignment pattern marks covered on the front side of the wafer, and then the front alignment method is used for the photolithography alignment process, and then the etching process is performed on this basis. Moreover, the method of the embodiments of the present invention ensures that the alignment method is always used in the process of preparing the mosaic light-transmitting layer, which greatly reduces the alignment error.

[0079] Furthermore, those skilled in the art should understand that the method described in the embodiments of the present invention according to steps 1) to 3) and step S132... means that front-side photolithography alignment and etching must be performed in each process, but when it comes to specific photolithography and etching locations, each photolithography and process is different.

[0080] As can be seen, in the embodiment of the present invention, a dry etching process is introduced when fabricating the light-transmitting layer of the mosaic chip structure. This process etches away the coating covering the alignment marks on the front side of the pixel photosensitive unit, exposing the alignment pattern marks. This allows for a front-side alignment method in the photolithography alignment process, significantly improving alignment accuracy. Under current photolithography alignment equipment conditions, the method of the present invention can achieve an alignment error of less than 1 micrometer. In the fabrication of a monolithic mosaic spectral imaging chip, the positional deviation between the thin-film filter structure and the photosensitive element of the imaging chip caused by alignment error can be controlled within 10% of the size of the photosensitive element of the imaging chip.

[0081] According to one embodiment of the present invention, the mosaic chip structure can also be a pixel photosensitive unit + a first matching layer + a narrowband filter film. The fabrication method of the mosaic chip structure further includes firstly depositing the first matching layer integrally on the front side of the wafer of the pixel photosensitive unit, and then integrally depositing the lower reflector on the first matching layer. The first matching layer transitions the optical admittance between the narrowband filter film and the pixel photosensitive unit to improve the peak transmittance of the center wavelength. The upper reflector, the light-transmitting layer and the lower reflector constitute the narrowband filter film.

[0082] The mosaic chip structure described in this embodiment of the invention further includes a first matching layer, which is integrally deposited on the pixel photosensitive unit. A narrow-band filter film (lower reflector + light-transmitting layer + upper reflector) is integrally deposited on the first matching layer. As can be seen, since the first matching layer is integrally deposited on the pixel photosensitive unit, when the mosaic chip structure is fabricated, the first matching layer will also cover the alignment pattern mark on the front side of the pixel photosensitive unit wafer. Therefore, in step S13, the first matching layer will be partially removed to expose the alignment pattern mark.

[0083] In this invention, the mosaic-style chip structure integrally deposits a first matching layer onto the pixel photosensitive unit and a narrowband filter onto the first matching layer. There are no gaps between the narrowband filter, the first matching layer, and the pixel photosensitive unit, resulting in high spectral transmittance, reduced energy loss, and a single-stage fabrication process that is unaffected by external environmental contamination, offering better robustness, higher fabrication efficiency, and higher integration. In this invention, because the refractive index difference between the narrowband filter material and the pixel photosensitive unit material of the image sensor is significant during the growth process, direct growth would lead to refractive index mismatch and a decrease in the center wavelength peak transmittance, resulting in low quantum efficiency of the spectral imaging system and affecting imaging performance. Therefore, by setting a matching layer between the pixel photosensitive unit and the narrowband filter, the problem of refractive index mismatch and decreased center wavelength peak transmittance can be effectively overcome, effectively improving the center wavelength peak transmittance of the spectral imaging chip structure. This increases transmittance while reducing bandwidth, allowing for the fabrication of more spectral bands and the acquisition of more spectral lines within a fixed cutoff range. Furthermore, the overlap between adjacent spectral bands is reduced, leading to better resolution during data processing.

[0084] According to one embodiment of the present invention, the film structure Q1 of the first matching layer includes L or HL, where H represents a high refractive index material and L represents a low refractive index material. Specifically, H represents one of the high refractive index materials Ta2O5, Ti3O5, TiO2, Si3N4, and Nb2O5; and L represents one or a mixture of the low refractive index materials SiO2, MgF2, and Al2O3.

[0085] According to one embodiment of the present invention, the structure of the mosaic chip structure can also be a pixel photosensitive unit + a first matching layer + a narrow band filter film + a second matching layer. The method for fabricating the mosaic chip structure further includes integrally depositing the second matching layer on the upper reflector. The second matching layer is used to improve the center wavelength transmittance of the mosaic chip structure.

[0086] This invention introduces a second matching layer based on the first matching layer. The second matching layer is integrally deposited on the narrowband filter film and is used to improve the center wavelength transmittance of the spectral imaging chip structure. In this embodiment, the first matching layer is disposed on the substrate side and the second matching layer is disposed on the air side. The addition of the first and second matching layers improves the filter transmittance while changing the half-width at half-maximum (WHM). Adding the matching layer to the substrate side reduces the WHM, while adding it to the air side increases the WHM. To make the bandwidth with and without the matching layer close to that without the matching layer, the matching layer can be added simultaneously to both the substrate side and the air side, thereby ensuring that the WHM remains unchanged.

[0087] According to one embodiment of the present invention, the film structure Q1 of the first matching layer includes HL or LHL; the film structure Q2 of the second matching layer includes LH or LHL, wherein when Q1 is HL, Q2 is LHL; and when Q1 is LHL, Q2 is LH. Wherein, H represents one of the high refractive index materials Ta2O5, Ti3O5, TiO2, Si3N4, and Nb2O5; and L represents one or a mixture of the low refractive index materials SiO2, MgF2, and Al2O3.

[0088] According to one embodiment of the present invention, the mosaic chip structure may further comprise a pixel photosensitive unit + a third matching layer + a narrowband filter film + a transition layer + a first cutoff filter film + a second cutoff filter film + a third cutoff filter film. The method for fabricating the mosaic chip structure further includes...

[0089] First, a third matching layer is deposited integrally on the front side of the pixel photosensitive unit wafer.

[0090] The lower mirror is then integrally deposited on the third matching layer;

[0091] Furthermore, a transition layer is integrally deposited on the upper reflector, a first cutoff filter film is integrally deposited on the transition layer, a second cutoff filter film is fabricated on the first cutoff filter film, and a third cutoff filter film is fabricated on the second cutoff filter film, wherein:

[0092] The first cutoff filter film, the second cutoff filter film, and the third cutoff filter film are respectively cut off from the first interference band, the second interference band, and the third interference band, and the first interference band, the second interference band, and the third interference band are all different;

[0093] The transition layer is used to transition between the narrowband filter and the cutoff filter. The third matching layer is used to transition between the optical admittance of the photosensitive unit and the narrowband filter, the transition layer and the cutoff filter to improve the peak transmittance of the center wavelength. The upper reflector, the light-transmitting layer and the lower reflector constitute the narrowband filter.

[0094] In this embodiment of the invention, the mosaic-style chip structure integrally deposits a third matching layer on the pixel photosensitive unit, a narrowband filter on the third matching layer, a transition layer on the narrowband filter, and a first cutoff filter on the transition layer. There are no gaps between the first cutoff filter, the transition layer, the narrowband filter, the third matching layer, and the pixel photosensitive unit, resulting in high spectral transmittance, reduced energy loss, and a single-stage fabrication process that is unaffected by external environmental contamination, offering better robustness, higher fabrication efficiency, and higher integration. Fabricating the second cutoff filter on the first cutoff filter and the third cutoff filter on the second cutoff filter broadens the cutoff range of the interference band. Furthermore, since the narrowband filter and the cutoff filter have different equivalent refractive indices, direct superposition would affect peak transmittance. By setting a transition layer between the narrowband filter and the cutoff filter, the peak transmittance of the spectral imaging chip structure can be effectively improved. Furthermore, during the growth of the narrowband filter, the refractive index difference between the film material and the pixel photosensitive unit material of the image sensor is significant. Direct growth will lead to refractive index mismatch and a decrease in the peak transmittance at the center wavelength, resulting in low quantum efficiency of the spectral imaging system and affecting the imaging effect. Therefore, by setting a third matching layer between the pixel photosensitive unit and the narrowband filter, the problem of refractive index mismatch and the decrease in peak transmittance at the center wavelength can be effectively overcome, and the peak transmittance at the center wavelength of the spectral imaging chip structure can be effectively improved.

[0095] According to one embodiment of the present invention, the mosaic chip structure may further be a pixel photosensitive unit + a third matching layer + a narrowband filter film + a transition layer + a first cutoff filter film + a second cutoff filter film + a third cutoff filter film. The method for fabricating the mosaic chip structure further includes integrally depositing the second cutoff filter film on the first cutoff filter film, integrally depositing the third cutoff filter film on the second cutoff filter film, or attaching the third cutoff filter film on the second cutoff filter film.

[0096] In this embodiment of the invention, by integrally depositing the second cutoff filter film on the first cutoff filter and then integrally depositing the third cutoff filter film on the second cutoff filter film, the cutoff effect can be better guaranteed. By integrally depositing the second cutoff filter film on the first cutoff filter and then attaching the third cutoff filter film to the second cutoff filter film, the processing technology is further simplified while ensuring the cutoff effect.

[0097] According to one embodiment of the present invention, the mosaic chip structure can further be configured as a pixel photosensitive unit + a third matching layer + a narrowband filter film + a transition layer + a first cutoff filter film + a second cutoff filter film + a third cutoff filter film. The fabrication method of the mosaic chip structure further includes attaching the second cutoff filter film onto the first cutoff filter. This configuration greatly simplifies the manufacturing process while ensuring the cutoff effect.

[0098] For example, the membrane structure of the transition layer can be L, where L is a low refractive index material.

[0099] Furthermore, those skilled in the art will know that the general membrane structure of a cutoff filter membrane is (HL)^nH, and the first, second, and third cutoff filter membranes mentioned above can all adopt this structure.

[0100] like Figure 3-7 As shown, according to another embodiment of the present invention, a method for fabricating a mosaic chip filter is provided. The filter includes a substrate, an anti-reflection film, a pixel modulation film structure, and a bandpass noise reduction film. The anti-reflection film, used to improve the transmittance of the desired spectral band of the pixel modulation film structure, is formed on a first side surface of the substrate. The pixel modulation film structure is formed on the anti-reflection film, and the pixel modulation film structure includes multiple periodically arranged filter unit groups. The filter unit group is a 2*2 mosaic structure, wherein a first interference cutoff film, a second interference cutoff film, and two third interference cutoff films are formed on four pixels respectively. The first and second interference cutoff films are arranged diagonally, and the two third interference cutoff films are simultaneously adjacent to the first and second interference cutoff films. The mid-wave infrared spectral transmission ranges covered by the first, second, and third interference cutoff films are all different. The bandpass noise reduction film, formed on a second side surface of the substrate opposite to the first side surface, is used to remove interference from the interfering spectral band. The fabrication method includes:

[0101] S21. Deposit a bandpass noise reduction film on the second side surface of the substrate;

[0102] S22, Base flipping;

[0103] S23. Deposit an antireflection film on the first side surface of the substrate;

[0104] S24. Processing a pixel modulation film structure on the antireflective film, including:

[0105] Processing multiple interference-type cutoff films a, wherein the interference-type cutoff film a is any one of a first interference-type cutoff film, a second interference-type cutoff film, and a third interference-type cutoff film, including:

[0106] 11) Use dry etching to expose the alignment pattern marks that were covered on the front side of the substrate;

[0107] 12) The photolithography alignment process is performed using a front-side alignment method;

[0108] 13) Deposit the raw material of the first interference-type cutoff film on the corresponding position of the antireflection film, remove the photoresist, and complete the processing of multiple interference-type cutoff films a;

[0109] S25. Following steps 11) to 13), complete the processing of the remaining interference-type cutoff films.

[0110] In this embodiment of the invention, the pixel modulation film structure is a pixel-level spectral modulation interference cutoff film system structure arranged in a Bayer-like array. The first interference cutoff film, the second interference cutoff film, and the third interference cutoff film correspond to three spectral bands, namely spectral band A, spectral band B, and spectral band C. The three spectral bands are arranged in a Bayer-like array structure, with a 2×2 pixel structure as a filter unit group. In a filter unit group, there are spectral bands A and B and two spectral bands C. Among them, spectral bands A and B are arranged diagonally, and the two spectral bands C are adjacent to spectral bands A and B.

[0111] This invention provides a monolithic, integrated filter structure with high signal-to-noise ratio by forming complementary bandpass noise reduction films and pixel modulation films on both sides of a substrate. The pixel modulation film structure is designed as a 2x2 mosaic structure, with specific design details: the first, second, and third interferometric cutoff films cover different mid-wave infrared spectral transmission ranges, resulting in a filter structure with a high signal-to-noise ratio. In this embodiment, the infrared spectral imaging filter is a pixel-level modulation structure interferometric filter. Based on this filter, a staring imaging detector is formed, enabling spectral modulation of infrared image information of the target scene. In reconnaissance and early warning, the spectral information is used to identify targets, achieving high-accuracy target identification based on a staring infrared image detector. This also enhances anti-interference capabilities, reduces false alarm rates, promotes the development of intelligent military detection technology, and lays the foundation for the development of infrared staring spectral imaging technology.

[0112] Furthermore, since the antireflective coating is integrally deposited on the substrate, the alignment pattern marks on the substrate are obscured. To achieve precise fabrication of the pixel modulation film structure, this embodiment of the invention introduces a dry etching process in the mosaic pattern fabrication to etch away the antireflective coating obscuring the alignment marks on the front side of the pixel photosensitive unit, thus exposing the alignment pattern marks. This allows for front-side alignment during the photolithography alignment process, significantly improving alignment accuracy. Under current commonly used photolithography alignment equipment conditions, the method of this invention can achieve an alignment error of less than 1 micrometer.

[0113] According to one embodiment of the present invention, in the preparation method, multiple first interference-type stop films, multiple second interference-type stop films, and multiple third interference-type stop films are processed in ascending order of total film thickness. This configuration avoids the inability to form vertical columnar structures at the film edges during deposition, reducing the impact of deposition and ensuring stable film growth.

[0114] Furthermore, the filter obtained by the method for fabricating the mosaic chip filter according to the embodiments of the present invention also includes the following features:

[0115] According to one embodiment of the present invention, in order to ensure that the infrared staring spectral imaging detector formed by the filter-bonded staring imaging detector of the present invention can better achieve the following functions: spectral modulation of infrared image information of the target scene, judgment of target objects through spectral information in reconnaissance and early warning, strengthening anti-interference ability and reducing false alarm rate, the spectral transmission range covered by the first interferometric cutoff film is 3.5 to 4.2 μm; the spectral transmission range covered by the second interferometric cutoff film is 4.4 to 5 μm; the spectral transmission range covered by the third interferometric cutoff film is 3.5 to 5 μm; and the bandpass denoising film is a uniform 3.5 to 5 μm bandpass film structure covering the entire pixel array.

[0116] In this embodiment of the invention, the C-band is the full-transmittance band of the detector's response range. That is, for a mid-wave staring detector, the average transmittance of the C-band in the 3.5-5 micrometer spectral range is over 80%. The A and B-bands have complementary transmittance ranges in the full 3.5-5 micrometer spectral range. This design ensures that the infrared staring spectral imaging detector formed by the filter-bonded staring imaging detector in this embodiment of the invention can better achieve the above-mentioned functions.

[0117] According to one embodiment of the present invention, in order to achieve tunable filtering at the center of the desired band, the film structure of the first interference cutoff film is Sub|((0.5LH 0.5L)^S1)|Air, where Sub is the substrate material, Air is air, H is the high refractive index material Ge, L is the low refractive index material, and S1 = 4-7.

[0118] According to one embodiment of the present invention, in order to achieve tunable filtering at the center of the desired band, the film structure of the second interference-type cutoff film is Sub|((0.5LH 0.5L)^S2)|Air, where Sub is the substrate material, Air is air, H is a high refractive index material, L is a low refractive index material, and S2 = 4-7.

[0119] According to one embodiment of the present invention, in order to achieve tunable filtering at the center of the desired band, the film structure of the third interference-type cutoff film is Sub|HL|Air, where Sub is the substrate material, Air is air, H is a high refractive index material, and L is a low refractive index material.

[0120] According to one embodiment of the present invention, in order to achieve tunable filtering at the center of the desired band, the film structure of the bandpass noise reduction film is Sub|(0.5HL0.5H)^S3 n((0.5LH0.5L)^S4)|Air, where Sub is the substrate material, Air is air, H is a high refractive index material, L is a low refractive index material, S3=4-7, S4=4-7, and n=2-3.

[0121] According to one embodiment of the present invention, in order to better achieve tunable filtering at the center of the desired band, the high refractive index material in the film structure of the first interference cutoff film, the second interference cutoff film, the third interference cutoff film and the bandpass noise reduction film is Ge, and the low refractive index material is ZnS.

[0122] According to one embodiment of the present invention, in order to obtain a mid-infrared spectral imaging filter with the above-mentioned performance, the substrate may be a double-sided polished silicon wafer or a germanium wafer.

[0123] like Figure 5-9As shown in the figure, as a specific embodiment of the present invention, this embodiment provides a mid-infrared spectral imaging filter. This filter is a pixel-level spectral modulation filter structure that can be bonded to an infrared staring spectral imaging detector. It uses a silicon or germanium wafer as a substrate, with one side processed with a full-range noise reduction bandpass film system; the other side is first processed with an anti-reflection film system, and then a pixel-level spectral modulation structure is processed on the anti-reflection film system, forming a monolithic integrated filter structure with a high signal-to-noise ratio. The filter consists of three spectral bands in the mid-infrared range of 3.5–5 μm: band A, band B, and band C. The three spectral bands are arranged in a Bayer-like array structure: a 2×2 pixel structure is formed by a filter unit group. Each filter unit group includes one band A, one band B diagonally opposite to band A, and two bands C adjacent to band A (band B). Each pixel is 30×30 μm in size, and each filter contains 320×256 pixels. In this design, spectral bands A and B each cover a portion of the 3.5–5 μm range. The transmission ranges of spectral bands A and B within this range are complementary: spectral band A has a transmission range of 3.5–4.2 μm, while spectral band B has a transmission range of 4.4–5 μm. Spectral band C transmits across the entire mid-infrared range of 3.5–5 μm. To achieve this, spectral bands A and B cover a portion of the 3.5–5 μm range, and their transmission ranges are complementary, the optimized film structures for the first, second, and third interference-type cutoff films, as well as the bandpass noise reduction film, are shown in Table 1-4.

[0124] Table 1 Optimized film structure of the first type of interference-type cutoff thin film

[0125] membrane Material Thickness (nm) 1 ZnS 678.14 2 Ge 337.82 3 ZnS 560.37 4 Ge 326.93 5 ZnS 582.77 6 Ge 285.66 7 ZnS 641.78 8 Ge 304.29 9 ZnS 534.29 10 Ge 327.78 11 ZnS 257.77

[0126] Table 2 Optimized Film Structures for Second Interference-Type Cutoff Thin Films

[0127] membrane Material Thickness (nm) 1 Ge 226.13 2 ZnS 333.3 3 Ge 153.37 4 ZnS 385.29 5 Ge 210.32 6 ZnS 388.02 7 Ge 184.37 8 ZnS 360.69 9 Ge 205.11 10 ZnS 435.88 11 Ge 214.76 12 ZnS 319.21 13 Ge 118.18

[0128] Table 3. Optimized film structure of the third type of interference-type cutoff thin film.

[0129] membrane Material Thickness (nm) 1 Ge 447.98 2 ZnS 453.11

[0130] Table 4 Optimized Membrane Structures for Bandpass Noise Reduction Films

[0131] membrane Material Thickness (nm) 1 Ge 93.56 2 ZnS 201.65 3 Ge 108.29 4 ZnS 281.42 5 Ge 122.92 6 ZnS 280.38 7 Ge 111.76 8 ZnS 264.43 9 Ge 140.15 10 ZnS 285.98 11 Ge 54.16 12 ZnS 441.09 13 Ge 420.3 14 ZnS 703.86 15 Ge 362.45 16 ZnS 719.11 17 Ge 349.34 18 ZnS 721.58 19 Ge 349.41 20 ZnS 750 21 Ge 320.69 22 ZnS 342.63

[0132] That is, for the first interference-type cutoff thin film, in preferred example S1=5, the thickness of each layer of the film system is further optimized. The optimized film layer thicknesses are shown in Table 1, with a center wavelength of 5400nm and simulated transmittance as shown in Table 1. Figure 8As shown in (a). The second interference-type cutoff thin film, preferably with S2=6, was further optimized in terms of the thickness of each layer. The optimized film layer thicknesses are shown in Table 2, with a center wavelength of 3350nm. Transmittance simulation is as follows... Figure 8 As shown in (b). The second interference-type cutoff film, with optimized thicknesses for each layer, is shown in Table 3. The center wavelength is 4300 nm. Transmittance simulations are as follows: Figure 8 As shown in (c). For the bandpass noise reduction film, in preferred examples S3=5, S4=5, n=2.8, the thickness of each layer of the film system was optimized. The optimized film layer thicknesses are shown in Table 4. The center wavelength is 2300nm, and the simulated transmittance is as follows. Figure 9 As shown, the optimized membrane structure exhibits an average transmittance exceeding 80% in all spectral bands within the transmittance range and an average cutoff rate of 95% in the cutoff spectral band.

[0133] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0134] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.

[0135] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a mosaic-like chip structure, characterized in that, The preparation method includes: The reflector is fabricated on the front side of the wafer of the pixel photosensitive unit. The raw material for the light-transmitting layer is integrally deposited on the lower reflector, and the thickness of the resulting deposited structure is the thickness of the highest step of the light-transmitting layer. The deposition structure is subjected to multiple processes including photolithography and etching to obtain a light-transmitting layer with a mosaic pattern, including: The first photolithography and etching process includes: 1) The alignment pattern marks that were covered on the front side of the wafer were exposed using a dry etching method; 2) The photolithography alignment process is performed using a front-side alignment method; 3) Etching; A second photolithography and etching process is performed, including: Determine whether the alignment pattern mark is covered. If so, follow steps 1) to 3) to complete the second photolithography and etching. The remaining photolithography and etching processes are completed sequentially using the second photolithography and etching method to obtain the desired light-transmitting layer; A reflector is fabricated on the light-transmitting layer; The method for fabricating the mosaic chip structure further includes firstly depositing a first matching layer integrally on the front side of the pixel photosensitive unit wafer, and then integrally depositing the lower reflector on the first matching layer. The first matching layer transitions the optical admittance between the narrowband filter and the pixel photosensitive unit to improve the peak transmittance of the center wavelength. The upper reflector, the light-transmitting layer and the lower reflector constitute the narrowband filter. The method for fabricating the mosaic chip structure further includes integrally depositing a second matching layer on the upper reflector, the second matching layer being used to improve the center wavelength transmittance of the mosaic chip structure; The method for fabricating the mosaic chip structure further includes first integrally depositing a third matching layer on the front side of the pixel photosensitive unit wafer, then integrally depositing the lower reflector on the third matching layer; and also integrally depositing a transition layer on the upper reflector, integrally depositing a first cutoff filter film on the transition layer, fabricating a second cutoff filter film on the first cutoff filter film, and fabricating a third cutoff filter film on the second cutoff filter film, wherein: The first cutoff filter film, the second cutoff filter film, and the third cutoff filter film are respectively cut off from the first interference band, the second interference band, and the third interference band, and the first interference band, the second interference band, and the third interference band are all different; The transition layer is used to transition between the narrowband filter and the cutoff filter. The third matching layer is used to transition between the optical admittance of the photosensitive unit and the narrowband filter, the transition layer and the cutoff filter to improve the peak transmittance of the center wavelength. The upper reflector, the light-transmitting layer and the lower reflector constitute the narrowband filter.

2. The method for fabricating a mosaic-like chip structure according to claim 1, characterized in that, The method for fabricating the mosaic chip structure further includes integrally depositing the second cutoff filter film on the first cutoff filter, integrally depositing the third cutoff filter film on the second cutoff filter film, or attaching the third cutoff filter film to the second cutoff filter film.

3. The method for fabricating a mosaic-like chip structure according to claim 1, characterized in that, The method for fabricating the mosaic-like chip structure further includes attaching the second cutoff filter film onto the first cutoff filter.

4. A method for fabricating a mosaic-style chip filter, characterized in that, The filter includes a substrate, an antireflection film, a pixel modulation film structure, and a bandpass noise reduction film. The antireflection film, formed on a first side surface of the substrate, is used to improve the transmittance of the pixel modulation film structure in the desired spectral band. The pixel modulation film structure is formed on the antireflection film and includes multiple periodically arranged filter unit groups. The filter unit group is a 2*2 mosaic structure, wherein a first interference cutoff film, a second interference cutoff film, and two third interference cutoff films are formed on four pixels respectively. The first and second interference cutoff films are arranged diagonally, and the two third interference cutoff films are simultaneously arranged adjacent to the first and second interference cutoff films. The mid-wave infrared spectral transmission ranges covered by the first, second, and third interference cutoff films are all different. The bandpass noise reduction film, formed on a second side surface of a substrate opposite to the first side surface, is used to remove interference in the interfering spectral band. The preparation method includes: A bandpass noise reduction film is deposited on the second side surface of the substrate; Base flipping; An antireflective coating is deposited on the first side surface of the substrate; Processing a pixel modulation film structure on the antireflection film includes: Processing multiple interference-type cutoff films a, wherein the interference-type cutoff film a is any one of a first interference-type cutoff film, a second interference-type cutoff film, and a third interference-type cutoff film, including: 11) Use dry etching to expose the alignment pattern marks that were covered on the front side of the substrate; 12) The photolithography alignment process is performed using a front-side alignment method; 13) Deposit the raw material of the first interference-type cutoff film on the corresponding position of the antireflection film, remove the photoresist, and complete the processing of multiple first interference-type cutoff films; Follow steps 11) to 13) to complete the processing of the remaining interference-type cutoff films.

5. The method for fabricating a mosaic chip filter according to claim 4, characterized in that, In the preparation method, multiple first interference-type cutoff films, multiple second interference-type cutoff films, and multiple third interference-type cutoff films are processed in order of increasing total film thickness.

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