Semiconductor device, method for manufacturing semiconductor device, and electronic device

Abstract

The application provides a semiconductor device, a preparation method of the semiconductor device and an electronic equipment, and relates to the technical field of semiconductors.The semiconductor device comprises a high-voltage depletion type silicon carbide junction field effect transistor, a low-voltage enhancement type gallium nitride high electron mobility transistor, and a first gate, a first drain and a first source; the low-voltage enhancement type gallium nitride high electron mobility transistor comprises a second gate, a second drain and a second source; wherein the first gate is connected with the second source, and the first source is connected with the second drain; the source of the semiconductor device is the second source, the gate of the semiconductor device is the second gate, and the drain of the semiconductor device is the first drain.The semiconductor device is of a common source and common gate structure, combines the advantages of a fast GaN switch and a high breakdown voltage of SiC, and effectively improves the working efficiency and reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for fabricating a semiconductor device, and an electronic device. Background Technology

[0002] Silicon carbide (SiC) power semiconductors can operate in high switching frequency scenarios and have advantages such as low power consumption, long life, high frequency, small size, and light weight. They have strong development potential in the fields of rail transit, communications, and photovoltaics.

[0003] Several SiC power devices have been commercialized, such as junction field-effect transistors (JFETs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to SiC MOSFETs, SiC JFETs offer higher channel mobility and lower manufacturing process requirements, as they do not involve the fabrication of gate oxides. However, SiC JFETs suffer from low operational reliability and significant safety risks.

[0004] Currently, the normally-off operation of SiC JFETs can be achieved through cascode configuration, where a low-voltage Si MOSFET is connected between the gate and power supply of the high-voltage SiC JFET. However, the relatively slow switching speed and limited operating temperature of Si MOSFET devices hinder the realization of SiC JFET functionality, thereby affecting the operating efficiency and reliability of semiconductor devices. Summary of the Invention

[0005] This invention provides a semiconductor device, a method for fabricating a semiconductor device, and an electronic device to improve the working efficiency and reliability of the semiconductor device.

[0006] This invention provides a semiconductor device, comprising:

[0007] A high-voltage depletion-type silicon carbide junction field-effect transistor, wherein the high-voltage depletion-type silicon carbide junction field-effect transistor includes a first gate, a first drain, and a first source;

[0008] A low-voltage enhancement-mode gallium nitride high electron mobility transistor, the low-voltage enhancement-mode gallium nitride high electron mobility transistor including a second gate, a second drain and a second source;

[0009] Wherein, the first gate and the second source are connected, the first source and the second drain are connected, the source of the semiconductor device is the second source, the gate of the semiconductor device is the second gate, and the drain of the semiconductor device is the first drain.

[0010] According to a semiconductor device provided by the present invention, the high-voltage depletion-type silicon carbide junction field-effect transistor includes a first gate region and a first source region, the first gate is connected to the first gate region, the first source is connected to the first source region, and a first abrupt junction is provided between the first gate region and the first source region.

[0011] According to a semiconductor device provided by the present invention, the operating modes of the semiconductor device include a first forward blocking mode. In the first forward blocking mode, the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, and the high-voltage depletion-mode silicon carbide junction field-effect transistor is turned on. The drain-source voltage of the semiconductor device is the voltage that the low-voltage enhancement-mode gallium nitride high electron mobility transistor withstands.

[0012] According to a semiconductor device provided by the present invention, the operating mode of the semiconductor device includes a second forward blocking mode. In the second forward blocking mode, both the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field-effect transistor are turned off. The drain-source voltage of the semiconductor device is the voltage that the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field-effect transistor withstand.

[0013] According to a semiconductor device provided by the present invention, the operating modes of the semiconductor device include a first forward conduction mode, in which both the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field-effect transistor are turned on.

[0014] According to a semiconductor device provided by the present invention, it further includes: a first metal connection structure and a second metal connection structure, wherein the first gate and the second source are connected through the first metal connection structure, and the first source and the second drain are connected through the second metal connection structure.

[0015] The present invention also provides a method for fabricating the above-mentioned semiconductor device, comprising:

[0016] GaN, AlGaN and P-GaN layers are sequentially grown in the first region of the SiC substrate.

[0017] In the second region of the SiC substrate, a p-type junction extension region, a p-type gate contact region, an n-type drift region, and an n-type source contact region are formed by photolithography and ion implantation.

[0018] Etching is performed in the first region and the second region to form a low-voltage enhancement-mode gallium nitride high electron mobility transistor and a high-voltage depletion-mode silicon carbide junction field-effect transistor, respectively.

[0019] A semiconductor device is obtained by connecting the first gate of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second source of the low-voltage enhancement-type gallium nitride high electron mobility transistor, and by connecting the first source of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second drain of the low-voltage enhancement-type gallium nitride high electron mobility transistor.

[0020] According to a method for fabricating a semiconductor device provided by the present invention, a first abrupt junction is provided between the p-type gate contact region and the n-type source contact region.

[0021] According to a method for fabricating a semiconductor device provided by the present invention, the method of connecting the first gate of the high-voltage depletion-mode silicon carbide junction field-effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion-mode silicon carbide junction field-effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, comprises:

[0022] A first metal connection structure and a second metal connection structure are formed by metal deposition. The first gate and the second source are connected through the first metal connection structure, and the first source and the second drain are connected through the second metal connection structure.

[0023] The present invention also provides an electronic device comprising the semiconductor device as described in any of the preceding claims.

[0024] The semiconductor device, semiconductor device fabrication method, and electronic device provided by this invention integrate a high-voltage depletion-mode silicon carbide junction field-effect transistor and a low-voltage enhancement-mode gallium nitride high electron mobility transistor into a single device through structural design, resulting in a cascode semiconductor device. This semiconductor device combines the advantages of GaN's fast switching speed and SiC's high breakdown voltage, effectively improving the working efficiency and reliability of the semiconductor device. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1This is a schematic diagram of the circuit structure of the semiconductor device provided by the present invention;

[0027] Figure 2 This is one of the three-dimensional structural schematic diagrams of the semiconductor device provided by the present invention;

[0028] Figure 3 This is the second three-dimensional structural schematic diagram of the semiconductor device provided by the present invention;

[0029] Figure 4 This is the third three-dimensional structural schematic diagram of the semiconductor device provided by the present invention;

[0030] Figure 5 This is the fourth three-dimensional structural schematic diagram of the semiconductor device provided by the present invention;

[0031] Figure 6 This is a top view of the semiconductor device provided by the present invention;

[0032] Figure 7 This is a schematic flowchart of the semiconductor device fabrication method provided by the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] In the description of the embodiments of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0036] In embodiments of the present invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0038] The following is combined Figures 1 to 6 A semiconductor device according to an embodiment of the present invention is described.

[0039] A high electron mobility transistor (HEMT) is a heterojunction field-effect transistor with high mobility.

[0040] The semiconductor devices provided in this invention include high-voltage depletion-mode silicon carbide junction field-effect transistors (D-mode SiC JFETs) and low-voltage enhancement-mode gallium nitride high electron mobility transistors (E-mode GaN HEMTs).

[0041] The high-voltage depletion-type silicon carbide junction field-effect transistor includes a first gate, a first drain, and a first source.

[0042] The low-voltage enhancement-mode gallium nitride high electron mobility transistor includes a second gate, a second drain, and a second source.

[0043] In this embodiment, the first gate of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second source of the low-voltage enhancement-type gallium nitride high electron mobility transistor are connected, and the source of the semiconductor device integrating the high-voltage depletion-type silicon carbide junction field-effect transistor and the low-voltage enhancement-type gallium nitride high electron mobility transistor is the second source.

[0044] The first source of a high-voltage depletion-type silicon carbide junction field-effect transistor and the second drain of a low-voltage enhancement-type gallium nitride high electron mobility transistor are connected.

[0045] The gate of the semiconductor device integrating the high-voltage depletion-type silicon carbide junction field-effect transistor and the low-voltage enhancement-type gallium nitride high electron mobility transistor is the second gate, and the drain is the first drain.

[0046] For example, such as Figure 1 As shown, e-GaN represents the low-voltage enhancement-mode gallium nitride high electron mobility transistor side, and SiCJFET represents the high-voltage depletion-mode silicon carbide junction field-effect transistor side.

[0047] G JFET D JFET and S JFET These correspond to the first gate, first drain, and first source of a high-voltage depletion-type silicon carbide junction field-effect transistor, respectively.

[0048] G GaN D GaN and S GaN These correspond to the second gate, second drain, and second source of a low-voltage enhancement-mode gallium nitride high electron mobility transistor, respectively.

[0049] First gate G JFET Second source pole S GaN Connection, first source S JFET Second drain D GaN The connection, the source of the semiconductor device is the second source S GaN The gate of the semiconductor device is the second gate G. GaN The drain of the semiconductor device is the first drain D. JFET This forms a semiconductor device with a common source and common gate structure (i.e., Cascode type).

[0050] According to the semiconductor device provided in the embodiments of the present invention, a high-voltage depletion-mode silicon carbide junction field-effect transistor and a low-voltage enhancement-mode gallium nitride high electron mobility transistor are integrated into one device through structural design, resulting in a common-source, common-gate semiconductor device. This semiconductor device combines the advantages of GaN's fast switching speed and SiC's high breakdown voltage, which can effectively improve the working efficiency and reliability of the semiconductor device.

[0051] In some embodiments, a high-voltage depletion-type silicon carbide junction field-effect transistor includes a first gate region and a first source region, the first gate is connected to the first gate region, the first source is connected to the first source region, and a first abrupt junction is provided between the first gate region and the first source region.

[0052] The first gate region is connected to the first gate. The first gate region is a P-type doped silicon carbide region in a high-voltage depletion-mode silicon carbide junction field-effect transistor. For example, the first gate region can be as follows: Figure 6 The P+SiC region shown.

[0053] The first source region is connected to the first source. The first source region is an N-type doped silicon carbide region in a high-voltage depletion-mode silicon carbide junction field-effect transistor. For example, the first source region is as follows: Figure 6 The N+SiC region shown.

[0054] Understandably, the saturated drain current density increases dramatically as the junction between the gate and the channel becomes more abrupt.

[0055] In this embodiment, a first abrupt junction is provided between the first gate region and the first source region. The high-voltage depletion-type silicon carbide junction field-effect transistor becomes a junction field-effect transistor with an abrupt junction between the gate and the channel, which can increase the drain current density and reduce the on-resistance.

[0056] A sudden junction occurs at the interface where the impurity concentration abruptly changes from the acceptor impurity concentration to the donor impurity concentration, while a gradual junction occurs when the impurity concentration changes gradually from the acceptor impurity region to the donor impurity region.

[0057] Depending on the space charge distribution and thickness of the transition region, the thickness of an abrupt junction is only a few lattice constants, while the thickness of a gradually changing junction can reach several carrier diffusion lengths.

[0058] The breakdown voltage (BV) of a junction field-effect transistor (JFET) is determined by the degree to which the drain bias lowers the barrier in the channel region. For a gradually changing junction, the low-doped gate region near the channel is affected by the drain bias, making it easy to lower the barrier. Therefore, narrow channels require high shielding voltage.

[0059] For abrupt junctions, a wider channel can block high voltages, and a narrow gate region with low doping concentration can increase current density without reducing breakdown voltage.

[0060] The following describes the operating modes of a common-source, common-gate semiconductor device integrating a high-voltage depletion-mode silicon carbide junction field-effect transistor and a low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0061] The operating modes of the semiconductor device may include a first forward blocking mode, a second forward blocking mode, and a first forward conduction mode.

[0062] In some embodiments, in the first forward blocking mode of the semiconductor device, the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, and the high-voltage depletion-mode silicon carbide junction field effect transistor is turned on. The drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0063] In this embodiment, the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, and the high-voltage depletion-mode silicon carbide junction field effect transistor is turned on. The voltage Vds (i.e., the drain-source voltage) between the drain and source of the semiconductor device satisfies 0 < Vds < -VTH_JFET, and the voltage Vgs between the gate and source of the semiconductor device is 0.

[0064] Where, VTH_JFET is the threshold voltage of the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0065] The low-voltage enhancement-mode gallium nitride high electron mobility transistor as a switch is in the off state, the driving voltage Vgs corresponds to 0, and there is no current in the low-voltage enhancement-mode gallium nitride high electron mobility transistor as a switch. Therefore, the current Id of the semiconductor device is 0.

[0066] The high-voltage depletion-mode silicon carbide junction field effect transistor is in the on state, -Vgs_JFET = -Vds_GaN < Vds < -VTH_GaN.

[0067] Where, Vgs_JFET is the voltage between the first gate and the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor, Vds_GaN is the voltage between the second drain and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and VTH_GaN is the threshold voltage of the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0068] The drain-source voltage Vds borne by the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor in the switching transistor, that is, Vds_GaN is equal to Vds.

[0069] In some embodiments, in the second forward blocking mode of the semiconductor device, both the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are turned off. The drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0070] In this embodiment, both the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are turned off, and the voltage Vds between the drain and source of the semiconductor device satisfies -VTH_JFET < Vds, and the voltage Vgs between the gate and source of the semiconductor device is 0.

[0071] Among them, VTH_JFET is the turn-on voltage threshold of the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0072] The voltage Vds between the drain and source of the semiconductor device continues to rise, maintaining -VTH_JFET < Vds, and the high-voltage depletion-mode silicon carbide junction field effect transistor is in the off state, and its drive voltage is lower than the threshold voltage.

[0073] The voltage Vds between the drain and source that the semiconductor device withstands is jointly borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0074] In some embodiments, in the first forward conduction mode of the semiconductor device, both the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are turned on.

[0075] In this embodiment, the drive voltage of the semiconductor device, that is, the voltage Vgs between the gate and source of the semiconductor device, is higher than the turn-on voltage threshold VTH_GaN of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and both the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor can be turned on.

[0076] In some embodiments, the semiconductor device may further include a first metal connection structure and a second metal connection structure.

[0077] Among them, the first gate and the second source are connected through the first metal connection structure, and the first source and the second drain are connected through the second metal connection structure.

[0078] In this embodiment, when connecting the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, the connection is made by setting the first metal connection structure.

[0079] When connecting the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, the connection is made by setting the second metal connection structure.

[0080] In practice, a first metal connection structure and a second metal connection structure can be deposited at corresponding positions between a high-voltage depletion-type silicon carbide junction field-effect transistor and a low-voltage enhancement-type gallium nitride high electron mobility transistor through metal deposition.

[0081] It should be noted that metal should not be deposited between the first gate and the first source of a high-voltage depletion-type silicon carbide junction field-effect transistor to avoid short circuits.

[0082] Understandably, in the structural design of semiconductor devices, design parameters such as the length, width, height, and doping concentration can be controlled to improve the performance of semiconductor devices.

[0083] This invention also provides a method for fabricating a semiconductor device, which can be used to fabricate the semiconductor device described above.

[0084] like Figure 7 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes:

[0085] Step 710: Grow a GaN layer, an AlGaN layer, and a P-GaN layer sequentially in the first region of the SiC substrate.

[0086] like Figure 2 As shown, GaN, AlGaN, and P-GaN layers are grown sequentially from the SiC substrate upwards. The AlGaN layer serves as a barrier layer, and the GaN layer serves as a buffer layer. There is a certain lattice mismatch between the GaN and AlGaN layers. The magnitude of the lattice mismatch is related to the Al composition. The device reliability can be improved by adjusting the Al composition to reduce the stress in the barrier layer.

[0087] In this step, GaN, AlGaN and P-GaN layers are grown in a first region of the SiC substrate for subsequent etching to obtain a low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0088] Step 720: Form a p-type junction extension region, a p-type gate contact region, an n-type drift region, and an n-type source contact region in the second region of the SiC substrate by photolithography and ion implantation.

[0089] The second region is the area on the SiC substrate where no GaN, AlGaN, or P-GaN layers have been grown.

[0090] In this embodiment, the p-type junction extension region, p-type gate contact region, n-type drift region, and n-type source contact region are formed by photolithography and ion implantation.

[0091] like Figure 3As shown, the p-type junction extension region corresponds to the region of P-SiC, the p-type gate contact region corresponds to the region of P+SiC, the n-type drift region corresponds to the region of N-SiC, and the n-type source contact region corresponds to the region of N+SiC.

[0092] The p-type gate contact region and the n-type source contact region are used to form the first gate and the first source of the high-voltage depletion-type silicon carbide junction field-effect transistor.

[0093] Step 730: Etching is performed in the first region and the second region to form a low-voltage enhancement-mode gallium nitride high electron mobility transistor and a high-voltage depletion-mode silicon carbide junction field-effect transistor, respectively.

[0094] Etching is performed in the first and second regions to form trench structures through dry etching. Low-voltage enhancement-mode gallium nitride high electron mobility transistors are etched in the first region, and high-voltage depletion-mode silicon carbide junction field-effect transistors are etched in the second region.

[0095] In actual implementation, such as Figure 4 As shown, during etching in the first and second regions, the connection regions of the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field-effect transistor are etched to facilitate subsequent connection.

[0096] The SiO2 between the p-type gate contact region (the region corresponding to P+SiC) and the n-type source contact region (the region corresponding to N+SiC) is a masking film.

[0097] Step 740: Connect the first gate of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second source of the low-voltage enhancement-type gallium nitride high electron mobility transistor, and connect the first source of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second drain of the low-voltage enhancement-type gallium nitride high electron mobility transistor to obtain a semiconductor device.

[0098] In the second region, a first source is formed in the region of N+SiC that is close to the first region (i.e., the n-type source contact region), a first gate is formed in the region of P+SiC that is close to the first region (i.e., the p-type gate contact region), and a first drain is formed in the region of N+SiC that is far from the first region in the second region.

[0099] In this embodiment, a low-voltage enhancement-mode gallium nitride high electron mobility transistor, including a second gate, a second drain, and a second source, is obtained by etching a portion of the first region.

[0100] like Figure 5 As shown, the first gate G JFET Second source pole S GaN Connection, first source S JFET Second drain DGaN Connection, the source of a semiconductor device (corresponding to) Figure 5 The S shown is the second source S. GaN The gate of a semiconductor device (corresponding to) Figure 5 The G shown is the second gate G. GaN The drain of a semiconductor device (corresponding to) Figure 5 D) shown is the first drain electrode D JFET This forms a semiconductor device with a common source and common gate structure (i.e., Cascode type).

[0101] According to the semiconductor device fabrication method provided in the embodiments of the present invention, a high-voltage depletion-mode silicon carbide junction field-effect transistor and a low-voltage enhancement-mode gallium nitride high electron mobility transistor are integrated into one device through structural design to obtain a common-source, common-gate semiconductor device. This semiconductor device combines the advantages of fast switching speed of GaN and high breakdown voltage of SiC, which can effectively improve the working efficiency and reliability of the semiconductor device.

[0102] In some embodiments, a first abrupt junction is provided between the p-type gate contact region and the n-type source contact region.

[0103] The high-voltage depletion-type silicon carbide junction field-effect transistor includes a first gate region and a first source region, with the first gate connected to the first gate region and the first source connected to the first source region.

[0104] The first gate region is the P-type doped silicon carbide region in a high-voltage depletion-type silicon carbide junction field-effect transistor, i.e., the p-type gate contact region.

[0105] The first source region is the N-type doped silicon carbide region in a high-voltage depletion-mode silicon carbide junction field-effect transistor, i.e., the n-type source contact region.

[0106] In this embodiment, a first abrupt junction is formed in the p-type gate contact region and the n-type source contact region, and the concentration of acceptor impurities in the p-type gate contact region abruptly changes to the concentration of donor impurities in the n-type source contact region. The high-voltage depletion-mode silicon carbide junction field-effect transistor becomes a junction field-effect transistor with an abrupt junction between the gate and the channel, which can increase the drain current density and reduce the on-resistance.

[0107] In some embodiments, step 740, connecting the first gate of the high-voltage depletion-mode silicon carbide junction field-effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion-mode silicon carbide junction field-effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, may include:

[0108] A first metal connection structure and a second metal connection structure are formed by metal deposition. The first gate and the second source are connected through the first metal connection structure, and the first source and the second drain are connected through the second metal connection structure.

[0109] In this embodiment, a first metal interconnect structure is deposited between the first gate of a high-voltage depletion-type silicon carbide junction field-effect transistor and the second source of a low-voltage enhancement-type gallium nitride high electron mobility transistor, connecting the first gate and the second source.

[0110] A second metal interconnect structure is deposited between the first source of a high-voltage depletion-type silicon carbide junction field-effect transistor and the second drain of a low-voltage enhancement-type gallium nitride high electron mobility transistor, connecting the first source and the second drain.

[0111] It should be noted that metal should not be deposited between the first gate and the first source of a high-voltage depletion-type silicon carbide junction field-effect transistor to avoid short circuits.

[0112] This invention also provides an electronic device, including the semiconductor device described above.

[0113] The semiconductor devices in electronic equipment are common-source, common-gate devices that combine the advantages of GaN's fast switching speed and SiC's high breakdown voltage, effectively improving the operating efficiency and reliability of semiconductor devices.

[0114] The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments of the present invention do not make specific limitations.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized by, Comprise: a SiC substrate; a high-voltage depletion-mode SiC JFET formed in a second region of the SiC substrate, the high-voltage depletion-mode SiC JFET comprising a first gate, a first drain and a first source; a low-voltage enhancement-mode GaN HEMT formed in a first region of the SiC substrate, the low-voltage enhancement-mode GaN HEMT comprising a second gate, a second drain and a second source; wherein the first gate and the second source are connected, the first source and the second drain are connected, the source of the semiconductor device is the second source, the gate of the semiconductor device is the second gate, and the drain of the semiconductor device is the first drain; the high-voltage depletion-mode SiC JFET comprises a first gate region and a first source region, the first gate is connected to the first gate region, and the first source is connected to the first source region, and a first abrupt junction is provided between the first gate region and the first source region; the first gate and the second source are connected through a first metal connection structure, and the first source and the second drain are connected through a second metal connection structure; the working mode of the semiconductor device comprises a first forward blocking mode, in which the low-voltage enhancement-mode GaN HEMT is turned off, the high-voltage depletion-mode SiC JFET is turned on, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode GaN HEMT.

2. The semiconductor device according to claim 1, wherein The working mode of the semiconductor device comprises a second forward blocking mode, in which the low-voltage enhancement-mode GaN HEMT and the high-voltage depletion-mode SiC JFET are both turned off, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode GaN HEMT and the high-voltage depletion-mode SiC JFET.

3. The semiconductor device of claim 1, wherein The working mode of the semiconductor device comprises a first forward conduction mode, in which the low-voltage enhancement-mode GaN HEMT and the high-voltage depletion-mode SiC JFET are both turned on.

4. A method of producing a semiconductor device as claimed in any one of claims 1 to 3, characterized in that Comprise: sequentially growing a GaN layer, an AlGaN layer and a P-GaN layer in a first region of a SiC substrate; forming a p-type junction termination extension region, a p-type gate contact region, an n-type drift region and an n-type source contact region in a second region of the SiC substrate through photolithography and ion implantation; etching in the first region and the second region to form a low-voltage enhancement-mode GaN HEMT and a high-voltage depletion-mode SiC JFET, respectively; The first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor is connected with the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor is connected with the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, to obtain a semiconductor device; a first abrupt junction is arranged between the p-type gate contact region and the n-type source contact region; the first gate and the second source are connected through a first metal connection structure, and the first source and the second drain are connected through a second metal connection structure.

5. An electronic device, comprising: The semiconductor device as claimed in any one of claims 1-3.

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