Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. By adding a negative capacitance structure to the device, a manufacturing method for fabricating a logic device and a flash memory structure on the same process platform is achieved, which has the advantages of simple design and process and low manufacturing cost. The present invention controls the thicknesses of the gate oxide layer and the negative capacitance dielectric layer of the corresponding device, and controls the range of the equivalent negative capacitance values of the embedded flash memory, the logic core device, and the input / output device, so that the embedded flash memory can be controlled to operate in the bistable region, thereby realizing a stable flash storage function, and the logic core device and the input / output device are controlled to operate in the non-hysteresis region, thereby realizing the functions of the logic device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Flash Memory is a non-volatile storage integrated circuit, and its main characteristics are fast working speed, small cell area, high integration degree, good reliability, capable of being repeatedly erased and written more than 100,000 times, and data can be reliably retained for more than 10 years. Flash Memory has gradually become the main carrier of data and programs in embedded systems. According to the type of carriers generating current, the basic FLASH unit can be divided into N-channel flash memory (nFLASH) and P-channel flash memory (pFLASH).

[0003] In an embedded system, the flash memory needs to be integrated with a logic circuit to achieve storage and read / write functions. However, since there are significant differences in the operating voltage and operating mode between the flash memory and the logic circuit, the existing process for embedded memory is complex, and the matching degree between the memory and the logic process is relatively low, resulting in greater difficulty in the integrated process design of the flash memory and the logic circuit and higher manufacturing costs.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art merely because these solutions are described in the background art part of the present application. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to solve the problem of the relatively large difficulty in the integrated process design of the flash memory and the logic circuit in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for manufacturing a semiconductor device, the manufacturing method comprising: 1) providing a substrate, on which a first gate groove corresponding to an embedded flash memory, a second gate groove corresponding to a logic core device, and a third gate groove corresponding to an input / output device are formed, the bottoms of the first gate groove, the second gate groove, and the third gate groove respectively having a first gate oxide layer, a second gate oxide layer, and a third gate oxide layer, and the thickness of the second gate oxide layer being less than the thicknesses of the first gate oxide layer and the third gate oxide layer; 2) forming a positive capacitance dielectric layer on the bottoms and sidewalls of the first gate groove, the second gate groove, and the third groove; 3) forming a negative capacitance dielectric layer on the surface of the positive capacitance dielectric layer, the thicknesses of the first negative capacitance dielectric layer and the second negative capacitance dielectric layer located in the first gate groove and the second gate groove being less than the thickness of the third negative capacitance dielectric layer located in the third gate groove; 4) forming metal gate electrodes in the first gate groove, the second gate groove, and the third gate groove.

[0007] Optionally, the material of the positive capacitance dielectric layer includes one or a combination of two or more of silicon oxide, silicon nitride, zirconium oxide, and hafnium-based high-k dielectric layers.

[0008] Optionally, the material of the negative capacitance dielectric layer includes a ferroelectric material, and the ferroelectric material includes one or a combination of two or more of Pb(Zr 0.5 Ti 0.5 )O3, HfZrO x , SrBi2Ta2O9, BaTiO3, and SrTiO3.

[0009] Optionally, in step 1), the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are deposited to control their respective thicknesses, and the thicknesses of the first gate oxide layer and the third gate oxide layer are the same and both greater than the thickness of the second gate oxide layer; or / and in step 2), the positive capacitance dielectric layer formed on the bottoms and sidewalls of the first gate groove, the second gate groove, and the third groove is formed simultaneously and has the same thickness; or / and in step 3), the first negative capacitance dielectric layer, the second negative capacitance dielectric layer, and the third negative capacitance dielectric layer are deposited to control their respective thicknesses, and the thicknesses of the first negative capacitance dielectric layer and the second negative capacitance dielectric layer are the same and both less than the thickness of the third negative capacitance dielectric layer located in the third gate groove.

[0010] Optionally, the positive capacitance dielectric layer and the negative capacitance dielectric layer are formed by an atomic layer deposition process.

[0011] Optionally, by controlling the thicknesses of the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer, and the thicknesses of the first negative capacitance dielectric layer, the second negative capacitance dielectric layer, and the third negative capacitance dielectric layer, the range of the equivalent negative capacitance values of the embedded flash memory, the logic core device, and the input / output device is controlled, where the range of the equivalent negative capacitance values of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer.

[0012] Optionally, the embedded flash memory operates in a bistable region, and the logic core device and the input / output device operate in a non-hysteretic region.

[0013] The present invention also provides a semiconductor device, which includes: a substrate, on which a first gate groove corresponding to the embedded flash memory, a second gate groove corresponding to the logic core device, and a third gate groove corresponding to the input / output device are formed. The bottoms of the first gate groove, the second gate groove, and the third gate groove respectively have a first gate oxide layer, a second gate oxide layer, and a third gate oxide layer, and the thickness of the second gate oxide layer is less than the thicknesses of the first gate oxide layer and the third gate oxide layer; a positive capacitance dielectric layer formed on the bottoms and sidewalls of the first gate groove, the second gate groove, and the third groove; a negative capacitance dielectric layer, where the thicknesses of the first negative capacitance dielectric layer in the first gate groove and the second negative capacitance dielectric layer in the second gate groove are less than the thickness of the third negative capacitance dielectric layer in the third gate groove; and a metal gate formed in the first gate groove, the second gate groove, and the third gate groove.

[0014] Optionally, the material of the positive capacitance dielectric layer includes one or a combination of two or more of silicon oxide, silicon nitride, zirconium oxide, and hafnium-based high-k dielectric layers.

[0015] Optionally, the material of the negative capacitance dielectric layer includes a ferroelectric material, and the ferroelectric material includes Pb(Zr 0.5 Ti 0.5 )O3, HfZrO x , SrBi2Ta2O9, BaTiO3, and SrTiO3, or a combination of two or more of them.

[0016] Optionally, by controlling the thicknesses of the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer, and the thicknesses of the first negative capacitance dielectric layer, the second negative capacitance dielectric layer, and the third negative capacitance dielectric layer, the range of the equivalent negative capacitance values of the embedded flash memory, the logic core device, and the input / output device is controlled, where the range of the equivalent negative capacitance values of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer.

[0017] Optionally, the embedded flash memory operates in the bistable region, and the logic core device and the input / output device operate in the non-hysteresis region.

[0018] As described above, the semiconductor device and its manufacturing method according to the present invention have the following beneficial effects:

[0019] The present invention adds a negative capacitance structure to the device, realizing a manufacturing method for fabricating a logic device and a flash memory structure on the same process platform, which has the advantages of simple design and process and low manufacturing cost.

[0020] The present invention controls the range of the equivalent negative capacitance values of the embedded flash memory, the logic core device, and the input / output device by controlling the thicknesses of the corresponding device gate oxide layer and the negative capacitance dielectric layer, where the range of the equivalent negative capacitance values of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer, which can enable the embedded flash memory to be controlled to operate in the bistable region, thereby realizing a stable flash storage function, and the logic core device and the input / output device are controlled to operate in the non-hysteresis region, thereby realizing the logic device function. Description of the Drawings

[0021] The accompanying drawings included are used to provide a further understanding of the embodiments of the present application, which form a part of the specification, are used to illustrate the implementation manners of the present application, and are used to explain the principles of the present application together with the text description. Obviously, the accompanying drawings in the following description are only some embodiments of the present application.

[0022] Figures 1 to 4 Show the structural schematic diagrams presented by the steps of the manufacturing method of the semiconductor device according to the embodiments of the present invention.

[0023] Figure 5 Show the schematic diagram of the capacitance-voltage relationship curve of the ferroelectric material according to the embodiments of the present invention.

[0024] Figure 6 and Figure 7 Show the schematic diagram of the capacitance (DE+FE)-voltage curve of the superposition of the negative capacitance (FE) and the positive capacitance (DE) according to the embodiments of the present invention.

[0025] Figure 8 Show the schematic diagram of the principle of the positive and negative equivalent capacitance circuits according to the embodiments of the present invention.

[0026] Figure 9 Show the subthreshold swing Vg-logI of the semiconductor device according to the embodiments of the present invention D relationship curve schematic diagram.

[0027] Element number description

[0028] 101 Substrate

[0029] 102 First gate groove

[0030] 103 Second gate groove

[0031] 104 Third gate groove

[0032] 105 First gate oxide layer

[0033] 106 Second gate oxide layer

[0034] 107 Third gate oxide layer

[0035] 108 Sidewall structure

[0036] 109 Positive capacitance dielectric layer

[0037] 110 First negative capacitance dielectric layer

[0038] 111 Second negative capacitance dielectric layer

[0039] 112 Third negative capacitance dielectric layer

[0040] 113 Metal barrier layer

[0041] 114 Metal conductive layer Detailed implementation manners

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, whole units, steps or components, but does not exclude the presence or addition of one or more other features, whole units, steps or components.

[0044] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or replace features in other embodiments.

[0045] When detailing the embodiments of the present invention, for ease of illustration, the cross-sectional views showing the device structure are enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0046] For convenience of description, spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0047] In the context of the present application, the structure in which the first feature is "above" the second feature described may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] As Figures 1 to 4 shown, this embodiment provides a method for preparing a semiconductor device, and the preparation method includes the following steps:

[0050] As shown Figure 1 in FIG. 1, first, perform step 1), provide a substrate 101, on which a first gate groove 102 corresponding to an embedded flash memory, a second gate groove 103 corresponding to a logic core device, and a third gate groove 104 corresponding to an input / output device are formed. The bottoms of the first gate groove 102, the second gate groove 103, and the third gate groove 104 respectively have a first gate oxide layer 105, a second gate oxide layer 106, and a third gate oxide layer 107, and the thickness of the second gate oxide layer 106 is less than the thicknesses of the first gate oxide layer 105 and the third gate oxide layer 107.

[0051] As shown Figure 1 in FIG. 2, the substrate 101 may be, for example, a silicon substrate. The substrate 101 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 101 may include compound semiconductors and / or alloy semiconductors, such as gallium nitride, gallium arsenide, etc. In addition, the substrate 101 may include an epitaxial layer (epitaxial layer), may be strained to improve performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement components. The substrate 101 may also include various layers, including conductive or insulating layers formed on a semiconductor substrate. Additionally, depending on design requirements, the substrate 101 may include various doping configurations, such as the body region, source region, drain region, etc. of a MOS transistor. Additionally, in some embodiments, isolation components may also be formed within the substrate 101 to define and isolate various device elements formed in and / or on the substrate 101. The isolation components may be, for example, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure, etc.

[0052] As shown Figure 1 in FIG. 3, in one embodiment, on the substrate 101, a first gate groove 102 corresponding to an embedded flash memory, a second gate groove 103 corresponding to a logic core device, and a third gate groove 104 corresponding to an input / output device are formed. The sidewalls of the first gate groove 102, the second gate groove 103, and the third gate groove 104 may be surrounded by a sidewall structure 108, and the material of the sidewall structure 108 may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, or a stacked structure of the above materials, etc. The first gate groove 102, the second gate groove 103, and the third gate groove 104 may originally be filled with materials such as polysilicon, and by selectively removing the polysilicon in the first gate groove 102, the second gate groove 103, and the third gate groove 104, the first gate groove 102, the second gate groove 103, and the third gate groove 104 having cavities are formed.

[0053] As shown Figure 1As shown, in one embodiment, the bottoms of the first gate groove 102, the second gate groove 103, and the third gate groove 104 respectively have a first gate oxide layer 105, a second gate oxide layer 106, and a third gate oxide layer 107. The first gate groove 102, the second gate groove 103, and the third gate groove 104 can be formed on the surface of the substrate 101 in the previous process, such as forming the first gate groove 102, the second gate groove 103, and the third gate groove 104 respectively through a chemical vapor deposition process, etc. The thickness of the second gate oxide layer 106 is less than the thicknesses of the first gate oxide layer 105 and the third gate oxide layer 107. The thinning process can be, for example, a photolithography process and an etching process, or a wet etching process, etc., and the thickness of the second gate oxide layer 106 can also be controlled by other means.

[0054] In one embodiment, the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are deposited to control their respective thicknesses. The thicknesses of the first gate oxide layer 105 and the third gate oxide layer 107 are the same and both are greater than the thickness of the second gate oxide layer 106 to further simplify the process. Of course, in other embodiments, the thicknesses of the first gate oxide layer 105 and the third gate oxide layer 107 can also be further adjusted to meet the performance requirements of different devices.

[0055] As Figure 2 shown, then step 2) is performed to form a positive capacitance dielectric layer 109 on the bottoms and sidewalls of the first gate groove 102, the second gate groove 103, and the third groove.

[0056] In one embodiment, the material of the positive capacitance dielectric layer 109 includes one or a combination of two or more of silicon oxide, silicon nitride, zirconium oxide, and hafnium-based high-k dielectric layers (such as HfO2, etc.).

[0057] In one embodiment, the positive capacitance dielectric layer 109 is formed by an atomic layer deposition process to precisely control the thickness of the positive capacitance dielectric layer 109.

[0058] In one embodiment, the positive capacitance dielectric layer 109 formed on the bottoms and sidewalls of the first gate groove 102, the second gate groove 103, and the third groove is formed simultaneously and has the same thickness.

[0059] As Figures 3 to 4As shown, then step 3) is carried out to form a negative capacitance dielectric layer on the surface of the positive capacitance dielectric layer 109. The thicknesses of the first negative capacitance dielectric layer 110 and the second negative capacitance dielectric layer 111 located in the first gate groove 102 and the second gate groove 103 are less than the thickness of the third negative capacitance dielectric layer 112 located in the third gate groove 104; and step 4) is carried out to form a metal gate in the first gate groove 102, the second gate groove 103 and the third gate groove 104. The metal gate may include, for example, a metal barrier layer 113 and a metal conductive layer 114.

[0060] In one embodiment, the material of the negative capacitance dielectric layer includes a ferroelectric material. Under the action of an electric field, the ferroelectric material requires a relatively large electric field for polarization reversal and has a relatively large hysteresis during the reversal process, as Figure 5 shown. According to the capacitance formula:

[0061]

[0062] the capacitance-voltage relationship curve of the ferroelectric material is obtained as Figure 5 shown, where there is a region with C FE < 0 in the curve, and the capacitance in this region exhibits negative capacitance properties.

[0063] In one embodiment, the ferroelectric material includes one or a combination of two or more of Pb(Zr 0.5 Ti 0.5 )O3, HfZrO x , SrBi2Ta2O9, BaTiO3 and SrTiO3.

[0064] In one embodiment, the first negative capacitance dielectric layer 110, the second negative capacitance dielectric layer 111 and the third negative capacitance dielectric layer 112 are deposited to control their respective thicknesses. The thicknesses of the first negative capacitance dielectric layer 110 and the second negative capacitance dielectric layer 111 are the same and are both less than the thickness of the third negative capacitance dielectric layer 112 located in the third gate groove 104.

[0065] In one embodiment, the negative capacitance dielectric layer is formed by an atomic layer deposition process to further control the thickness of the negative capacitance dielectric layer. In a specific embodiment, the thickness of the negative capacitance dielectric layer may be 20 nm to 200 nm.

[0066] In one embodiment, by controlling the thicknesses of the first gate oxide layer 105, the second gate oxide layer 106, and the third gate oxide layer 107, and the thicknesses of the first negative capacitance dielectric layer 110, the second negative capacitance dielectric layer 111, and the third negative capacitance dielectric layer 112, the range of the equivalent negative capacitance values of the embedded flash memory, the logic core device, and the input / output device is controlled, wherein the range of the equivalent negative capacitance values of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer 109.

[0067] In one embodiment, by controlling the range of the equivalent negative capacitance value of the logic core device and the input / output device to be -2C MOS <C FE <0, the capacitance (DE + FE)-voltage curve of the final negative capacitance (FE) superimposed on the positive capacitance (DE) is as Figure 6 shown, and this capacitance (DE + FE) setting can make the logic core device and the input / output device operate in the hysteresis-free state region. By controlling the range of the equivalent negative capacitance value of the embedded flash memory to be C FE <-2C MOS , the capacitance (DE + FE)-voltage curve of the final negative capacitance (FE) superimposed on the positive capacitance (DE) is as Figure 7 shown, and this capacitance (DE + FE) setting can make the embedded flash memory operate in the bistable region.

[0068] The circuit principle of the positive and negative equivalent capacitances of the present invention (the positive and negative equivalent capacitances can be composed of a substrate, a metal gate, and the gate oxide layer, the positive capacitance dielectric layer, and the negative capacitance dielectric layer therebetween) is as Figure 8 shown,

[0069] It can be seen that, compared with the traditional positive capacitance device, the positive and negative equivalent capacitances of the present application can achieve a certain voltage increase, thereby effectively reducing the supply voltage required by the system. At the same time, Figure 9 is shown as the subthreshold swing Vg-logI of the device of the present application D relationship curve. From Figure 9 it can be known that, compared with the traditional positive capacitance device, the positive and negative equivalent capacitances of the present application can effectively improve the subthreshold swing of the device.

[0070] As Figure 4As shown, this embodiment further provides a semiconductor device, which includes: a substrate 101, on which a first gate groove 102 corresponding to an embedded flash memory, a second gate groove 103 corresponding to a logic core device, and a third gate groove 104 corresponding to an input / output device are formed. The bottoms of the first gate groove 102, the second gate groove 103, and the third gate groove 104 respectively have a first gate oxide layer 105, a second gate oxide layer 106, and a third gate oxide layer 107, and the thickness of the second gate oxide layer 106 is less than the thicknesses of the first gate oxide layer 105 and the third gate oxide layer 107; a positive capacitance dielectric layer 109 is formed on the bottoms and sidewalls of the first gate groove 102, the second gate groove 103, and the third groove; the thicknesses of the first negative capacitance dielectric layer 110 in the first gate groove 102 and the second negative capacitance dielectric layer 111 in the second gate groove 103 are less than the thickness of the third negative capacitance dielectric layer 112 in the third gate groove 104; a metal gate is formed in the first gate groove 102, the second gate groove 103, and the third gate groove 104.

[0071] In one embodiment, the material of the positive capacitance dielectric layer 109 includes one or a combination of two or more of silicon oxide, silicon nitride, zirconium oxide, and a hafnium-based high-k dielectric layer.

[0072] In one embodiment, the material of the negative capacitance dielectric layer includes a ferroelectric material, and the ferroelectric material includes Pb(Zr 0.5 Ti 0.5 )O3, HfZrO x , SrBi2Ta2O9, BaTiO3, and SrTiO3 or a combination of two or more of them.

[0073] In one embodiment, the thicknesses of the first gate oxide layer 105 and the third gate oxide layer 107 are the same; and / or the positive capacitance dielectric layer 109 formed on the bottoms and sidewalls of the first gate groove 102, the second gate groove 103, and the third groove has the same thickness; and / or the thicknesses of the first negative capacitance dielectric layer 110 and the second negative capacitance dielectric layer 111 are the same.

[0074] In one embodiment, by controlling the thicknesses of the first gate oxide layer 105, the second gate oxide layer 106, and the third gate oxide layer 107, and the thicknesses of the first negative capacitance dielectric layer 110, the second negative capacitance dielectric layer 111, and the third negative capacitance dielectric layer 112, the range of the equivalent negative capacitance values of the embedded flash memory, the logic core device, and the input / output device is controlled. Among them, the range of the equivalent negative capacitance values of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is CFE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer 109.

[0075] In one embodiment, the embedded flash memory operates in the bistable region, and the logic core device and the input / output device operate in the hysteresis-free region.

[0076] As described above, the semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0077] The present invention adds a negative capacitance structure to the device, realizing a manufacturing method for fabricating a logic device and a flash memory structure on the same process platform, which has the advantages of simple design and process and low manufacturing cost.

[0078] The present invention controls the thicknesses of the gate oxide layer and the negative capacitance dielectric layer of the corresponding device to control the range of the equivalent negative capacitance value of the embedded flash memory, the logic core device, and the input / output device. Among them, the range of the equivalent negative capacitance value of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer 109, which can control the embedded flash memory to operate in the bistable region, thereby realizing a stable flash storage function, and the logic core device and the input / output device are controlled to operate in the hysteresis-free region, thereby realizing the logic device function.

[0079] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0080] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The preparation method includes: 1) Providing a substrate, on which a first gate groove corresponding to an embedded flash memory, a second gate groove corresponding to a logic core device, and a third gate groove corresponding to an input / output device are formed. The bottoms of the first gate groove, the second gate groove, and the third gate groove respectively have a first gate oxide layer, a second gate oxide layer, and a third gate oxide layer, and the thickness of the second gate oxide layer is less than the thicknesses of the first gate oxide layer and the third gate oxide layer; 2) Forming a positive capacitance dielectric layer on the bottoms and sidewalls of the first gate groove, the second gate groove, and the third groove; 3) Forming a negative capacitance dielectric layer on the surface of the positive capacitance dielectric layer. The thicknesses of the first negative capacitance dielectric layer and the second negative capacitance dielectric layer located in the first gate groove and the second gate groove are less than the thickness of the third negative capacitance dielectric layer located in the third gate groove; 4) Forming metal gates in the first gate groove, the second gate groove, and the third gate groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the positive capacitance dielectric layer includes one or a combination of two or more of silicon oxide, silicon nitride, zirconium oxide, and hafnium-based high-k dielectric layers.

3. The manufacturing method of the semiconductor device according to claim 1, characterized in that: The material of the negative capacitance dielectric layer includes a ferroelectric material, and the ferroelectric material includes Pb(Zr 0.5 Ti 0.5 )O3, HfZrO x , SrBi2Ta2O9, BaTiO3, and SrTiO3, or a combination of two or more thereof.

4. The manufacturing method of the semiconductor device according to claim 1, wherein: In step 1), the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are deposited to control their respective thicknesses, and the thicknesses of the first gate oxide layer and the third gate oxide layer are the same and both greater than the thickness of the second gate oxide layer; or / and in step 2), the positive capacitance dielectric layer formed on the bottoms and sidewalls of the first gate groove, the second gate groove, and the third groove is formed simultaneously and has the same thickness; or / and in step 3), the first negative capacitance dielectric layer, the second negative capacitance dielectric layer, and the third negative capacitance dielectric layer are deposited to control their respective thicknesses, and the thicknesses of the first negative capacitance dielectric layer and the second negative capacitance dielectric layer are the same and both less than the thickness of the third negative capacitance dielectric layer located in the third gate groove.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: By controlling the thicknesses of the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer, and the thicknesses of the first negative capacitance dielectric layer, the second negative capacitance dielectric layer, and the third negative capacitance dielectric layer, the range of the equivalent negative capacitance value of the embedded flash memory, the logic core device, and the input / output device is controlled, wherein the range of the equivalent negative capacitance value of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer.

6. The method for preparing a semiconductor device according to claim 5, wherein: The embedded flash memory operates in a bistable region, and the logic core device and the input / output device operate in a non-hysteretic region.

7. A semiconductor device, characterized in that, It includes: A substrate, on which a first gate groove corresponding to an embedded flash memory, a second gate groove corresponding to a logic core device, and a third gate groove corresponding to an input / output device are formed. The bottoms of the first gate groove, the second gate groove, and the third gate groove respectively have a first gate oxide layer, a second gate oxide layer, and a third gate oxide layer, and the thickness of the second gate oxide layer is less than the thicknesses of the first gate oxide layer and the third gate oxide layer; A positive capacitance dielectric layer, formed on the bottoms and sidewalls of the first gate groove, the second gate groove, and the third groove; A negative capacitance dielectric layer, the thicknesses of the first negative capacitance dielectric layer located in the first gate groove and the second negative capacitance dielectric layer located in the second gate groove are less than the thickness of the third negative capacitance dielectric layer located in the third gate groove; Metal gates, formed in the first gate groove, the second gate groove, and the third gate groove.

8. The semiconductor device according to claim 7, wherein: The material of the positive capacitance dielectric layer includes one or a combination of two or more of silicon oxide, silicon nitride, zirconium oxide, and hafnium-based high-k dielectric layers.

9. The semiconductor device according to claim 8, wherein: The material of the negative capacitance dielectric layer includes a ferroelectric material, and the ferroelectric material includes Pb(Zr 0.5 Ti 0.5 )O3, HfZrO x , one or a combination of two or more of SrBi2Ta2O9, BaTiO3, and SrTiO3.

10. The semiconductor device according to any one of claims 7 to 9, characterized in that: By controlling the thicknesses of the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer, as well as the thicknesses of the first negative capacitance dielectric layer, the second negative capacitance dielectric layer, and the third negative capacitance dielectric layer, the range of the equivalent negative capacitance value of the embedded flash memory, the logic core device, and the input / output device is controlled, where the range of the equivalent negative capacitance value of the logic core device and the input / output device is -2C MOS <C FE <0, and the range of the equivalent negative capacitance value of the embedded flash memory is C FE <-2C MOS , where C FE is the equivalent negative capacitance value of the negative capacitance dielectric layer, and C MOS is the equivalent positive capacitance value of the combination of the gate oxide layer and the positive capacitance dielectric layer.

11. The semiconductor device according to claim 10, wherein: The embedded flash memory operates in a bistable region, and the logic core device and the input / output device operate in a non-hysteretic region.

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