A clock switching method and switching circuit

Abstract

The present invention discloses a clock switching method and switching circuit, which includes: when a chip system performs mode switching, if an internal low-frequency clock is configured to be in a non-enabled state, controlling the internal low-frequency clock to enter an enabled state and selecting the internal low-frequency clock for mode switching control; the chip system includes a normal power consumption mode and a low power consumption mode; when the chip system performs mode switching, if both the internal low-frequency clock and the external low-frequency clock are configured to be in an enabled state, selecting the internal low-frequency clock or the external low-frequency clock for mode switching control according to a set selection rule; when the chip system switches from the normal power consumption mode to the low power consumption mode, after the internal low-frequency clock or the external low-frequency clock performs mode switching control, controlling the internal low-frequency clock or the external low-frequency clock to enter a non-enabled state. The technical solution provided by the present invention can avoid deadlock and abnormal phenomena during the mode switching process, thereby improving the stability of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of low power consumption of chips, and in particular to a clock switching method and a switching circuit. Background Art

[0002] With the rapid development of information technology and the increasing diversification of electronic products, the requirements for microcontroller chip performance are becoming increasingly higher, such as chip power consumption and reliability. Power consumption directly determines the service life of the chip system, while reliability determines the working performance of the chip.

[0003] Traditional clock switching between normal and low-power modes involves manually turning on the low-frequency internal clock through software before switching to low-power mode. This disadvantage increases the current consumption of the low-frequency internal clock during low-power mode. Furthermore, if the user forgets to turn on the low-frequency internal clock before entering low-power mode, the system may freeze or experience anomalies. Summary of the Invention

[0004] The embodiments of the present invention provide a clock switching method and a switching circuit to avoid locking and abnormal phenomena during mode switching and improve chip stability.

[0005] In a first aspect, an embodiment of the present invention provides a clock switching method, comprising:

[0006] When the chip system performs mode switching, if the internal low-frequency clock is configured to be in a non-enabled state, the internal low-frequency clock is controlled to enter an enabled state and the internal low-frequency clock is selected for mode switching control; the chip system includes a normal power consumption mode and a low power consumption mode;

[0007] When the chip system performs mode switching, if both the internal low-frequency clock and the external low-frequency clock are configured to be enabled, the internal low-frequency clock or the external low-frequency clock is selected according to a set selection rule to perform mode switching control;

[0008] When the chip system switches from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock performs mode switching control, the internal low frequency clock or the external low frequency clock is controlled to enter a disabled state.

[0009] In a second aspect, an embodiment of the present invention provides a clock switching circuit that can execute the clock switching method provided by any embodiment of the present invention, the clock switching circuit comprising: an internal low-frequency clock module, an external low-frequency clock module, a clock signal output module, and a mode control module;

[0010] The internal low-frequency clock module is used to output the internal low-frequency clock to the clock signal output module in an enabled state; the external low-frequency clock module is used to output the external low-frequency clock to the clock signal output module in the enabled state;

[0011] The clock signal output module is used to, when the chip system performs mode switching, if the internal low-frequency clock is configured to be in a non-enabled state, control the internal low-frequency clock to enter an enabled state and select the internal low-frequency clock to be output to the mode control module; if both the internal low-frequency clock and the external low-frequency clock are configured to be in an enabled state, select the internal low-frequency clock or the external low-frequency clock to be output to the mode control module according to a set selection rule;

[0012] When switching from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock is output to the mode control module, the internal low frequency clock module and the external low frequency clock module enter a disabled state.

[0013] In the present invention, when the chip system switches between normal power consumption mode and low power consumption mode, the mode switching can be controlled by an internal low-frequency clock or an external low-frequency clock. Specifically, when the internal low-frequency clock is in a disabled state, the internal low-frequency clock is controlled to enter an enabled state and assist in the control of the above-mentioned mode switching; and when both the internal low-frequency clock and the external low-frequency clock are in an enabled state, the internal low-frequency clock or the external low-frequency clock is selected to assist in the mode switching according to the setting rules defined by the chip system. That is, in this embodiment, during the mode switching process, the internal low-frequency clock or the external low-frequency clock always assists in the mode switching, and the chip system will not be locked or abnormal due to forgetting to turn on the internal low-frequency clock before the mode switching, thereby improving the stability of the mode switching process and the chip system. In addition, when the chip system completes the mode switching and enters the low power consumption mode, the internal low-frequency clock or the external low-frequency clock that controls the mode switching is entered into a disabled state, effectively reducing the current consumption of the low-frequency clock in the low power consumption mode and avoiding unnecessary power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic flow chart of a clock switching method provided in an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of a flow chart of another clock switching method provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of a flow chart of another clock switching method provided by an embodiment of the present invention;

[0017] Figure 4A schematic structural diagram of a clock switching circuit provided by an embodiment of the present invention;

[0018] Figure 5 A schematic structural diagram of another clock switching circuit provided by an embodiment of the present invention;

[0019] Figure 6 A timing diagram of a clock switching circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0021] The chip system has two low-frequency clocks: an internal low-frequency clock (LSI) and an external low-frequency clock (LSE). The internal low-frequency clock is generated by an internal RC oscillator, while the external low-frequency clock is generated by an external crystal oscillator. Due to the external crystal oscillator, the external low-frequency clock is less stable and may experience clock loss. During chip system operation, software can arbitrarily turn on or off the internal low-frequency clock LSI or the external low-frequency clock LSE. In low-power mode, there are long periods of time when the low-frequency clock is not required, allowing the system to enter a deep sleep state. However, during mode switching, low-frequency clocks are still required to control functions such as power on and off. Therefore, the internal low-frequency clock LSI or the external low-frequency clock LSE is required to control or assist in mode switching.

[0022] In the technology of switching between normal power consumption mode and low power consumption mode, the traditional solution is to manually turn on the internal low-frequency clock through software before switching to low power consumption mode. The disadvantage is that the current consumption of the internal low-frequency clock will increase in low power consumption mode. In addition, if the user forgets to turn on the internal low-frequency clock before entering low power consumption mode, the chip system may be locked or abnormal. To solve these problems, this embodiment adopts adaptive dynamic control of the internal low-frequency clock and the external low-frequency clock, so that when the chip system switches between normal power consumption mode and low power consumption mode clock, the LSI and LSE clocks can be automatically switched, avoiding unnecessary power consumption and increasing system stability.

[0023] Specifically, an embodiment of the present invention provides a clock switching method, such as Figure 1 As shown, Figure 1A flowchart of a clock switching method provided by an embodiment of the present invention is shown below:

[0024] Step S101 : When the chip system performs mode switching, if the internal low-frequency clock is configured to be in a disabled state, the internal low-frequency clock is controlled to enter an enabled state and the internal low-frequency clock is selected for mode switching control.

[0025] The chip system includes a normal power consumption mode and a low power consumption mode. In this embodiment, the chip system can operate in multiple modes, for example, the run mode and the low power consumption mode. In this embodiment, it is divided into two categories according to the size of its power consumption: normal power consumption mode and low power consumption mode, and the power consumption of the low power consumption mode is less than that of the normal power consumption mode. In this embodiment, optionally, the normal power consumption mode may include the run mode; the low power consumption mode may include various low power modes, for example, the sleep low power consumption mode. Of course, if the chip system can be classified into one of the normal power consumption mode and the low power consumption mode according to the size of the power consumption. Among them, the run mode is the normal working mode of the chip system, and the core clock and peripherals are running. At this time, the software can arbitrarily turn off or on the internal low-frequency clock LSI or the external low-frequency clock LSE, and the user can arbitrarily switch and select the LSI and LSE clocks. Before entering the sleep low-power mode (sleep), if the lsi and lse clocks are turned off through the configuration register, and then after executing the WFI (wait for interrupt) or WFE (wait for event) instruction, the low-power mode is entered. The software will not be able to directly turn on the lsi clock. It should be noted that at this time, this embodiment can configure the internal low-frequency clock to the enabled state by building a hardware device to complete the switch from normal power mode to low-power mode. The enabled state is the clock-on state, and clock pulses can be output for mode switching control. The disabled state is the clock-off state, and clock pulses cannot be output for mode switching control.

[0026] It should be noted that, optionally, the mode switching may include: switching from a normal power consumption mode to a low power consumption mode; and switching from a low power consumption mode to a normal power consumption mode. During the mode switching process, if it is detected that the internal low-frequency clock is configured in a disabled state, this embodiment directly controls the internal low-frequency clock to enter an enabled state and directly selects the internal low-frequency clock for mode switching control.

[0027] Optionally, if the internal low-frequency clock is configured as a non-enabled state, controlling the internal low-frequency clock to enter an enabled state and selecting the internal low-frequency clock for mode switching control may include: if the external low-frequency clock is configured as an enabled state and the internal low-frequency clock is configured as a non-enabled state, controlling the internal low-frequency clock to enter an enabled state and selecting the internal low-frequency clock for mode switching control; if the external low-frequency clock is configured as a non-enabled state and the internal low-frequency clock is configured as a non-enabled state, controlling the internal low-frequency clock to enter an enabled state and selecting the internal low-frequency clock for mode switching control. That is, regardless of whether the external low-frequency clock is configured as a non-enabled state or an enabled state, as long as the internal low-frequency clock is configured as a non-enabled state, the internal low-frequency clock will be turned on to enable the state, and the internal low-frequency clock will be directly selected for mode switching control.

[0028] Step S102 : When the chip system performs mode switching, if both the internal low-frequency clock and the external low-frequency clock are configured to be enabled, the internal low-frequency clock or the external low-frequency clock is selected according to a set selection rule to perform mode switching control.

[0029] Similarly, during a mode switch, the internal low-frequency clock may be in the enabled state. For example, if both the internal and external low-frequency clocks are enabled before the mode switch, the chip system can select one of the internal and external low-frequency clocks for mode switch control based on the selection rules set in its memory. Alternatively, if the internal low-frequency clock is enabled and the external low-frequency clock is disabled before the mode switch, the chip system can directly select the internal low-frequency clock for mode switch control. That is, when the internal low-frequency clock is disabled, the hardware automatically enables the internal low-frequency clock for use. If the internal low-frequency clock is enabled, the hardware selects the internal and external low-frequency clocks based on the selection rules (which can be factory-set or user-defined). The system ensures that a single low-frequency clock is selected to complete the mode switch, preventing the chip system from locking up and improving chip system reliability.

[0030] Step S103 : When the chip system switches from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock performs mode switching control, the internal low frequency clock or the external low frequency clock is controlled to enter a disabled state.

[0031] It should also be noted that, because a low-frequency clock is not required to operate in the low-power mode, in order to further reduce the current consumption of the low-power mode, this embodiment directly configures the low-frequency clock of the control mode switch to a non-enabled state when the chip system switches from the normal power mode to the low-power mode, thereby avoiding unnecessary power consumption.

[0032] In an embodiment of the present invention, when the chip system switches between normal power consumption mode and low power consumption mode, the mode switching can be controlled by an internal low-frequency clock or an external low-frequency clock. Specifically, when the internal low-frequency clock is in a disabled state, the internal low-frequency clock is controlled to enter an enabled state and assist in the control of the above-mentioned mode switching; and when both the internal low-frequency clock and the external low-frequency clock are in an enabled state, the internal low-frequency clock or the external low-frequency clock is selected to assist in the mode switching according to the setting rules defined by the chip system. That is, in this embodiment, during the mode switching process, the internal low-frequency clock or the external low-frequency clock always assists in the mode switching, and the chip system will not be locked or abnormal due to forgetting to turn on the internal low-frequency clock before the mode switching, thereby improving the stability of the mode switching process and the chip system. In addition, when the chip system completes the mode switching and enters the low power consumption mode, the internal low-frequency clock or the external low-frequency clock that controls the mode switching is entered into a disabled state, effectively reducing the current consumption of the low-frequency clock in the low power consumption mode and avoiding unnecessary power consumption.

[0033] The above is the core concept of the present invention. The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] Based on the above embodiment, this embodiment describes the specific process of step S102. Figure 2 As shown, Figure 2 A flowchart of another clock switching method provided by an embodiment of the present invention, wherein the specific steps are as follows:

[0035] Step S201 : When the chip system performs mode switching, if the internal low-frequency clock is configured to be in a disabled state, the internal low-frequency clock is controlled to enter an enabled state and the internal low-frequency clock is selected for mode switching control.

[0036] Step S202: When the chip system switches modes, if both the internal low-frequency clock and the external low-frequency clock are configured to be enabled, then step S203 is executed;

[0037] Step S203: Detect the low-frequency clock configured by the chip system for mode switching control.

[0038] Step S204: If the low-frequency clock configured by the chip system for mode switching control is an internal low-frequency clock, the internal low-frequency clock is selected for mode switching control.

[0039] Step S205: If the low-frequency clock configured by the chip system for mode switching control is an external low-frequency clock, a safety check operation is performed on the external low-frequency clock; if the external low-frequency clock passes the safety check operation, the external low-frequency clock is selected for mode switching control; if the external low-frequency clock fails the safety check operation, the internal low-frequency clock is selected for mode switching control.

[0040] In this embodiment, selecting an internal low-frequency clock or an external low-frequency clock for mode switching control according to a set selection rule may include the process of steps S203 to S205 described above. That is, steps S203 to S205 are the specific contents of setting the selection rule. When both the internal low-frequency clock and the external low-frequency clock are configured to be enabled, the chip system detects whether the low-frequency clock configured for mode switching control is the internal low-frequency clock. If so, the internal low-frequency clock, which is highly reliable and not easily lost, is directly selected for mode switching control. If not, the external low-frequency clock is selected for mode switching control while ensuring the reliability of the external low-frequency clock. Specifically, when the low-frequency clock configured for mode switching control in the chip system is an external low-frequency clock, it is necessary to perform a security detection operation on the external low-frequency clock. If the external low-frequency clock passes the security detection operation, the external low-frequency clock is directly selected for mode switching control. If the external low-frequency clock does not pass the security detection operation, the reliability of the external low-frequency clock cannot be guaranteed, and the internal low-frequency clock with higher safety performance is selected for mode switching control. The setting selection rules in this embodiment can effectively ensure the mode switching, avoid the chip system from being locked, and further improve the stability of the chip system.

[0041] In this embodiment, optionally, performing a safety detection operation on the external low-frequency clock may include: when the external low-frequency clock is in a safety detection enabled state, monitoring whether the external low-frequency clock generates a loss warning; if so, determining that the external low-frequency clock fails the safety detection operation; if not, determining that the external low-frequency clock passes the safety detection operation; when the external low-frequency clock is in a safety detection disabled state, determining that the external low-frequency clock fails the safety detection operation.

[0042] In this embodiment, the external low-frequency clock can be subjected to a safety check, but the chip system can set two states for the safety check: an enabled state and a disabled state. When the safety check is in the disabled state, the external low-frequency clock cannot be subjected to a safety check. When the safety check is in the enabled state, the external low-frequency clock can be subjected to a safety check. Because, if the external low-frequency clock is in the disabled state, the mode switching control is directly performed through the internal low-frequency clock, and there is no need to additionally test the reliability of the external low-frequency clock. Setting the safety check of the external low-frequency clock to the disabled state saves power consumption. If the external low-frequency clock is in the enabled state, and the low-frequency clock that the chip system has configured for mode switching control is the external low-frequency clock, it is necessary to set the safety check of the external low-frequency clock to the enabled state and perform a reliability test on the external low-frequency clock.

[0043] Specifically, the process of performing a safety check on the external low-frequency clock is a process of monitoring whether the external low-frequency clock generates a loss warning. If the external low-frequency clock is in a safety check-enabled state, the external low-frequency clock is monitored for a loss warning. If a loss warning is generated, it is determined that the external low-frequency clock has failed the safety check. If no loss warning is generated, it is determined that the external low-frequency clock has passed the safety check. If the external low-frequency clock is in a safety check-disabled state, it is directly determined that the external low-frequency clock has failed the safety check.

[0044] Step S206 : When the chip system switches from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock performs mode switching control, the internal low frequency clock or the external low frequency clock is controlled to enter a disabled state.

[0045] In this embodiment, an implementation method for setting selection rules is provided. When the low-frequency clock configured for mode switching control in the chip system is an external low-frequency clock, a safety detection operation is performed on the external low-frequency clock. If the signal of the external low-frequency clock is lost, the mode switching control can be performed through the internal low-frequency clock, further avoiding locking and abnormal phenomena during the mode switching process, thereby improving the stability of the chip.

[0046] Optionally, when entering low power mode, after controlling the internal low frequency clock or the external low frequency clock to enter the disabled state, the low power mode can also be awakened by an external wake-up source, such as Figure 3 As shown, Figure 3 A flowchart of another clock switching method provided by an embodiment of the present invention, wherein the specific steps are as follows:

[0047] Step S301 : When the chip system performs mode switching, if the internal low-frequency clock is configured to be in a disabled state, the internal low-frequency clock is controlled to enter an enabled state and the internal low-frequency clock is selected for mode switching control.

[0048] Step S302: When the chip system performs mode switching, if both the internal low-frequency clock and the external low-frequency clock are configured to be enabled, the internal low-frequency clock or the external low-frequency clock is selected according to a set selection rule to perform mode switching control.

[0049] Step S303 : When the chip system switches from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock performs mode switching control, the internal low frequency clock or the external low frequency clock is controlled to enter a disabled state.

[0050] Step S304: If the external wake-up source triggers the low power mode to be awakened, the internal low-frequency clock or the external low-frequency clock is controlled to enter the enabled state and the low power mode wake-up control is performed; after the internal low-frequency clock or the external low-frequency clock completes the low power mode wake-up control, the internal low-frequency clock or the external low-frequency clock is controlled to enter the disabled state.

[0051] Optionally, after the chip system switches from normal power consumption mode to low power consumption mode and controls the internal low-frequency clock or the external low-frequency clock to enter the disabled state, step S304 may be performed. In order to save current power consumption, after entering the low power consumption mode, the internal low-frequency clock or the external low-frequency clock controlled by the control mode switch is turned off. If a trigger from an external wake-up source is received, the low power consumption mode can be awakened, and the hardware turns on the low-frequency clock again. Whether to turn on the internal low-frequency clock or the external low-frequency clock needs to be determined according to the clock selection signal of the external wake-up source, so as to avoid the chip system being locked in the low power consumption mode and improve the reliability of the chip system.

[0052] Based on the same concept, an embodiment of the present invention further provides a clock switching circuit. Figure 4 A schematic diagram of a clock switching circuit according to an embodiment of the present invention is shown in FIG. Figure 4 As shown, the clock switching circuit provided in the embodiment of the present invention can execute the clock switching method provided in any embodiment of the present invention. Specifically, the clock switching circuit includes: an internal low-frequency clock module 11, an external low-frequency clock module 12, a clock signal output module 13 and a mode control module 14;

[0053] The internal low-frequency clock module 11 is used to output the internal low-frequency clock to the clock signal output module 13 when in an enabled state; the external low-frequency clock module 12 is used to output the external low-frequency clock to the clock signal output module 13 when in an enabled state;

[0054] The clock signal output module 13 is used to control the internal low-frequency clock to enter the enabled state and select the internal low-frequency clock to be output to the mode control module 14 when the chip system switches modes. If the internal low-frequency clock and the external low-frequency clock are both configured to be enabled, the internal low-frequency clock or the external low-frequency clock is selected according to the set selection rules and output to the mode control module 14.

[0055] When switching from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock is output to the mode control module 14 , the internal low frequency clock module 11 and the external low frequency clock module 12 enter a disabled state.

[0056] In an embodiment of the present invention, when the chip system switches between normal power consumption mode and low power consumption mode, the mode switching can be controlled by an internal low-frequency clock or an external low-frequency clock. Specifically, when the internal low-frequency clock is in a disabled state, the internal low-frequency clock is controlled to enter an enabled state and assist in the control of the above-mentioned mode switching; and when both the internal low-frequency clock and the external low-frequency clock are in an enabled state, the internal low-frequency clock or the external low-frequency clock is selected to assist in the mode switching according to the setting rules defined by the chip system. That is, in this embodiment, during the mode switching process, the internal low-frequency clock or the external low-frequency clock always assists in the mode switching, and the chip system will not be locked or abnormal due to forgetting to turn on the internal low-frequency clock before the mode switching, thereby improving the stability of the mode switching process and the chip system. In addition, when the chip system completes the mode switching and enters the low power consumption mode, the internal low-frequency clock or the external low-frequency clock that controls the mode switching is entered into a disabled state, effectively reducing the current consumption of the low-frequency clock in the low power consumption mode and avoiding unnecessary power consumption.

[0057] Optional, Figure 5 A structural diagram of another clock switching circuit provided in an embodiment of the present invention, the clock switching circuit may also include: an external low-frequency clock monitoring module 15; the external low-frequency clock monitoring module 15 is used to perform a safety detection operation on the external low-frequency clock in an enabled state, and send an alarm signal to the clock signal output module 13 when the external low-frequency clock fails the safety detection operation; so that the clock signal output module 13 selects the internal low-frequency clock to output to the mode control module 14.

[0058] Optional, continue to refer to Figure 4 and Figure 5The chip system is used to output a first enable signal da_lsi_en to the internal low-frequency clock module 11, so that the internal low-frequency clock module 11 switches between an enabled state and a disabled state; the chip system is used to output a second enable signal da_lse_en to the external low-frequency clock module 12, so that the external low-frequency clock module 12 switches between an enabled state and a disabled state; the chip system is also used to output a third enable signal lsecsson_en to the external low-frequency clock monitoring module 15, so that the external low-frequency clock monitoring module 15 switches between an enabled state and a disabled state; the chip system is also used to output an external wake-up source clock selection signal lse_lsi_sel to the clock signal output module 13; the clock signal output module 13 is used to select the internal low-frequency clock or the external low-frequency clock according to the external wake-up source clock selection signal lse_lsi_sel and output it to the mode control module 14.

[0059] Figure 6 A timing diagram of a clock switching circuit provided by an embodiment of the present invention. Specifically, Figure 4 、 Figure 5 and Figure 6As shown, upon power-up, the chip system performs the following initialization configuration: enabling the LSI clock, enabling the LSE clock, enabling LSE clock monitoring, and selecting the clock source for waking up from low-power mode: lsi_lse_sel. da_lsi_en is the enable signal for the internal RC oscillator LSI clock; da_lse_en is the enable signal for the external crystal oscillator LSE clock; lsecsson_en is the enable signal for the external crystal oscillator LSE clock safety monitoring; lse_lsi_sel is the clock source selection signal for waking up from low-power mode; a value of 1 selects the LSE clock, and a value of 0 selects the LSI clock; lsecssd is the LSE clock loss alarm signal; a value of 1 indicates an LSE clock loss alarm, and a value of 0 indicates no alarm; ad_lsi_clk is the internal RC oscillator LSI clock output; ad_lse_clk is the external crystal oscillator LSE clock output; and lsi_lse_clk is the clock output for waking up from low-power mode. The RC oscillator LSI clock module generates the LSI clock. When the enable signal da_lsi_en is 0, the LSE clock module does not operate to save power and outputs ad_lsi_clk as 0. When the enable signal is 1, it outputs ad_lsi_clk. The external crystal oscillator LSE clock module generates the LSE clock. When the enable signal da_lse_en is 0, the LSE clock module does not operate to save power and outputs ad_lse_clk as 0. When the enable signal is 1, if the external crystal oscillator is functioning properly, it outputs ad_lse_clk; otherwise, it outputs ad_lse_clk as 0. The LSE clock monitoring module monitors whether the LSE clock is outputting normally. When the enable signal lsecsson_en is 0, the chip will not operate to save power, and the lse clock loss alarm lsecssd will be 0. When lsecsson_en is 1, da_lse_en is 1, and da_lsi_en is 1, and the lsi clock is normally output, if the lse clock is lost, the lse clock loss alarm lsecssd will be 1; otherwise, the lse clock loss alarm lsecssd will be 0. The mode control module is used to control the chip system's switching between low-power mode and normal power mode. If lsi_lse_clk has a stable clock output, the low-power mode switch can be completed; otherwise, the low-power mode switch may fail.

[0060] In normal operation, the default value of the da_lsi_en register is 1, which means the lsi clock is on by default, and the default value of the da_lse_en register is 0, which means the lse clock is off by default. Users can arbitrarily switch the lsi and lse clocks through the software configuration register. In normal power mode, users can arbitrarily switch the lsi and lse clocks. Before entering low power mode, if the user turns off the lsi and lse clocks through the configuration register, and then sends the WFI or WFE instruction to enter low power mode, the hardware will automatically turn on the lsi clock. After completing the switch from normal power mode to low power mode, the hardware will automatically turn off the lsi clock. When an external wake-up source triggers the wake-up of low power mode, the hardware will automatically turn on the lsi clock. After completing the wake-up from low power mode, the hardware will automatically turn off the lsi clock. If the user only turns off the lsi clock through the configuration register and the lse clock is on, because the lse clock may be lost, the hardware will automatically turn on the lsi clock to complete the switch from normal power mode to low power mode. After completing the switch, the hardware will automatically turn off the lsi clock. , when the external wake-up source triggers the low power mode to wake up, the LSI clock is turned on asynchronously, and after waking up, the LSI clock is automatically turned off; if the user turns on both the LSI and LSE clocks, the LSI or LSE clock can be selected to wake up the low power mode by configuring the register. If the software selects LSE, the hardware will monitor whether the LSE security detection enable is turned on. If the LSE security monitoring enable is turned on and there is no LSE loss alarm, LSE will be selected. Otherwise, the hardware will switch to LSI to complete the switch from normal power mode to low power mode. The hardware will automatically turn off the LSI or LSE clock, and when the external trigger source triggers the low power mode to wake up, the LSI or LSE clock will be turned on asynchronously, and then automatically turned off after waking up.

[0061] The present invention uses a switching circuit that dynamically adapts the LSI and LSE clocks to avoid system lockups and anomalies when the system switches to a low-power mode, thereby improving reliability. At the same time, no system-level intervention is required, further reducing power consumption in the low-power mode, improving overall stability, and extending battery life.

[0062] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A clock switching method, characterized in that: include: When the chip system performs mode switching, if the internal low-frequency clock is configured to be in a non-enabled state, the internal low-frequency clock is controlled to enter an enabled state and the internal low-frequency clock is selected for mode switching control; the chip system includes a normal power consumption mode and a low power consumption mode; When the chip system performs mode switching, if both the internal low-frequency clock and the external low-frequency clock are configured to be enabled, the internal low-frequency clock or the external low-frequency clock is selected according to a set selection rule to perform mode switching control; When the chip system switches from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock performs mode switching control, the internal low frequency clock or the external low frequency clock is controlled to enter a disabled state.

2. The clock switching method according to claim 1, wherein: The mode switching includes: Switching from the normal power consumption mode to the low power consumption mode; and Switch from the low power consumption mode to the normal power consumption mode.

3. The clock switching method according to claim 1, wherein: Selecting the internal low-frequency clock or the external low-frequency clock to perform mode switching control according to a set selection rule includes: Detect the low-frequency clock configured by the chip system for mode switching control; If the low-frequency clock configured by the chip system for mode switching control is an internal low-frequency clock, the internal low-frequency clock is selected for mode switching control; If the low-frequency clock configured by the chip system for mode switching control is an external low-frequency clock, a safety detection operation is performed on the external low-frequency clock; if the external low-frequency clock passes the safety detection operation, the external low-frequency clock is selected for mode switching control; if the external low-frequency clock fails the safety detection operation, the internal low-frequency clock is selected for mode switching control.

4. The clock switching method according to claim 3, wherein: Performing a security detection operation on the external low-frequency clock includes: When the external low-frequency clock is in a safety detection enabled state, monitoring whether the external low-frequency clock generates a loss warning; if so, determining that the external low-frequency clock fails the safety detection operation; if not, determining that the external low-frequency clock passes the safety detection operation; When the external low-frequency clock is in a safety detection disabled state, it is determined that the external low-frequency clock fails the safety detection operation.

5. The clock switching method according to claim 1, wherein: After the chip system switches from the normal power consumption mode to the low power consumption mode and controls the internal low-frequency clock or the external low-frequency clock to enter a disabled state, the method further includes: If an external wake-up source triggers the low power consumption mode to be awakened, the internal low-frequency clock or the external low-frequency clock is controlled to enter an enabled state and low power consumption mode wake-up control is performed; After the internal low-frequency clock or the external low-frequency clock completes the low-power mode wake-up control, the internal low-frequency clock or the external low-frequency clock is controlled to enter a disabled state.

6. The clock switching method according to claim 1, wherein: If the internal low-frequency clock is configured to be in a disabled state, controlling the internal low-frequency clock to enter an enabled state and selecting the internal low-frequency clock for mode switching control includes: If the external low-frequency clock is configured to be in an enabled state and the internal low-frequency clock is configured to be in a disabled state, controlling the internal low-frequency clock to enter an enabled state and selecting the internal low-frequency clock for mode switching control; If the external low-frequency clock is configured as a disabled state and the internal low-frequency clock is configured as a disabled state, the internal low-frequency clock is controlled to enter an enabled state and the internal low-frequency clock is selected for mode switching control.

7. A clock switching circuit, characterized in that: The clock switching method according to any one of claims 1 to 6 above can be executed, wherein the clock switching circuit comprises: an internal low-frequency clock module, an external low-frequency clock module, a clock signal output module, and a mode control module; The internal low-frequency clock module is used to output the internal low-frequency clock to the clock signal output module in an enabled state; the external low-frequency clock module is used to output the external low-frequency clock to the clock signal output module in the enabled state; The clock signal output module is used to, when the chip system performs mode switching, if the internal low-frequency clock is configured to be in a non-enabled state, control the internal low-frequency clock to enter an enabled state and select the internal low-frequency clock to be output to the mode control module; if both the internal low-frequency clock and the external low-frequency clock are configured to be in an enabled state, select the internal low-frequency clock or the external low-frequency clock to be output to the mode control module according to a set selection rule; When switching from the normal power consumption mode to the low power consumption mode, after the internal low frequency clock or the external low frequency clock is output to the mode control module, the internal low frequency clock module and the external low frequency clock module enter a disabled state.

8. The clock switching circuit according to claim 7, wherein: Also includes: External low-frequency clock monitoring module; The external low-frequency clock monitoring module is used to perform a safety detection operation on the external low-frequency clock in an enabled state, and send an alarm signal to the clock signal output module when the external low-frequency clock fails the safety detection operation; The clock signal output module selects the internal low-frequency clock and outputs it to the mode control module.

9. The clock switching circuit according to claim 8, wherein: The chip system is used to output a first enable signal to the internal low-frequency clock module to switch the internal low-frequency clock module between an enabled state and a disabled state; The chip system is used to output a second enable signal to the external low-frequency clock module, so that the external low-frequency clock module switches between an enabled state and a disabled state; The chip system is further configured to output a third enable signal to the external low-frequency clock monitoring module, so as to switch the external low-frequency clock monitoring module between an enabled state and a disabled state.

10. The clock switching circuit according to claim 8, wherein: The chip system is also used to output an external wake-up source clock selection signal to the clock signal output module; the clock signal output module is used to select the internal low-frequency clock or the external low-frequency clock according to the external wake-up source clock selection signal and output it to the mode control module.

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