Pixel steady voltage array substrate avoiding metal over-etching and manufacturing method thereof

Abstract

The application relates to the technical field of display, and provides a pixel voltage stabilization array substrate capable of avoiding metal over-etching, which comprises a glass substrate, a first metal layer plated on the upper surface of the glass substrate and forming spacedly distributed gate electrodes, CK signal wires for controlling the gate electrodes and CK signal wires for controlling a conductive layer, a gate insulation layer plated on the upper surface of the glass substrate and the first metal layer, an active layer plated on the upper surface of the gate insulation layer, a second metal layer plated on the upper surface of the gate insulation layer and forming spacedly distributed source electrodes, drain electrodes and first signal connecting wires, a conductive layer plated on the upper surface of a passivation layer and also having second signal connecting wires plated on the upper surface of the passivation layer, and a pixel electrode plated on the upper surface of the passivation layer. The application has the advantage that the potential of the conductive layer is opposite to the potential of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are counteracted, and the Feedthrough voltage is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of displays, and in particular to a pixel voltage-stabilizing array substrate that avoids metal over-etching and a manufacturing method thereof. Background Art

[0002] For TFT-LCD displays, the side of the TFT connected to the pixel electrode is generally called the drain, and the capacitance formed between the drain and the gate metal is called the parasitic capacitance C. gd The gate of the TFT device is connected to the horizontally distributed gate line to control the on and off of the TFT device; the source of the TFT device is connected to the vertically distributed data line to write the data voltage to be displayed into the TFT device; when the TFT is turned on, the source and drain are connected, the data voltage enters the drain and then reaches the liquid crystal capacitor Cst through the pixel electrode to adjust the transmittance of the liquid crystal; when the TFT is turned off, the source and drain are cut off and disconnected, and the data voltage of the source cannot enter the drain. The data voltage of the source changes periodically between positive and negative polarity, and is the deflection voltage that causes the liquid crystal to produce positive and negative polarity.

[0003] Combine Figure 1 and Figure 2 At the moment when TFT is turned off, the gate voltage V g From the high level V high The V low , due to the parasitic capacitance C gd The existence of V g The instantaneous change is coupled to the drain, causing the drain voltage to drop. Since the TFT device is turned off at this time, the voltage difference between the pixel electrode and the drain will cause the pixel electrode voltage to jump. This jump value ΔV is called the feedthrough voltage. Figure 2 In the waveform diagram, V g is the gate voltage, V d is the ideal drain voltage, It is the actual common electrode voltage provided, that is, the center point of the actual positive and negative polarity deflection voltage provided, V p (t) is the actual pixel electrode voltage, V com It is the common electrode voltage that keeps the voltage at both ends of the liquid crystal the same in the positive and negative polarity states. offset is the deviation between the ideal common electrode voltage and the actual common electrode voltage, Tf is the switching period of the TFT device, V lc >V com It is the area where the pixel electrode voltage is greater than the common electrode voltage in the current ideal state, V lc <V com This is the area where the pixel electrode voltage is lower than the common electrode voltage in the current ideal state.

[0004] like Figure 2 As shown, due to the existence of the Feedthrough voltage, the ideal common electrode V com The dot deviates from the center of the actual positive and negative polarity deflection voltages. This means that the ideal common electrode voltage changes, but the actual positive and negative polarity deflection voltages remain unchanged. This results in different voltages across the liquid crystal in the positive and negative polarity states. This causes different deflection angles of the liquid crystal in the positive and negative polarity states, resulting in different light transmission through the array substrate, causing flicker on the LCD screen. Therefore, reducing the feedthrough voltage is a problem that should be solved at present. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a pixel voltage-stabilizing array substrate and its manufacturing method that avoids metal over-etching. By providing a conductive layer above the drain electrode, the potential of the conductive layer is opposite to that of the gate electrode. The coupling effect of the gate on the drain electrode and the coupling effect of the conductive layer on the drain electrode offset each other, thereby reducing the feedthrough voltage and helping to stabilize the voltage of the pixel electrode.

[0006] The present invention is achieved in that:

[0007] A pixel voltage-stabilizing array substrate for preventing metal over-etching, comprising:

[0008] glass substrate;

[0009] a first metal layer, plated on the upper surface of the glass substrate, forming spaced-apart gates, a CK signal trace for controlling the gates, and a CK signal trace for controlling the conductive layer, wherein the potential of the CK signal trace for controlling the gates is opposite to the potential of the CK signal trace for controlling the conductive layer;

[0010] a gate insulating layer, plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with a first hole, a second hole, and a third hole, the gate being exposed through the first hole, the CK signal trace of the control gate being exposed through the second hole, and the CK signal trace of the control conductive layer being exposed through the third hole;

[0011] an active layer, plated on the upper surface of the gate insulating layer and located directly above the gate;

[0012] a second metal layer, plated on the upper surface of the gate insulating layer, forming a source electrode, a drain electrode, and a first signal connection line that are spaced apart, the source electrode being connected to the left end of the active layer, the drain being connected to the right end of the active layer, the right end of the first signal connection line passing through the first hole to be connected to the gate electrode, and the left end of the first signal connection line passing through the second hole to be connected to the CK signal line of the control gate electrode;

[0013] A passivation layer is plated on the upper surface of the gate insulation layer, the active layer and the second metal layer, the passivation layer is provided with a fourth hole and a fifth hole, the fourth hole is communicated with the third hole, the CK signal wire of the control conductive layer is exposed to the fourth hole, and the drain electrode is exposed to the fifth hole;

[0014] A conductive layer is plated on the upper surface of the passivation layer and directly above the drain electrode, a second signal connecting wire is also plated on the upper surface of the passivation layer, the conductive layer is connected with the right end of the second signal connecting wire, and the left end of the second signal connecting wire is connected with the CK signal wire of the control conductive layer through the fourth hole and the third hole.

[0015] A pixel electrode is plated on the upper surface of the passivation layer, and the lead wire of the pixel electrode is connected with the drain electrode through the fifth hole.

[0016] Further, the display panel further comprises:

[0017] The second metal layer also forms the TP wires which are distributed at intervals.

[0018] An outer insulation layer is plated on the upper surface of the pixel electrode, the conductive layer and the passivation layer, the outer insulation layer is also provided with a sixth hole, the sixth hole penetrates the passivation layer, and the TP wire is exposed to the sixth hole.

[0019] A common electrode is plated on the upper surface of the outer insulation layer, and the common electrode is connected with the TP wire through the sixth hole.

[0020] Further, the first metal layer is a three-layer structure of Ti / AL / Ti, and the second metal layer is a three-layer structure of MO / AL / MO.

[0021] Further, the gate insulation layer is a single-layer structure of SiOx or a double-layer structure of SiNx / SiOx, the passivation layer is made of SiO2, and the outer insulation layer is made of SiOx, SiNO or SiNx.

[0022] Further, the active layer is made of IGZO, and the conductive layer, the pixel electrode and the common electrode are all made of ITO.

[0023] Further, a complementary capacitor is formed between the conductive layer and the drain electrode, a parasitic capacitor is formed between the gate electrode and the drain electrode, and the capacitance of the complementary capacitor is equal to that of the parasitic capacitor.

[0024] Further, the conductive layer and the second signal connecting wire do not cover the channel of the active layer.

[0025] A method for manufacturing a pixel voltage-stabilizing array substrate that avoids metal over-etching includes the following steps:

[0026] S1. Plate a first metal layer on the upper surface of a glass substrate to form spaced-apart gates, a CK signal trace for controlling the gates, and a CK signal trace for controlling the conductive layer. The potential of the CK signal trace for controlling the gates is opposite to that of the CK signal trace for controlling the conductive layer.

[0027] S2, coating a gate insulating layer on the upper surface of the glass substrate and the first metal layer;

[0028] S3, depositing an active layer on the upper surface of the gate insulating layer, wherein the active layer is located directly above the gate;

[0029] S4, opening a first hole, a second hole, and a third hole in the gate insulating layer, wherein the gate is exposed through the first hole, the CK signal trace of the control gate is exposed through the second hole, and the CK signal trace of the control conductive layer is exposed through the third hole;

[0030] S5. Plate a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode, and a first signal connection line that are spaced apart, wherein the source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, the right end of the first signal connection line passes through the first hole and is connected to the gate electrode, and the left end of the first signal connection line passes through the second hole and is connected to the CK signal line of the control gate electrode;

[0031] S6, coating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, and the second metal layer, wherein the passivation layer first covers the third hole, and then a fourth hole and a fifth hole are formed in the passivation layer;

[0032] The fourth and fifth holes are etched simultaneously. The passivation layer is etched at the location of the fourth hole until the fourth hole is connected to the third hole, and the CK signal trace of the control conductive layer is exposed through the fourth hole. The passivation layer is etched at the location of the fifth hole until the drain is exposed.

[0033] S7. A conductive layer, a second signal connection line, and a pixel electrode are plated on the upper surface of the passivation layer in a distributed manner at intervals, wherein the conductive layer is located directly above the drain electrode, the conductive layer is connected to the right end of the second signal connection line, the left end of the second signal connection line passes through the fourth and third holes and is connected to the CK signal line of the control conductive layer, and the lead of the pixel electrode passes through the fifth hole and is connected to the drain electrode.

[0034] Furthermore, the method further comprises the following steps:

[0035] In the S5, the second metal layer also forms the TP trace distributed at intervals;

[0036] S8, plating an outer insulating layer on the upper surface of the pixel electrode, the conductive layer and the passivation layer, the outer insulating layer being provided with a sixth hole, the sixth hole penetrating the passivation layer, and the TP trace being exposed in the sixth hole;

[0037] S9, plating a common electrode on the upper surface of the outer insulating layer, the lead of the common electrode penetrating the sixth hole and being connected with the TP trace.

[0038] Further, the first metal layer is a three-layer structure of Ti / AL / Ti, and the second metal layer is a three-layer structure of MO / AL / MO.

[0039] The present application has the following advantages: 1. The conductive layer is arranged above the drain electrode, a supplementary capacitor is formed between the conductive layer and the drain electrode, the signal of the gate electrode is provided by the CK signal trace for controlling the gate electrode, the signal of the conductive layer is provided by the CK signal trace for controlling the conductive layer, the potential of the conductive layer is opposite to that of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are counteracted, the voltage difference between the pixel electrode and the drain electrode is reduced, the Feedthrough voltage is reduced, the voltage of the pixel electrode is stabilized, and the picture flicker of the liquid crystal display is reduced; when the size of the supplementary capacitor is equal to that of the parasitic capacitor, the Feedthrough voltage is eliminated, and the picture display stability of the liquid crystal display is improved. 2. The conductive layer is arranged at the position close to the contact between the drain electrode and the active layer, the field intensity at this position is larger, the Schottky barrier formed by the contact between the semiconductor of the active layer and the metal wire of the drain electrode can be reduced, the contact resistance can be reduced, and the on-state current is increased. 3. ITO has good conductivity and light transmittance, the conductive layer of the array substrate and the pixel electrode of the present application are both made of ITO, so the conductive layer and the pixel electrode can be formed in the same process, the substrate structure is simplified, and the production capacity is improved. 4. The hole is pre-formed in the gate insulating layer above the CK signal trace for controlling the conductive layer, the situation that the metal of the outermost layer of the drain electrode is over-etched due to the different depths of the two hole positions for reaching the CK signal trace for controlling the conductive layer and the drain electrode after the passivation layer is plated is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0040] The present application will be further described in connection with the embodiments and with reference to the accompanying drawings.

[0041] Figure 1 is a schematic diagram of the parasitic capacitor between the gate electrode and the drain electrode of the TFT device in the background art.

[0042] Figure 2is the schematic diagram of the ideal state of the common electrode V com is the schematic diagram of the pixel deviation.

[0043] Figure 3 is the design diagram of the pixel stable array substrate of the present application.

[0044] Figure 4 is the circuit schematic diagram of the first row TFT device of the array substrate. Figure 3

[0045] Figure 5 is the circuit schematic diagram of the second row TFT device of the array substrate. Figure 3

[0046] Figure 6 is the timing diagram of the first CK signal trace, the second CK signal trace, the third CK signal trace and the fourth CK signal trace.

[0047] Figure 7 is the top view schematic diagram of the pixel stable array substrate of the present application.

[0048] Figure 8.1 is the manufacturing process of the pixel stable array substrate of the present application. Figure One .

[0049] Figure 8.2 is the manufacturing process of the pixel stable array substrate of the present application. Figure Two .

[0050] Figure 8.3 is the manufacturing process of the pixel stable array substrate of the present application. Figure Three .

[0051] Figure 8.4 is the manufacturing process of the pixel stable array substrate of the present application. Figure Four .

[0052] Figure 8.5 is the manufacturing process of the pixel stable array substrate of the present application. Figure Five .

[0053] Figure 8.6 is the manufacturing process of the pixel stable array substrate of the present application. Figure Six .

[0054] Figure 8.7 is the manufacturing process of the pixel stable array substrate of the present application. Figure Seven .

[0055] ​​Figure 8.8 FIG8 is a flowchart of the manufacturing process of the pixel voltage-stabilizing array substrate for avoiding metal over-etching according to the present invention.

[0056] Figure 8.9 FIG9 is a ninth flow chart of the manufacturing process of the pixel voltage-stabilizing array substrate for avoiding metal over-etching according to the present invention.

[0057] Figure 8.9 1 is a schematic diagram showing that a gate insulating layer above a CK signal line of a control conductive layer is not drilled in an embodiment of the present invention.

[0058] Figure 9.1 yes Figure 9.2 Schematic diagram of etching the fourth and fifth holes in the passivation layer simultaneously.

[0059] Figure 9.1 yes Figure 9.3 The fourth hole is then etched downwards to reach the reverse CK signal line.

[0060] Reference numerals: glass substrate 1;

[0061] Gate 2;

[0062] CK signal trace 3 of the control gate; CK1 signal trace 31; CK2 signal trace 32;

[0063] CK signal trace 4 of the control conductive layer; CK3 signal trace 41; CK4 signal trace 42;

[0064] Gate insulating layer 5; first hole 51; second hole 52; third hole 53;

[0065] Active layer 6; source electrode 7; drain electrode 8;

[0066] First signal connection line 9; right end 91 of the first signal connection line; left end 92 of the first signal connection line;

[0067] Passivation layer 10; fourth hole 101; fifth hole 102;

[0068] Conductive layer 20; second signal connection line 201;

[0069] Pixel electrode 30;

[0070] TP trace 40 ; outer insulating layer 50 ; sixth hole 501 ; common electrode 60 . DETAILED DESCRIPTION

[0071] The embodiment of the present application provides a pixel voltage stabilization array substrate avoiding metal over-etching and a manufacturing method thereof, solves the flickering of a liquid crystal display picture caused by the existence of a Feedthrough voltage in the background art, realizes reduction of the Feedthrough voltage, helps voltage stabilization of a pixel electrode, liquid crystal display picture stabilization, and avoids metal over-etching of an outermost layer of a drain electrode.

[0072] The technical solution in the embodiment of the present application is as follows to solve the above-mentioned shortcomings:

[0073] The main improvement of the present application is that a conductive layer is plated above the drain electrode after the passivation layer is plated, and the conductive layer and the drain electrode form a complementary capacitor C 补充 The potential of the conductive layer is always opposite to the potential of the gate of the TFT array substrate at any time, and there is a parasitic capacitor C gd between the drain electrode and the gate electrode. In this way, the coupling effect of the gate on the drain electrode and the coupling effect of the conductive layer on the drain electrode are offset to each other, so that the voltage difference generated between the pixel electrode and the drain electrode is reduced, the voltage jump of the pixel electrode is reduced, and the Feedthrough voltage is reduced. The signal of the gate is provided by a forward CK signal wire, and the signal of the conductive layer is provided by a reverse CK signal wire. When the size of the complementary capacitor C 补充 is consistent with the size of the parasitic capacitor C gd , the Feedthrough voltage caused by the signal change of the gate can be eliminated. The complementary capacitor C 补充 and the parasitic capacitor C gd can be made to have the same size by adjusting the area directly opposite to the conductive layer and the distance of the film layer.

[0074] A third hole is pre-formed in the gate insulating layer above the CK signal wire of the conductive layer, the first hole, the second hole and the third hole are etched at the same time, and then the fourth hole and the fifth hole are etched after the passivation layer is plated. The etching depth of the fourth hole and the fifth hole is the same, the drain electrode is exposed to the fifth hole when the fourth hole communicates with the third hole, so that the metal over-etching of the outermost layer of the drain electrode is avoided.

[0075] In order to better understand the above technical solution, the above technical solution will be described in detail in combination with the drawings of the specification and the specific embodiments.

[0076] Reference Figure 9.2 to the preferred embodiment of the present application.

[0077] A pixel voltage stabilization array substrate avoiding metal over-etching comprises:

[0078] a glass substrate 1;

[0079] A first metal layer is plated on the upper surface of the glass substrate 1, forming a gate 2, a CK signal line 3 for controlling the gate, and a CK signal line 4 for controlling the conductive layer. The potential of the CK signal line 3 for controlling the gate is opposite to the potential of the CK signal line 4 for controlling the conductive layer.

[0080] a gate insulating layer 5, plated on the upper surfaces of the glass substrate 1 and the first metal layer, and having a first hole 51, a second hole 52, and a third hole 53 formed therein; the gate 2 is exposed through the first hole 51, the CK signal trace 3 for controlling the gate is exposed through the second hole 52, and the CK signal trace 4 for controlling the conductive layer is exposed through the third hole 53;

[0081] An active layer 6 is plated on the upper surface of the gate insulating layer 5 and is also located directly above the gate 2;

[0082] A second metal layer is plated on the upper surface of the gate insulating layer 5, forming a source electrode 7, a drain electrode 8 and a first signal connection line 9 that are spaced apart. The source electrode 7 is connected to the left end of the active layer 6, and the drain electrode 8 is connected to the right end of the active layer 6. The right end 91 of the first signal connection line passes through the first hole 51 to connect to the gate 2, and the left end 92 of the first signal connection line passes through the second hole 52 to connect to the CK signal line 3 of the control gate.

[0083] A passivation layer 10 is plated on the upper surfaces of the gate insulating layer 5, the active layer 6, and the second metal layer. The passivation layer 10 is provided with a fourth hole 101 and a fifth hole 102. The fourth hole 101 communicates with the third hole 53. The CK signal trace 4 of the control conductive layer is exposed through the fourth hole 101, and the drain electrode 8 is exposed through the fifth hole 102.

[0084] A conductive layer 20 is plated on the upper surface of the passivation layer 10 and is also located directly above the drain electrode 8. A second signal connection line 201 is also plated on the upper surface of the passivation layer 10. The conductive layer 20 is connected to the right end of the second signal connection line 201. The left end of the second signal connection line 201 passes through the fourth hole 101 and the third hole 53 to connect to the CK signal line 4 of the control conductive layer.

[0085] The pixel electrode 30 is plated on the upper surface of the passivation layer 10 , and the lead of the pixel electrode 30 passes through the fifth hole 102 and is connected to the drain electrode 8 .

[0086] In the present application, a conductive layer 20 is arranged above the drain 8, a supplementary capacitance is formed between the conductive layer 20 and the drain 8, the signal of the gate 2 is provided by the CK signal line 3 which controls the gate, the signal of the conductive layer 20 is provided by the CK signal line 4 which controls the conductive layer, the potential of the conductive layer 20 is opposite to the potential of the gate 2, the coupling effect of the gate 2 to the drain 8 and the coupling effect of the conductive layer 20 to the drain 8 are counteracted, the voltage difference between the pixel electrode 30 and the drain 8 is reduced, thus the Feedthrough voltage is reduced, the picture flicker of the liquid crystal display is reduced; when the size of the supplementary capacitance is equal to the size of the parasitic capacitance, the Feedthrough voltage is eliminated, the voltage of the pixel electrode 30 is stabilized, and the picture display stability of the liquid crystal display is improved; the V com point of the common electrode 6050 deviates from the center position of the positive and negative polarity deflection voltage actually provided; the liquid crystal keeps the same voltage value at both ends in the positive and negative polarity state, the deflection angle of the liquid crystal in the positive and negative polarity state is the same, thus the light transmittance of the array substrate is the same, and the picture of the liquid crystal display is stable.

[0087] The conductive layer 20 is arranged at the position close to the contact between the drain 8 and the active layer 6, the field intensity at the position is larger, thus the Schottky barrier formed by the contact between the semiconductor of the active layer 6 and the metal wire of the drain 8 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.

[0088] Comparison Figures 1 to 9.3Since the position of the drain electrode 8 is higher than that of the CK signal line 4 of the control conductive layer, when the fourth hole 101 and the fifth hole 102 are etched in the passivation layer 10 at the same time, the fourth hole 101 reaches the upper surface of the gate insulating layer 5 only when the fifth hole 102 reaches the upper surface of the drain electrode 8; if the third hole 53 is not set in advance, the CK signal line 4 of the control conductive layer cannot be exposed to the fourth hole 101, and in order to connect the conductive layer 20 and the CK signal line 4 of the control conductive layer in sequence, the fourth hole 101 and the fifth hole 102 must be etched downward continuously, and when the fourth hole 101 reaches the upper surface of the CK signal line 4 of the control conductive layer, the fifth hole 102 will be over-etched to the outermost metal of the drain electrode 8 due to the same etching depth, and for the MO / AL / MO three-layer structure of the drain electrode 8, the inner AL will be oxidized after the over-etching of the outermost MO, so that the contact resistance between the pixel electrode 30 and the drain electrode 8 at this time is large. If the fourth hole 101 and the fifth hole 102 are not etched at the same time, that is, the fourth hole 101 is etched twice, the fourth hole 101 and the fifth hole 102 are etched in the passivation layer 10 at the same time in the first etching, and the fourth hole 101 is etched alone in the gate insulating layer 5 in the second etching, although this method avoids the over-etching of the metal of the drain electrode 8, but due to the twice etching of the fourth hole 101, an additional etching process and a mask cost are required.

[0089] In the present application, by setting the third hole 53 in the gate insulating layer 5 above the CK signal line 4 of the control conductive layer in advance, the over-etching of the outermost metal of the drain electrode 8 caused by the different depths of the two hole positions reaching the CK signal line 4 of the control conductive layer and the drain electrode 8 after the passivation layer 10 is plated is avoided. Here, the fourth hole 101 and the fifth hole 102 are etched in the passivation layer 10 at the same time after the passivation layer 10 is plated, and when the fifth hole 102 reaches the upper surface of the drain electrode 8, the fourth hole 101 communicates with the third hole 53 in the gate insulating layer 5, so that the CK signal line 4 of the control conductive layer can be exposed to the fourth hole 101 without further etching. The conductive layer 20 is connected with the CK signal line 4 of the control conductive layer through the fourth hole 101 and the third hole 53.

[0090] Further comprising: the second metal layer also forms the TP line 40 which is distributed at intervals;

[0091] The outer insulating layer 50 is plated on the upper surfaces of the pixel electrode 30, the conductive layer 20 and the passivation layer 10, and the outer insulating layer 50 is also provided with the sixth hole 501 which penetrates the passivation layer 10, and the TP line 40 is exposed to the sixth hole 501;

[0092] A common electrode 60 is plated on the upper surface of the outer insulating layer 50, and the common electrode 60 is connected to the TP line 40 through the sixth hole 501. One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 30, and the other end is connected to the common electrode 60. The full name of the TP line 40 is Touch Panel Senser Line; the TP line 40 provides a voltage signal to the common electrode 60.

[0093] The first metal layer is a Ti / AL / Ti three-layer structure, and the second metal layer is a MO / AL / MO three-layer structure.

[0094] The gate insulating layer 5 is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer 10 is SiO2 material, and the outer insulating layer 50 is SiOx or SiNO or SiNx material.

[0095] The active layer 6 is IGZO material, the conductive layer 20, the pixel electrode 30, and the common electrode 60 are all ITO material. The second signal connection line 201 is also ITO material.

[0096] The conductive layer 20 and the drain 8 form a complementary capacitor, the gate 2 and the drain 8 form a parasitic capacitor, and the size of the complementary capacitor is equal to that of the parasitic capacitor. When the size of the complementary capacitor C 补充 is consistent with that of the parasitic capacitor C gd , the Feedthrough voltage caused by the signal change of the gate 2 can be eliminated. The size of the complementary capacitor C 补充 can be consistent with that of the parasitic capacitor C gd by adjusting the opposite area and film layer distance between the conductive layer 20 and the drain 8.

[0097] In combination Figures 8.1 to 9.3 , the conductive layer 20 and the second signal connection line 201 do not cover the channel of the active layer 6. The voltage signal of the conductive layer 20 and the second signal connection line 201 prevents the channel of the active layer 6 from being interfered, and ensures the working stability of the active layer 6.

[0098] In the embodiment, the control gate CK signal wire 3 has two wires, one of which (CK1) is connected with the gate 2 of the array substrate of the first row, and the other (CK2) is connected with the gate 2 of the array substrate of the second row; the control conductive layer CK signal wire 4 has two wires, one of which (CK3) is connected with the conductive layer 20 of the array substrate of the first row, and the other (CK4) is connected with the conductive layer 20 of the array substrate of the second row. The signal timing phase of CK1 is earlier than that of CK2 by one quarter of a cycle, and the signal timing phase of CK3 is earlier than that of CK4 by one quarter of a cycle. When the signal wire 31 of CK1 drives the gate 2 of the first row TFT device to be high, the source 7 and the drain 8 of the first row TFT device are turned on, the data voltage signal is written into the pixel electrode 30, and after one quarter of a cycle, the signal wire of CK2 drives the gate 2 of the second row TFT device to be high, the source 7 and the drain 8 of the second row TFT device are turned on, and the data voltage signal is written into the pixel electrode 30. When the signal wire 31 of CK1 is high, the signal wire 41 of CK3 is low, and when the signal wire 31 of CK1 is low, the signal wire 41 of CK3 is high; similarly, the high and low potentials of the signal wire 32 of CK2 are opposite to those of the signal wire 42 of CK4. Under the control of CK1, CK2, CK3 and CK4, the array substrate makes the display screen be sequentially lit from top to bottom or from bottom to top by one row of pixels. For example, when the CK signal wire 3 of the control gate is 10V, the CK signal wire 4 of the control conductive layer is -15V; when the CK signal wire 3 of the control gate is -15V, the CK signal wire 4 of the control conductive layer is 10V.

[0099] Further comprising a driving IC connected with the two control gate CK signal wires 3 and the two control conductive layer CK signal wires 4. The driving IC is used to give different timing signals to the two control gate CK signal wires 3 and the two control conductive layer CK signal wires 4.

[0100] The working principle of the pixel voltage stabilizing array substrate for avoiding metal over-etching of the present application is as follows:

[0101] Here, the embodiment is described by taking the single-side level transmission 4CK design as an example (note that the circuit design of the present application is not limited to single-side level transmission 4CK, but can also be double-side level transmission), and the timing diagram is as shown in Figure 7 Figure 6 is Figure 4 the circuit diagram of all pixels in the first row, Figure 3 is Figure 5 ​The circuit diagram for all pixel TFTs in the second row is shown in Figure 1. Simply put, the image is displayed by lighting up the pixels row by row, either from top to bottom or from bottom to top. Pixel lighting requires that the gate 2 corresponding to the pixel TFT device in that row be at a high potential. This allows the TFT device to turn on, allowing data signals to be written to the pixel electrode 30, thereby controlling the liquid crystal twist and illuminating the pixel. Taking the first row of pixel display as an example, when the signal line 31 of CK1 is at a high potential, the signal line 41 of CK3 is at a low potential. The high potential of the signal line 31 of CK1 is transmitted to the gate 2 of the first row, the TFT device of the first row is turned on, the signal of the pixel electrode 30 is written, and the low potential of the signal line 41 of CK3 is transmitted to the conductive layer 20 of the first row; when the signal line 31 of CK1 switches to a low potential, the signal line 41 of CK3 switches to a high potential, the gate 2 switches from a high potential to a low potential, and the parasitic capacitance formed by the gate 2 and the drain 8 will have a coupling effect, thereby pulling down the voltage of the drain 8. However, since the signal line 41 of CK3 is switched from a low potential to a high potential at this time, that is, the conductive layer 20 of the first row is switched from a low potential to a high potential, the supplementary capacitance formed by the conductive layer 20 and the drain 8 will also have a coupling effect, thereby pulling up the voltage of the drain 8. Therefore, the voltage of the drain 8 will not change due to the jump of the gate 2, that is, the voltage of the pixel electrode 30 will not change. Note that the design requires C 补充 with C gd The purpose of this design is to ensure that there are two feedthrough voltages, one increasing and one decreasing, of equal magnitude at the drain 8. Similarly, each row of TFT devices can avoid the feedthrough voltage caused by the gate 2 production jump.

[0102] From a microscopic perspective, it is actually the migration of charges between the drain 8 and the pixel electrode 30 that causes the amount of charge stored on the pixel electrode 30 to change, thereby causing the voltage to change. After the pixel electrode 30 is charged, the potential between the drain 8 and the pixel electrode 30 is equal, and no electron migration occurs between them. However, since the gate 2 voltage switches from a high potential to a low potential at this moment, this change will be coupled to the drain 8 through the parasitic capacitance formed by the gate 2 and the drain 8. At this time, a voltage difference will be generated between the drain 8 and the pixel electrode 30, causing charge migration between the drain 8 and the pixel electrode 30, thereby causing the pixel electrode 30 to change. The starting point for the present invention to solve this problem is to add a conductive layer 20, which forms a supplementary capacitor C with the drain 8. 补充 Then, opposite potential signals are given to the gate 2 and the conductive layer 20 respectively through the CK signal line 3 of the control gate and the CK signal line 4 of the control conductive layer, which offsets the coupling effect of the parasitic capacitance and the supplementary capacitance and improves the working performance of the device.

[0103] A pixel voltage-stabilized array substrate manufacturing method for avoiding metal over-etching, comprising the following steps:

[0104] S1, refer to Figure 3 A first metal layer is plated on the upper surface of the glass substrate 1 to form a gate electrode 2, a CK signal wire 3 for controlling the gate electrode, and a CK signal wire 4 for controlling the conductive layer, the potential of the CK signal wire 3 for controlling the gate electrode is opposite to the potential of the CK signal wire 4 for controlling the conductive layer; in this embodiment, the CK signal wire 3 for controlling the gate electrode has two wires, and the CK signal wire 4 for controlling the conductive layer has two wires.

[0105] The gate electrode 2 is used to turn on and off the TFT device, the CK signal wire 3 for controlling the gate electrode is used to transmit the signal of the gate electrode 2, and the CK signal wire 4 for controlling the conductive layer is used to transmit the signal of the conductive layer 20; the material of the first metal layer is selected as a Ti / AL / Ti three-layer structure or an AL / Ti stack (Ti as the top layer), the metal selected for the outer layer of the gate electrode 2 is Ti, not MO, and PVD film is formed, since Ti has strong corrosion resistance, only dry etching can be used. AL is used for conduction (which can be replaced by Cu), which can reduce impedance and power consumption; secondly, the expansion coefficient of Ti is small, which can inhibit the deformation of AL in high-temperature processing, and can also prevent the oxidation of AL.

[0106] S2, refer to Figure 8.1 A gate insulating layer 5 is plated on the upper surface of the glass substrate 1 and the first metal layer.

[0107] The gate insulating layer 5 acts as an insulating medium and also as a capacitive medium between the gate electrode 2 and the active layer 6, and is made of a single layer of SiOx or a double layer of SiNx / SiOx, and is formed by CVD. Considering the current requirements for TFT devices, which are fast response and low power consumption, these are achieved by reducing the size of the TFT device, and in order to realize the miniaturization of the device, the gate insulating layer 5 needs to select a suitable high-K material (such as HfO2), but considering that there are many defects in the interface of HfO2, if it is directly in contact with the active layer 6 or the gate electrode 2 metal, it may affect the stability of the device, so it can be considered to use SiOx or SiNx with a good interface as a contact surface, such as a three-layer structure of SiOx / HfO2 / SiOx as a GI insulating layer, in order to ensure the advantages of high-K materials, the thickness of HfO2 in the three-layer structure needs to be larger than that of SiOx.

[0108] S3, refer to Figure 8.2, depositing an active layer 6 on the upper surface of the gate insulating layer 5 , wherein the active layer 6 is located directly above the gate 2 ;

[0109] The material of the active layer 6 is a metal oxide semiconductor such as IGZO, formed by PVD, and etched by wet etching.

[0110] S4. See Figure 8.3 A first hole 51, a second hole 52, and a third hole 53 are formed in the gate insulating layer 5, wherein the gate 2 is exposed in the first hole 51, the CK signal trace 3 of the control gate is exposed in the second hole 52, and the CK signal trace 4 of the control conductive layer is exposed in the third hole 53;

[0111] For the first row of the array substrate, a second hole 52 is opened at the position of the signal trace 31 of CK1, and a third hole 53 is opened at the position of the signal trace 41 of CK3; for the second row of the array substrate, a second hole 52 is opened at the position of the signal trace 32 of CK2, and a third hole 53 is opened at the position of the signal trace 42 of CK4.

[0112] A first hole 51, a second hole 52, and a third hole 53 are formed by dry etching. The first hole 51 and the second hole 52 serve to connect the CK signal trace 3 of the control gate to the gate 2, while the third hole 53 serves to connect the CK signal trace 4 of the control conductive layer to the conductive layer 20. Here, the gate insulating layer 5 above the CK signal trace 3 of the control gate and the insulating layer above the CK signal trace 4 of the control conductive layer are etched away in the same process. This avoids the need for an extra photomask due to the different hole depths of the fourth hole 101 and the fifth hole 102 after plating the passivation layer 10, or the possibility of oxidation of the internal metal lines due to the loss of the outer protective metal layer of the drain electrode 8, which could increase contact resistance.

[0113] S5. See Figure 8.4 , a second metal layer is plated on the upper surface of the gate insulating layer 5 to form a source electrode 7, a drain electrode 8 and a first signal connection line 9 that are spaced apart. The source electrode 7 is connected to the left end of the active layer 6, and the drain electrode 8 is connected to the right end of the active layer 6. The right end 91 of the first signal connection line passes through the first hole 51 and is connected to the gate 2. The left end 92 of the first signal connection line passes through the second hole 52 and is connected to the CK signal line 3 of the control gate.

[0114] The material of the second metal layer is selected as MO / AL / MO three-layer structure, the resistance of AL is small for conducting electricity (Cu can be used instead), which can reduce impedance and power consumption; in addition, the expansion coefficients of the outer metal MO are small, which can inhibit the deformation of AL in high-temperature processing and prevent oxidation of AL. PVD film forming, acid liquid wet etching, and etching will face a problem that the gate insulating layer 5 above the CK signal wire 4 of the control conductive layer is lost due to the third hole 53, and in the process of etching the source electrode 7, the drain electrode 8 and the first signal connection wire 9 of the second metal layer, the metal wire of the CK signal wire 4 of the control conductive layer is also exposed to the acid liquid, if the outer metal of the CK signal wire 4 of the control conductive layer is also MO, it will be immediately corroded, so in the embodiment, the gate electrode 2, the CK signal wire 3 of the control gate and the CK signal wire 4 of the control conductive layer are selected as Ti / AL / Ti three-layer structure, AL / Ti double-layer structure (Ti as the top layer), because Ti surface is easy to form a layer of TiO2 protective film, and Ti as the outer metal has stronger corrosion resistance, so even if the outer metal of the CK signal wire 4 of the control conductive layer is exposed to the etching acid liquid, there is no problem.

[0115] S6、refer to Figure 8.5 The passivation layer 10 is plated on the upper surface of the gate insulating layer 5, the active layer 6 and the second metal layer, the passivation layer 10 covers the third hole 53 first, then the fourth hole 101 and the fifth hole 102 are opened in the passivation layer 10;

[0116] The fourth hole 101 and the fifth hole 102 are etched at the same time, the passivation layer 10 is etched at the position of the fourth hole 101 until the fourth hole 101 communicates with the third hole 53, and the CK signal wire 4 of the control conductive layer is exposed in the fourth hole 101, the passivation layer 10 is etched at the position of the fifth hole 102 until the drain electrode 8 is exposed;

[0117] The material of the passivation layer 10 is SiO2, CVD film formation, dry etching to form the fourth hole 101 and the fifth hole 102. The fourth hole 101 provides a connection between the CK signal line 4 of the control conductive layer and the conductive layer 20. For the first row of the array substrate, the fourth hole 101 is formed at the position of the CK3 signal line 41. For the second row of the array substrate, the fourth hole 101 is formed at the position of the CK4 signal line 42. The fifth hole 102 provides a connection between the pixel electrode 30 and the drain 8. Since the gate insulating layer 5 has been etched to form the third hole 53 at the position of the fourth hole 101 in the step S4, the etching depth of the fourth hole 101 and the fifth hole 102 is the thickness of the passivation layer 10. Therefore, the fourth hole 101 does not need to etch the gate insulating layer 5 further, which avoids the problems of the additional mask and the simultaneous etching of the fourth hole 101 and the fifth hole 102, which leads to the loss of the outer protective metal of the drain 8 and the oxidation of the internal metal line, the increase of the contact resistance, and other problems.

[0118] S7, referring to Figure 8.6 The conductive layer 20, the second signal connection line 201, and the pixel electrode 30 are plated on the upper surface of the passivation layer 10 in a spaced distribution. The conductive layer 20 is located directly above the drain 8. The conductive layer 20 is connected to the right end of the second signal connection line 201. The left end of the second signal connection line 201 is connected to the CK signal line 4 through the fourth hole 101 and the third hole 53. The lead of the pixel electrode 30 is connected to the drain 8 through the fifth hole 102.

[0119] The materials of the conductive layer 20 and the pixel electrode 30 are both ITO. The main reason is that ITO has good conductivity and light transmittance. The PVD film formation and acid wet etching are used. The conductive layer 20 is designed to be located directly above the drain 8. The purpose is to form a capacitor structure with the drain 8. The capacitance of the supplementary capacitor formed by the conductive layer 20 and the drain 8 is consistent with the capacitance of the parasitic capacitor formed by the gate 2 and the drain 8. The capacitance is equal by adjusting the facing area and the film distance of the conductive layer 20.

[0120] The method further includes the following steps:

[0121] In the step S5, the second metal layer also forms the TP line 40 in a spaced distribution.

[0122] S8, referring to Figure 8.7 The outer insulating layer 50 is plated on the upper surface of the pixel electrode 30, the conductive layer 20, and the passivation layer 10. The outer insulating layer 50 is provided with the sixth hole 501. The sixth hole 501 penetrates the passivation layer 10. The TP line 40 is exposed to the sixth hole 501.

[0123] The outer insulating layer 50 can be made of SiOx, SiNO, SiNx, etc., and formed by CVD. The insulating layer and the passivation layer 10 are dry-etched to expose the TP trace 40 , thereby providing a connection between the common electrode 60 and the TP trace 40 .

[0124] S9, see Figure 8.8 Figure 8.9 , a common electrode 60 is plated on the upper surface of the outer insulating layer 50 , and a lead of the common electrode 60 passes through the sixth hole 501 and is connected to the TP trace 40 .

[0125] The material of the common electrode 60 is ITO, mainly because ITO has good electrical conductivity and light transmittance, and can be formed by PVD and wet etched with acid solution.

[0126] One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 30 , and the other end is connected to the common electrode 60 . The full name of the TP line 40 is Touch Panel Sensor Line; the TP line 40 provides a voltage signal to the common electrode 60 .

[0127] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A pixel voltage stabilizing array substrate for preventing metal over-etching, characterized in that: include: glass substrate; a first metal layer, plated on the upper surface of the glass substrate, forming spaced-apart gates, a CK signal trace for controlling the gates, and a CK signal trace for controlling the conductive layer, wherein the potential of the CK signal trace for controlling the gates is opposite to the potential of the CK signal trace for controlling the conductive layer; a gate insulating layer, plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with a first hole, a second hole, and a third hole, the gate being exposed through the first hole, the CK signal trace of the control gate being exposed through the second hole, and the CK signal trace of the control conductive layer being exposed through the third hole; an active layer, plated on the upper surface of the gate insulating layer and located directly above the gate; a second metal layer, plated on the upper surface of the gate insulating layer, forming a source electrode, a drain electrode, and a first signal connection line that are spaced apart, the source electrode being connected to the left end of the active layer, the drain being connected to the right end of the active layer, the right end of the first signal connection line passing through the first hole to be connected to the gate electrode, and the left end of the first signal connection line passing through the second hole to be connected to the CK signal line of the control gate electrode; a passivation layer, plated on the upper surfaces of the gate insulating layer, the active layer, and the second metal layer, the passivation layer being provided with a fourth hole and a fifth hole, the fourth hole being connected to the third hole, the CK signal line of the control conductive layer being exposed through the fourth hole, and the drain being exposed through the fifth hole; a conductive layer, plated on the upper surface of the passivation layer and directly above the drain electrode; a second signal connection line is plated on the upper surface of the passivation layer; the conductive layer is connected to the right end of the second signal connection line; and the left end of the second signal connection line passes through the fourth and third holes and is connected to the CK signal line of the control conductive layer; A supplementary capacitor is formed between the conductive layer and the drain electrode, a parasitic capacitor is formed between the gate electrode and the drain electrode, and the capacitance of the supplementary capacitor is equal to that of the parasitic capacitor; The conductive layer and the second signal connection line do not cover the channel of the active layer; A pixel electrode is plated on the upper surface of the passivation layer, and a lead of the pixel electrode passes through the fifth hole and is connected to the drain electrode.

2. The pixel voltage stabilizing array substrate for avoiding metal over-etching according to claim 1, wherein: Also includes: The second metal layer also forms TP traces distributed at intervals; an outer insulating layer, plated on the upper surfaces of the pixel electrode, the conductive layer, and the passivation layer, the outer insulating layer further having a sixth hole formed therein, the sixth hole penetrating the passivation layer, and the TP trace exposed through the sixth hole; A common electrode is plated on the upper surface of the outer insulating layer, and the common electrode is further connected to the TP trace through the sixth hole.

3. The pixel voltage stabilizing array substrate for avoiding metal over-etching according to claim 2, wherein: The first metal layer is a three-layer structure of Ti / Al / Ti, and the second metal layer is a three-layer structure of MO / Al / MO.

4. The pixel voltage-stabilizing array substrate for avoiding metal over-etching according to claim 2, wherein: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer is made of SiO2, and the outer insulating layer is made of SiOx, SiNO or SiNx.

5. The pixel voltage stabilizing array substrate for avoiding metal over-etching according to claim 2, wherein: The active layer is made of IGZO material, and the conductive layer, pixel electrode and common electrode are all made of ITO material.

6. A method for manufacturing a pixel voltage-stabilizing array substrate that avoids metal over-etching, characterized in that: The following steps are involved: S1. Plate a first metal layer on the upper surface of a glass substrate to form spaced-apart gates, a CK signal trace for controlling the gates, and a CK signal trace for controlling the conductive layer. The potential of the CK signal trace for controlling the gates is opposite to that of the CK signal trace for controlling the conductive layer. S2, coating a gate insulating layer on the upper surface of the glass substrate and the first metal layer; S3, depositing an active layer on the upper surface of the gate insulating layer, wherein the active layer is located directly above the gate; S4, opening a first hole, a second hole, and a third hole in the gate insulating layer, wherein the gate is exposed through the first hole, the CK signal trace of the control gate is exposed through the second hole, and the CK signal trace of the control conductive layer is exposed through the third hole; S5. Plate a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode, and a first signal connection line that are spaced apart, wherein the source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, the right end of the first signal connection line passes through the first hole and is connected to the gate electrode, and the left end of the first signal connection line passes through the second hole and is connected to the CK signal line of the control gate electrode; S6, coating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, and the second metal layer, wherein the passivation layer first covers the third hole, and then a fourth hole and a fifth hole are formed in the passivation layer; The fourth and fifth holes are etched simultaneously. The passivation layer is etched at the location of the fourth hole until the fourth hole is connected to the third hole, and the CK signal trace of the control conductive layer is exposed through the fourth hole. The passivation layer is etched at the location of the fifth hole until the drain is exposed. S7. Plate a conductive layer, a second signal connection line, and a pixel electrode on the upper surface of the passivation layer in a distributed manner at intervals, wherein the conductive layer is located directly above the drain electrode, the conductive layer is connected to the right end of the second signal connection line, the left end of the second signal connection line passes through the fourth and third holes and is connected to the CK signal trace of the control conductive layer, and the lead of the pixel electrode passes through the fifth hole and is connected to the drain electrode; A supplementary capacitor is formed between the conductive layer and the drain electrode, a parasitic capacitor is formed between the gate electrode and the drain electrode, and the capacitance of the supplementary capacitor is equal to that of the parasitic capacitor; The conductive layer and the second signal connection line do not cover the channel of the active layer.

7. The method for manufacturing a pixel voltage-stabilized array substrate that avoids metal over-etching according to claim 6, wherein: The following steps are also included: In the step S5 , the second metal layer further forms TP traces distributed at intervals; S8, coating an outer insulating layer on the upper surfaces of the pixel electrode, the conductive layer, and the passivation layer, wherein a sixth hole is formed in the outer insulating layer, the sixth hole penetrates the passivation layer, and the TP trace is exposed in the sixth hole; S9. Plate a common electrode on the upper surface of the outer insulating layer, and connect the lead of the common electrode to the TP line through the sixth hole.

8. The method for manufacturing a pixel voltage-stabilizing array substrate that avoids metal over-etching according to claim 7, wherein: The first metal layer is a three-layer structure of Ti / Al / Ti, and the second metal layer is a three-layer structure of MO / Al / MO.

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