Method for improving floating gate sidewall etch profile

Abstract

The application provides a method for improving the etching profile of a floating gate sidewall, a substrate is provided, and a stack is formed on the substrate, the stack is composed of a pad oxide layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, a control gate polysilicon layer and a first hard mask layer, which are stacked in order from bottom to top, then an opening is formed on the first hard mask layer so that the control gate polysilicon layer below is exposed; a second hard mask layer is formed to cover the first hard mask layer and the exposed control gate polysilicon layer; an etching gas with a carbon content greater than a preset value is introduced into an etching machine, the ionized etching gas is a first ion beam, and the second hard mask layer is etched by using the first ion beam; an etching gas with a carbon content greater than a preset value is introduced into an etching machine, the ionized etching gas is a second ion beam, and the second hard mask layer is etched by using the second ion beam until the control gate polysilicon layer is exposed. The application can improve the uniformity of the critical dimension at the bottom of the etching profile to obtain a vertical etching profile, and the height of the sidewall is easy to control.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the etching profile of floating gate sidewalls. Background Technology

[0002] In the floating gate sidewall etching process, the height of the floating gate sidewall, the uniformity of its contour, and the critical dimensions and uniformity at the bottom control gate opening are all important parameters that directly affect the word line filling quality and the electrical properties of the cell devices. In some products, the floating gate sidewall etching has exhibited problems such as insufficient sidewall height, contour tilt, and uneven critical dimensions in the middle and edge areas. To solve these problems, a novel method for improving the floating gate sidewall etching contour is needed. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the etching profile of the floating gate sidewall, to solve the problems of insufficient sidewall height, profile tilt, and uneven critical dimensions in the middle and edge portions of the floating gate sidewall etching in the prior art. To achieve the above and other related objectives, this invention provides a method for improving the etching profile of the floating gate sidewall, comprising:

[0004] Step 1: Provide a substrate on which a stack is formed. The stack consists of an oxide pad layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, a control gate polysilicon layer, and a first hard mask layer stacked sequentially from bottom to top. Then, an opening is formed in the first hard mask layer to expose the control gate polysilicon layer below it.

[0005] Step 2: Form a second hard mask layer that covers the first hard mask layer and exposes the control gate polysilicon layer;

[0006] Step 3: In the etching machine, an etching gas with a carbon content greater than a preset value is introduced, and the etching gas is ionized into a first ion beam. When the first ion beam is used for etching, the second hard mask layer has a first etching selectivity relative to the control gate polysilicon. The second hard mask layer is etched by the first ion beam until a portion of the second hard mask layer remains at the bottom of the opening.

[0007] Step 4: Introduce the etching gas with a carbon content greater than the preset value into the etching machine. Ionize the etching gas to form a second ion beam. During the second ion beam etching, the second hard mask layer has a second etching selectivity relative to the control gate polysilicon. The second etching selectivity is less than the first etching selectivity. Use the second ion beam to etch the second hard mask layer until the control gate polysilicon layer is exposed.

[0008] Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0009] Preferably, the material of the inter-electrode dielectric layer in step one is silicon dioxide.

[0010] Preferably, the material of the first hard mask layer in step one is silicon dioxide.

[0011] Preferably, the material of the second hard mask layer in step two is silicon nitride.

[0012] Preferably, the etching gas in steps three and four includes at least one of C4F8, C5F8, and C4F6.

[0013] Preferably, the method of introducing an etching gas with a carbon content greater than a preset value into the etching machine in step three, and ionizing the etching gas into a first ion beam, includes: using a 27MHz radio frequency source with a power greater than 700W to ionize the etching gas, accelerating the ions formed by the ionization of the etching gas, and forming the first processed ion beam.

[0014] Preferably, in step four, the method of introducing the etching gas with a carbon content greater than the preset value into the etching machine and ionizing the etching gas into a second ion beam includes: using a 2MHz radio frequency source with a power greater than 1000W to ionize the etching gas, accelerating the ions formed by the ionization of the etching gas, and forming the second ion beam.

[0015] Preferably, the etching amount of the control gate polysilicon layer in step four is a fixed preset value.

[0016] As described above, the method for improving the etching profile of the floating gate sidewall of the present invention has the following beneficial effects: the etching process of the present invention uses a radio frequency source with high ion energy distribution and high bombardment energy, which can improve the uniformity of the key dimensions at the bottom of the etching profile and increase the physical bombardment of the bottom profile of the sidewall to obtain a vertical etching profile; the use of a high carbon content etching gas to protect the sidewall sidewall makes it easier to control the sidewall height; in the second etching, the etching selectivity of the control gate polysilicon is reduced, and after the etching amount of the control gate polysilicon is fixed, the etching amount of the sidewall is reduced, thereby increasing the height of the sidewall. Attached Figure Description

[0017] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0018] Figure 2 The diagram shown illustrates the formation of the second hard mask layer according to the present invention.

[0019] Figure 3 The diagram shown is a schematic diagram of the first etching step of this invention.

[0020] Figure 4 This is a schematic diagram of the second etching step of the present invention. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0022] Please see Figure 1 The present invention provides a method for improving the etching profile of the sidewall of a floating gate, comprising:

[0023] Step 1: Provide a substrate 101. A stack is formed on the substrate 101. The stack consists of a pad oxide layer 102, a floating gate polysilicon layer 103, an inter-electrode dielectric layer 104, a control gate polysilicon layer 105, and a first hard mask layer 106 stacked sequentially from bottom to top. The material of the pad oxide layer 102 is usually silicon dioxide. Then, an opening is formed in the first hard mask layer 106 to expose the control gate polysilicon layer 105 below it.

[0024] In an embodiment of the invention, the substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. In an embodiment of the invention, the material of the interpolar dielectric layer 104 in step one is silicon dioxide.

[0025] In an embodiment of the present invention, the material of the first hard mask layer 106 in step one is silicon dioxide.

[0026] Step 2: Form a second hard mask layer 107 covering the first hard mask layer 106 and the exposed control gate polysilicon layer 105, forming as shown in the figure. Figure 2 The structure shown.

[0027] In an embodiment of the present invention, the material of the second hard mask layer 107 in step two is silicon nitride, which can be formed by chemical vapor deposition.

[0028] Step 3, please refer to Figure 3 An etching gas with a carbon content greater than a preset value is introduced into the etching machine. The ionized etching gas is a first ion beam 109. When the first ion beam 109 etches, the second hard mask layer 107 has a first etching selectivity relative to the control gate polysilicon layer 105. The first ion beam 109 is used to etch the second hard mask layer 107 until a portion of the second hard mask layer 107 remains at the bottom of the opening. In an embodiment of the present invention, the etching gas in step three includes at least one of C4F8, C5F8, and C4F6. A high carbon content etching gas is used to protect the sidewall of the sidewall 108, which facilitates control of the height of the sidewall 108.

[0029] In an embodiment of the present invention, the method of introducing an etching gas with a carbon content greater than a preset value into the etching machine in step three, and ionizing the etching gas as a first ion beam 109, includes: using a 27MHz radio frequency source with a power greater than 700W to ionize the etching gas, accelerating the ions formed by the ionization of the etching gas to form a first processing ion beam. The use of a radio frequency source with high ion energy distribution and high bombardment energy can improve the uniformity of the key dimensions at the bottom of the etching contour.

[0030] Step 4, please refer to Figure 4 An etching gas with a carbon content greater than a preset value is introduced into the etching machine. The ionized etching gas is a second ion beam 110. When the second ion beam 110 etches, the second hard mask layer 107 has a second etching selectivity relative to the control gate polysilicon layer 105. The second etching selectivity is less than the first etching selectivity. The second hard mask layer 107 is etched by the second ion beam 110 until the control gate polysilicon layer 105 is exposed.

[0031] In an embodiment of the present invention, the etching gas in step four includes at least one of C4F8, C5F8, and C4F6. The high carbon content etching gas is used to protect the sidewall of the sidewall 108, which facilitates control of the height of the sidewall 108.

[0032] In an embodiment of the present invention, step four involves introducing an etching gas with a carbon content greater than a preset value into the etching machine. The method of ionizing the etching gas into a second ion beam 110 includes: using a 2MHz radio frequency source with a power greater than 1000W to ionize the etching gas, accelerating the ions formed by the ionization of the etching gas to form a second ion beam 110. Using a radio frequency source with high ion energy distribution and high bombardment energy can improve the uniformity of the critical dimensions at the bottom of the etching profile and reduce the etching selectivity of the second ion beam 110 for the control gate polysilicon layer 105, thereby reducing the etching of the sidewall 108 and increasing the height of the sidewall 108.

[0033] In an embodiment of the present invention, the etching amount of the control gate polysilicon layer 105 in step four is a fixed preset value. In the second etching using the second ion beam 110, the etching selectivity of the control gate polysilicon layer 105 is reduced. After the etching amount of the control gate polysilicon layer 105 is fixed, the etching amount of the sidewall 108 is reduced, thereby increasing the height of the sidewall 108.

[0034] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] In summary, the method for improving the etching profile of the floating gate sidewalls according to the present invention has the following beneficial effects: The etching process of the present invention employs a radio frequency source with high ion energy distribution and high bombardment energy, which can improve the uniformity of critical dimensions at the bottom of the etching profile and enhance the physical bombardment of the bottom profile of the sidewalls to obtain a vertical etching profile; the use of a high-carbon etching gas to protect the sidewalls facilitates control of the sidewall height; and by reducing the etching selectivity of the control gate polysilicon in the second etching process, once the etching amount of the control gate polysilicon is fixed, the etching amount of the sidewalls is reduced, thereby increasing the sidewall height. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving floating gate sidewall etch profile, comprising: At least comprising: Step one, providing a substrate, a stack layer is formed on the substrate, the stack layer is composed of a pad oxygen layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, a control gate polysilicon layer and a first hard mask layer stacked in turn from bottom to top, and then an opening is formed on the first hard mask layer so that the control gate polysilicon layer below is exposed; Step two, forming a second hard mask layer covering the first hard mask layer and the exposed control gate polysilicon layer; Step three, introducing an etching gas with a carbon content greater than a preset value into the etching machine, the etching gas with a carbon content greater than a preset value includes at least one of C4F8, C5F8, C4F6, ionizing the etching gas into a first ion beam, when the first ion beam etches, the second hard mask layer has a first etching selectivity ratio relative to the control gate polysilicon, and the second hard mask layer is etched by the first ion beam until part of the second hard mask layer remains at the bottom of the opening; wherein the method of ionizing the etching gas into the first ion beam includes: ionizing the etching gas by using a 27MHz, power greater than 700W radio frequency source, accelerating the ions formed by ionizing the etching gas to form the first ion beam; Step four, introducing the etching gas with a carbon content greater than the preset value into the etching machine, the etching gas with a carbon content greater than a preset value includes at least one of C4F8, C5F8, C4F6, ionizing the etching gas into a second ion beam, when the second ion beam etches, the second hard mask layer has a second etching selectivity ratio relative to the control gate polysilicon, the second etching selectivity ratio is less than the first etching selectivity ratio, and the second hard mask layer is etched by the second ion beam until the control gate polysilicon layer is exposed.

2. The method of claim 1, wherein: The substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method of claim 1, wherein: The material of the inter-electrode dielectric layer in step one is silicon dioxide.

4. The method of claim 1, wherein: The material of the first hard mask layer in step one is silicon dioxide.

5. The method for improving floating gate sidewall etch profile according to claim 1, wherein: The material of the second hard mask layer in step two is silicon nitride.

6. The method of claim 1, wherein: The method of introducing the etching gas with a carbon content greater than the preset value into the etching machine and ionizing the etching gas into the second ion beam in step four includes: ionizing the etching gas by using a 2MHz, power greater than 1000W radio frequency source, accelerating the ions formed by ionizing the etching gas to form the second ion beam.

7. The method for improving floating gate sidewall etch profile according to claim 1, wherein: The etching amount of the control gate polysilicon layer in step four is a fixed preset value.

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