GGNMOS Structure and Fabrication Method

Abstract

This application provides a GGNMOS structure and its fabrication method. The structure includes: a P-type substrate having a P-well and two lightly doped drain regions spaced apart within the P-well; a source; n first heavily doped regions spaced apart; m second heavily doped regions spaced apart; a first gate structure covering the P-type substrate between the two lightly doped drain regions and a portion of the surface of the two lightly doped drain regions; and a second gate structure located on the lightly doped drain regions spaced between the n first heavily doped regions. The first heavily doped regions and the lightly doped drain regions spaced between the first heavily doped regions constitute alternating heavily and lightly doped drains, where m is an integer greater than or equal to 1, n is an integer greater than or equal to 2, and m < n. By controlling the feature size of the second gate structure, the trigger voltage of the GGNMOS structure is reduced, improving the controllability of its fabrication and enhancing the uniform conduction and robustness of the ESD device array.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a GGNMOS structure and its fabrication method. Background Technology

[0002] In integrated circuits, the impact of electrostatic discharge (ESD) on chip reliability cannot be ignored. Especially with the widespread application of deep submicron and nanotechnology, the destructive effects of ESD on chips from external environment, human body, machinery, and radiation fields are even more significant.

[0003] Devices used for ESD protection mainly include diodes, GGNMOS (Gate Ground NMOS), and silicon controlled rectifiers (SCRs). Among them, GGNMOS has inherent advantages such as compatibility with CMOS process technology, fast switching response, and low on-resistance, making it one of the most commonly selected devices for ESD protection in CMOS process technology.

[0004] GGNMOS primarily uses its parasitic lateral NPN transistor to discharge large ESD currents. The turn-on voltage of this parasitic transistor depends on the avalanche breakdown voltage of the collector reverse PN junction, which is the avalanche breakdown voltage between the drain of the GGNMOS and the P-well in the substrate.

[0005] When selecting GGNMOS as an ESD protection device, a large width is required to ensure sufficient discharge current. However, due to layout limitations and current uniformity requirements, existing technologies often design GGNMOS structures as multi-finger structures. This involves fabricating multiple gates on the P-well, with each pair of source and drain forming an NPN junction called a finger. The source and drain of each GGNMOS transistor are connected via contact holes and metal interconnects to ground or electrostatic terminals, with adjacent NMOS transistors sharing a single drain. This GGNMOS structure results in a relatively high breakdown voltage between the drain and the P-well, which is detrimental to ESD protection. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a GGNMOS structure and its fabrication method to solve the problem of excessively high trigger voltage of GGNMOS as an electrostatic discharge protection device in the prior art. The technical solution is as follows:

[0007] In a first aspect, embodiments of this application provide a GGNMOS structure, including:

[0008] A P-type substrate, wherein a P-well and a first lightly doped drain region and a second lightly doped drain region are formed in the P-well;

[0009] The source is located in the first lightly doped drain region;

[0010] The first heavily doped region is set with n intervals, and the first heavily doped region is set in the second lightly doped drain region;

[0011] The third lightly doped drain regions are arranged at intervals of m, and each third lightly doped drain region is located in the second lightly doped drain region between two first heavily doped regions.

[0012] The second doped regions are set at m intervals, and each second doped region is set in the corresponding third lightly doped drain region;

[0013] A first gate structure, the first gate structure covering the P-type substrate between the first lightly doped drain region and the second lightly doped drain region, and a portion of the surface of the first lightly doped drain region and the second lightly doped drain region; and...

[0014] The second gate structure is located on the second lightly doped drain region in the interval between the n first heavily doped regions;

[0015] Where m is an integer greater than or equal to 1, n is an integer greater than or equal to 2, and m < n.

[0016] Preferably, the spacing between the second heavily doped region and the first heavily doped region is controlled by changing the feature size of the second gate structure.

[0017] Preferably, the feature size of the second gate structure is 100 nanometers to 1 micrometer.

[0018] Preferably, the second lightly doped drain region in the interval between the first heavily doped regions constitutes a drain electrode with alternating heavy and light doping.

[0019] Preferably, the dopant ions in the first lightly doped drain region, the second lightly doped drain region, and the first heavily doped region are N-type.

[0020] Preferably, the dopant ions in the third lightly doped drain region and the second heavily doped region are P-type.

[0021] Preferably, the GGNMOS structure further includes a silicide barrier layer that covers the portion of the source near the first gate structure and the first heavily doped region between the first gate structure and the second gate structure.

[0022] Preferably, the second doped region is at the same potential as the P-well.

[0023] Secondly, embodiments of this application provide a method for fabricating a GGNMOS structure, including:

[0024] A P-type substrate is provided, and a P-well is formed in the P-type substrate.

[0025] N-type ion light doping implantation is performed on the P-type substrate to form a first lightly doped drain region and a second lightly doped drain region;

[0026] Forming a first gate structure and a second gate structure;

[0027] N-type ion heavy doping implantation is performed on the P-type substrate to form a source in a first lightly doped drain region and n spaced first heavily doped regions in a second lightly doped drain region, wherein the second lightly doped drain regions in the intervals between the first heavily doped regions constitute a drain with alternating heavy and light doping.

[0028] P-type substrate is lightly doped with P-type ions to form m spaced third lightly doped drain regions in the second lightly doped drain region;

[0029] A P-type substrate is subjected to P-type ion heavy doping implantation to form m spaced-apart second heavily doped regions in a second lightly doped drain region, wherein each second heavily doped region is disposed in a corresponding third lightly doped drain region; and

[0030] A silicide barrier layer is formed on the portion of the source near the first gate structure and on the first heavily doped region between the first gate structure and the second gate structure.

[0031] Where m is an integer greater than or equal to 1, n is an integer greater than or equal to 2, and m < n.

[0032] Preferably, both the first gate structure and the second gate structure are composed of a gate oxide layer and a gate material layer stacked from bottom to top.

[0033] As described above, the GGNMOS structure and its fabrication method provided in this application have the following beneficial effects: by controlling the feature size of the second gate structure, the trigger voltage of the GGNMOS structure can be reduced, the controllability of the GGNMOS structure fabrication can be improved, and the uniform conduction and robustness of the ESD device array can be enhanced. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1The diagram shown is a cross-sectional view of the GGNMOS structure provided in an embodiment of this application.

[0036] Figure 2 The image shown is a top view of the GGNMOS structure provided in an embodiment of this application.

[0037] Figures 3-8 The diagram shows a cross-sectional view of the device in each process step of the fabrication method of the GGNMOS structure provided in the embodiments of this application. Detailed Implementation

[0038] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0039] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0042] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0043] Please see Figure 1 The diagram shows a cross-sectional view of the GGNMOS structure provided in the embodiments of this application.

[0044] like Figure 1 As shown, the GGNMOS structure includes:

[0045] A P-type substrate 100 is formed therein, including a P-well 101 and a first lightly doped drain region 102 and a second lightly doped drain region 103 spaced apart in the P-well 101.

[0046] Source 105 is located in the first lightly doped drain region 102;

[0047] n heavily doped regions 106 are spaced apart and are spaced apart in the second lightly doped drain regions 103. The second lightly doped drain regions 103 spaced apart between the first heavily doped regions 106 constitute a drain 107 with alternating heavy and light doping.

[0048] m third lightly doped drain regions 108 are spaced apart, and each third lightly doped drain region 108 is disposed in a second lightly doped drain region 103 between two first heavily doped regions 106;

[0049] m intervals are set in the second heavily doped region 109, and each second heavily doped region 109 is set in the corresponding third lightly doped drain region 108;

[0050] A first gate structure 110 covers the P-type substrate 100 between the first lightly doped drain region 102 and the second lightly doped drain region 103, as well as a portion of the surface of the first lightly doped drain region 102 and the second lightly doped drain region 103; and...

[0051] The second gate structure 111 is located on the second lightly doped drain region 103 in the interval between the n first heavily doped regions 106;

[0052] Where m is an integer greater than or equal to 1, n is an integer greater than or equal to 2, and m < n, the first gate structure 110 and the second gate structure 111 are both composed of a gate oxide layer 11a and a gate material layer 11b stacked from bottom to top.

[0053] Furthermore, the GGNMOS structure also includes a silicide barrier layer 112, which covers the portion of the source 105 near the first gate structure 110 and the first heavily doped region 106 between the first gate structure 110 and the second gate structure 111.

[0054] The silicide barrier layer 112 defines the RPO region (oxide layer) as a non-silicide region to ensure a certain resistance to prevent current from concentrating through the center GGNMOS that conducts first and causing it to burn out.

[0055] Furthermore, the GGNMOS structure also includes sidewall structures 113 located on both sides of the first gate structure 110 and the second gate structure 111. The sidewall structures 113 can block lightly doped implantation, heavily doped source / drain implantation, and can block the subsequent diffusion of implanted conductive ions into the gate material layer 11b.

[0056] Furthermore, the GGNMOS structure also includes an isolation component 115 located in the P-type substrate 100, the isolation component 115 being disposed around the source 105 and the drain 107.

[0057] Please see Figure 2 The diagram shows a top view of the GGNMOS structure provided in the embodiments of this application.

[0058] like Figure 2 As shown, the first heavily doped region 106 is spaced within the second lightly doped drain region 103, and the second lightly doped drain region 103 is not blocked by the second heavily doped region 109. From the perspective of the top view, the third lightly doped drain region 108 is completely blocked by the second gate structure 111 and the second heavily doped region 109, and the second lightly doped drain region 103 is also not blocked by the third lightly doped drain region 108.

[0059] The GGNMOS structure of this application is used for ESD protection. The first gate structure 110 and the source 105 are grounded through a metal interconnect structure, and the drain 107 is connected to the electrostatic terminal through a metal interconnect structure, that is, connected to the electrostatic terminal of the external circuit to be protected against ESD. The specific working principle is as follows:

[0060] The source 105, P-well 101, and drain 107 of the GGNMOS structure form a parasitic NPN transistor. The source 105 of the GGNMOS structure is the emitter of the NPN transistor, the P-well 101 is the base of the NPN transistor, and the drain 107 is the collector of the NPN transistor. The second heavily doped region 109 (P-type doped, at the same potential as the P-well 101) provided in the drain 107 will form a lateral Zener diode between the collector of the NPN transistor and the external circuit to be protected against ESD. When an ESD event occurs, the ESD current flows through the electrostatic terminal of the external circuit into the drain 107 and the second heavily doped region 109, and then into the P-well 101. Due to the parasitic resistance in the P-well 101, the ESD current generates a voltage difference within the P-well 101. Meanwhile, the Zener diode formed by the second heavily doped region 109 at the drain 107 creates a higher electric field, lower leakage current, and a more stable voltage difference between the drain 107 and the P-well 101. When the voltage difference exceeds the threshold voltage, the parasitic NPN transistor is in the conducting state, and current flows in from the drain 107 and finally out from the source 105, discharging the static electricity and preventing damage to the circuit. Simultaneously, the second heavily doped region 109 generates a similar effect to tip discharge, achieving ESD-assisted breakdown and enabling the GGNMOS to have a lower excitation voltage. This solves the problems of increased trigger voltage and poor static electricity leakage, providing more effective protection for the core components of the external circuit.

[0061] The GGNMOS structure provided in this application embodiment reduces the feature size (width dimension) of the second gate structure 111, increases the spacing between the second gate structures 111, and shortens the spacing between the first heavily doped region 106 and the second heavily doped region 109, thereby further reducing the trigger voltage of the GGNMOS structure. The width dimension (Poly CD) of the second gate structure 111 can be accurately controlled in terms of size and uniformity according to actual process requirements, so that a uniform and controllable second gate structure 111 can be formed on the drain 107 according to the actual width dimension of the drain 107, thereby improving the controllability of the GGNMOS structure fabrication. For example, the feature size of the second gate structure 111 is 100 nanometers to 1 micrometer. The second lightly doped drain region 103 in the interval between the first heavily doped region 106 and the first heavily doped region 106 constitutes a drain 107 with alternating heavy and light doping, which can increase the on-resistance of the drain 107, making the turn-on of the ESD device array more uniform and stable, thereby improving the uniform conduction and robustness of the ESD device array.

[0062] Please see Figures 3-8 It shows a schematic diagram of the device cross-sectional structure in each process step of the fabrication method of the GGNMOS structure provided in the embodiments of this application.

[0063] First, such as Figure 3 As shown, a P-type substrate 100 is provided. The P-type substrate 100 is a lightly doped P-type silicon wafer or a silicon-on-insulator substrate. The resistivity, impurity concentration, and other properties of the P-type substrate 100 meet the electrical requirements of the device. Further, P-type ion trap implantation is performed on the P-type substrate 100 to form a P-well 101. Further, an isolation component 115 is formed in the P-type substrate 100. The isolation component 115 surrounds a region, which is the active region of the subsequently formed device. Exemplarily, the isolation component 115 is formed using device isolation methods such as Localized Field Oxide (LOCOS) or Shallow Trench Isolation (STI).

[0064] Next, as Figure 4 As shown, N-type ions are lightly implanted into a P-type substrate 100 to form a first lightly doped drain region 102 and a second lightly doped drain region 103. For example, the ion concentration of both the first lightly doped drain region 102 and the second lightly doped drain region 103 can be 1E13 atoms / cm³. 2 ~1E14 atoms / cm 2 .

[0065] Next, as Figure 5 As shown, a first gate structure 110 and a second gate structure 111 are formed on the active region of the device. Both the first gate structure 110 and the second gate structure 111 are composed of a gate oxide layer 11a and a gate material layer 11b stacked from bottom to top. For example, the silicon wafer is cleaned to remove surface contaminants and oxide layers. A silicon oxide thin film is formed on the active region of the device as the gate oxide layer 11a using an oxidation furnace process or a chemical vapor deposition process. Then, a gate material layer 11b is deposited on the gate oxide layer 11a using silane and a low-pressure chemical vapor deposition device, and the deposited gate material layer 11b is subjected to phosphorus doping or silicide treatment. Then, a gate structure with a vertical cross-section is selectively etched using deep ultraviolet lithography and anisotropic plasma etching technology, thereby obtaining the first gate structure 110 and the second gate structure 111, both composed of a gate oxide layer 11a and a gate material layer 11b stacked from bottom to top. Furthermore, using a deposition and etching process such as silicon nitride or silicon oxide, sidewall structures 113 surrounding the first gate structure 110 and the second gate structure 111 are formed on the sides of the second gate structure 110 and the second gate structure 111. For example, the feature size of the second gate structure 111 is 100 nanometers to 1 micrometer.

[0066] Next, as Figure 6As shown, an N-type ion heavy doping implantation is performed on a P-type substrate 100 to form a source 105 in a first lightly doped drain region 102 and n spaced-apart first heavily doped regions 106 in a second lightly doped drain region 103. The second lightly doped drain regions 103 spaced between the first heavily doped regions 106 constitute an N+ / N- alternating drain structure 107, where n is an integer greater than or equal to 2. For example, the ion concentration of the first heavily doped region 106 can be 1E14 atoms / cm³. 2 ~1E16atoms / cm 2 .

[0067] Next, as Figure 7 As shown, a P-type substrate 100 is lightly doped with P-type ions to form m spaced third lightly doped drain regions 108 in the second lightly doped drain region 103. Each third lightly doped drain region 108 is located in the second lightly doped drain region 103 between two first heavily doped regions 106. The depth of the third lightly doped drain region 108 is less than the depth of the second lightly doped drain region 103, where m is an integer greater than or equal to 2 and m < n. For example, for CMOS processes, a 1.5V PLDD (P-type lightly doped drain) process can be used to form the third lightly doped drain region 108; for LDMOS processes, a 5V P-body (P-type body region) process can be used to form the third lightly doped drain region 108. When performing P-type light doping implantation on the P-type substrate 100, a certain ion implantation angle is required to extend the formed third lightly doped drain region 108 to the bottom of the second gate structure 111. For example, the process parameters for a 1.5V PLDD process are: ion implantation source B / BF2, implantation energy 5 keV to 200 keV, incident angle 0° to 30°, and ion concentration 1 E11 atoms / cm³. 2 ~1E14 atoms / cm 2 The process parameters for the 5V P-body process are as follows: ion implantation source B / BF2, implantation energy 10 keV–450 keV, incident angle 0°–30°, and ion concentration 1E11 atoms / cm³. 2 ~1E15atoms / cm 2 .

[0068] Next, as Figure 8As shown, a P-type substrate 100 is subjected to P-type ion heavy doping implantation to form m spaced second heavily doped regions 109 in the second lightly doped drain region 103. Each second heavily doped region 109 is located in a corresponding third lightly doped drain region 108. The width of the second heavily doped region 109 is smaller than the width of the third lightly doped drain region 108, and the depth of the second heavily doped region 109 is smaller than the depth of the third lightly doped drain region 108. m is an integer greater than or equal to 2, and m < n. For example, the process parameters for P-type ion heavy doping implantation are: ion implantation source B / BF2, implantation energy 15 keV ~ 500 keV, and ion concentration 1E14 atoms / cm³. 2 ~1E16atoms / cm 2 .

[0069] For example, to simplify the process, the step of lightly doping the P-type substrate 100 with P-type ions can be omitted before performing heavy doping implantation of P-type ions on the P-type substrate 100.

[0070] For example, since this application controls the ion implantation process window for forming the first heavily doped region 106, the third lightly doped drain region 108, and the second heavily doped region 109 by using the feature size of the second gate structure 111, in other embodiments of this application, the P-type substrate 100 can be lightly doped with P-type ions to form m spaced third lightly doped drain regions 108 in the active region of the device (this step can be omitted to simplify the process), then the P-type substrate 100 can be heavily doped with P-type ions to form m spaced second heavily doped regions 109 in the active region of the device, and then the P-type substrate 100 can be heavily doped with N-type ions to form the source 105 in the first lightly doped drain region 102 and the first heavily doped region 106 with n spaced first times in the second lightly doped drain region 103.

[0071] For example, the width and depth of the second heavily doped region 109 may be the same as or different from the width and depth of the first heavily doped region 106.

[0072] Next, a silicide barrier layer 112 is formed on the portion of the source 105 near the first gate structure 110 and on the first heavily doped region 106 between the first gate structure 110 and the second gate structure 111, resulting in the following: Figure 1 The diagram shows the cross-sectional structure of the device.

[0073] The silicide barrier layer 112 defines the RPO region as a metal-free silicide region to ensure a certain resistance to prevent current from concentrating through the center GGNMOS that conducts first, thus causing it to burn out.

[0074] For example, the material of the silicide barrier layer 112 is an oxide.

[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] In summary, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0077] Next, a silicide layer is formed that covers the top of the source 105, the first gate structure 110, and the second gate structure 111, as well as the top of the second heavily doped region 109 and the first heavily doped region 106, except for the first heavily doped region 106 in the drain 107 that is adjacent to the first gate structure 110.

[0078] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A GGNMOS structure, characterized in that, The GGNMOS structure includes: A P-type substrate, wherein a P-well and a first lightly doped drain region and a second lightly doped drain region are spaced apart in the P-well; The source is located in the first lightly doped drain region; The first heavily doped regions are arranged at intervals of n, and the first heavily doped regions are arranged at intervals in the second lightly doped drain regions; m third lightly doped drain regions are arranged at intervals, and each of the third lightly doped drain regions is disposed in a second lightly doped drain region between two first heavily doped regions; The second heavily doped regions are arranged at intervals of m, and each of the second heavily doped regions is disposed in the third lightly doped drain region; A first gate structure, the first gate structure covering the P-type substrate between the first lightly doped drain region and the second lightly doped drain region, and a portion of the surface of the first lightly doped drain region and the second lightly doped drain region; and... A second gate structure is located on a second lightly doped drain region in the interval between n first heavily doped regions; Where m is an integer greater than or equal to 1, n is an integer greater than or equal to 2, and m < n.

2. The GGNMOS structure according to claim 1, characterized in that, The spacing between the second heavily doped region and the first heavily doped region is controlled by changing the feature size of the second gate structure.

3. The GGNMOS structure according to claim 1 or 2, characterized in that, The feature size of the second gate structure is 100 nanometers to 1 micrometer.

4. The GGNMOS structure according to claim 1, characterized in that, The second lightly doped drain region in the interval between the first heavily doped region and the first heavily doped region constitutes a drain electrode with alternating heavy and light doping.

5. The GGNMOS structure according to claim 1, characterized in that, The doped ions in the first lightly doped drain region, the second lightly doped drain region, and the first heavily doped region are N-type.

6. The GGNMOS structure according to claim 1, characterized in that, The doped ions in the third lightly doped drain region and the second heavily doped region are P-type.

7. The GGNMOS structure according to claim 1, characterized in that, The GGNMOS structure further includes a silicide barrier layer that covers the portion of the source near the first gate structure and the first heavily doped region between the first gate structure and the second gate structure.

8. The GGNMOS structure according to claim 1, characterized in that, The second heavily doped region and the P-well are at the same potential.

9. A method for fabricating a GGNMOS structure, characterized in that, The manufacturing method includes: A P-type substrate is provided, and a P-well is formed in the P-type substrate; The P-type substrate is lightly doped with N-type ions to form a first lightly doped drain region and a second lightly doped drain region. Forming a first gate structure and a second gate structure; The P-type substrate is subjected to N-type ion heavy doping implantation to form a source in the first lightly doped drain region and n spaced first heavily doped regions in the second lightly doped drain region, wherein the second lightly doped drain regions in the interval between the first heavily doped regions constitute a drain with alternating heavy and light doping. The P-type substrate is lightly doped with P-type ions to form m spaced third lightly doped drain regions in the second lightly doped drain region. The P-type substrate is subjected to P-type ion heavy doping implantation to form m spaced-apart second heavily doped regions in the second lightly doped drain region, wherein each second heavily doped region is disposed in a corresponding third lightly doped drain region; and A silicide barrier layer is formed on the portion of the source near the first gate structure and on the first heavily doped region between the first gate structure and the second gate structure; Where m is an integer greater than or equal to 1, n is an integer greater than or equal to 2, and m < n.

10. The manufacturing method according to claim 9, characterized in that, Both the first gate structure and the second gate structure are composed of a gate oxide layer and a gate material layer stacked from bottom to top.

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