A normally-on GaN HEMT power device

Abstract

The present invention discloses a normally-on GaN HEMT power device, belonging to the field of semiconductor technology. The device comprises a third substrate, a second intermediate layer, a buffer layer, a GaN layer, and an AlGaN layer, connected sequentially from bottom to top. The AlGaN layer is provided with a source, a drain, and a gate, wherein the source and drain electrodes extend into the GaN layer. The GaN layer is provided with a cavity, the lower end of which extends into the buffer layer, and the upper end of which is located below the source and drain channels. P-type GaN is epitaxially grown on the AlGaN layer, and the gate is located on the p-type GaN. By forming a cavity in the GaN layer, the present invention reduces the thickness of the GaN layer below the channel, thereby reducing leakage paths and reducing leakage. It also increases the density of the two-dimensional electron gas at the AlGaN / GaN interface, improving device performance and achieving a normally-on device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a normally-on GaN HEMT power device. Background Art

[0002] Traditional GaN HEMT devices require growing AlGaN / GaN materials on a silicon substrate before fabricating the device. Two factors that affect GaN HEMT devices are tensile strain in the AlGaN layer and leakage in the GaN layer. The core operating principle of GaN HEMT devices is that the AlGaN layer exhibits tensile strain, which exhibits both spontaneous and piezoelectric polarization effects, while the GaN layer exhibits only spontaneous polarization. This disparity in polarization effects leads to the generation of an induced two-dimensional electron gas (2DEG) at the AlGaN / GaN interface. The concentration of the 2DEG determines the device's conductivity, so increasing the tensile strain in the AlGaN layer helps increase the 2DEG concentration and improve device performance. Furthermore, when growing AlGaN / GaN on a silicon substrate, due to lattice and thermal mismatch, the GaN layer experiences significant tensile stress after growth, leading to a large number of dislocations in the AlGaN / GaN layer. These dislocations increase leakage in the power device, severely impacting device performance. Summary of the Invention

[0003] The purpose of the present invention is to overcome the problems of insufficient induced two-dimensional electron gas concentration and leakage at the AlGaN / GaN interface of existing GaN HEMT devices, and to provide a normally-on GaN HEMT power device.

[0004] The object of the present invention is achieved through the following technical solutions:

[0005] In one embodiment, a normally-on GaN HEMT power device is provided, comprising a third substrate, a second intermediate layer, a buffer layer, a GaN layer, and an AlGaN layer connected sequentially from bottom to top; a source, a drain, and a gate are provided on the AlGaN layer, wherein the source and the drain both extend and connect to the GaN layer; a cavity is provided in the GaN layer, wherein the lower end of the cavity extends into the buffer layer, and the upper end of the cavity is located below the channel of the source and the drain.

[0006] As a preferred option, in a normally-on GaN HEMT power device, the thickness of the GaN layer above the cavity is 0.2um-1um.

[0007] As a preferred option, in a normally-on GaN HEMT power device, the third substrate is a silicon substrate or an SOI wafer.

[0008] As a preferred option, in a normally-on GaN HEMT power device, p-type GaN is epitaxially grown on the AlGaN layer, and the gate is located on the p-type GaN.

[0009] As a preferred option, in a normally-on GaN HEMT power device, an enhancement-mode silicon MOSFET device is connected to the AlGaN layer.

[0010] In another embodiment, a method for preparing a normally-on GaN HEMT power device is provided, the method comprising the following steps:

[0011] S1, sequentially growing a buffer layer, a GaN layer, and an AlGaN layer on a first substrate;

[0012] S2. Spin-coating or depositing a first intermediate layer on the AlGaN layer, and bonding a second substrate on the first intermediate layer;

[0013] S3, removing the first substrate by grinding and selective etching to expose the buffer layer, spin-coating photoresist on the buffer layer and opening a window;

[0014] S4, etching the buffer layer and the GaN layer in sequence to form an etched groove, wherein the etching is stopped after the etched groove extends into the interior of the GaN layer and the photoresist is removed;

[0015] S5, bonding a third substrate on which a second intermediate layer is spin-coated or deposited on the buffer layer, and allowing the second intermediate layer to cover the etched groove to form a cavity;

[0016] S6. Remove the first intermediate layer and the second substrate, and manufacture a source electrode, a drain electrode, and a gate electrode on the AlGaN layer to obtain a GaN HEMT power device.

[0017] As a preferred option, in a method for preparing a normally-on GaN HEMT power device, the first substrate, the second substrate, and the third substrate are all silicon substrates.

[0018] As a preferred option, in a method for preparing a normally-on GaN HEMT power device, in step S6, the channels of the source and drain are arranged at the upper end of the cavity.

[0019] As a preferred option, a method for preparing a normally-on GaN HEMT power device further includes:

[0020] P-type GaN is epitaxially grown on the AlGaN layer, and a gate is formed on the p-type GaN.

[0021] As a preferred option, a method for preparing a normally-on GaN HEMT power device further includes:

[0022] An enhancement-mode silicon MOSFET device is connected to the AlGaN layer.

[0023] It should be further explained that the technical features corresponding to the above options can be combined or replaced with each other to form a new technical solution if there is no conflict.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention provides a cavity in the GaN layer, extends the lower end of the cavity into the buffer layer, and positions the upper end of the cavity below the source and drain channels. The formation of the cavity leads to stress redistribution, and the lattice in the area above the corresponding cavity is further stretched, significantly increasing the piezoelectric polarization of the AlGaN layer and increasing the two-dimensional electron gas density at the AlGaN / GaN interface. At the same time, the cavity is formed below the source and drain channels, significantly reducing the thickness of the GaN layer and the leakage path, thereby reducing leakage and greatly improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a structural diagram of a normally-on GaN HEMT power device according to the present invention;

[0027] Figure 2 This is a schematic diagram of the structure of a p-type GaN epitaxially grown on a GaN HEMT power device according to the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of an epitaxial enhancement-mode silicon MOSFET device on a GaN HEMT power device according to the present invention;

[0029] Figure 4 The present invention is based on Figure 3 Schematic diagram of the structure of epitaxial AlGaN / GaN layer on SOI substrate;

[0030] Figure 5 The present invention is based on Figure 3 Schematic diagram of another normally-on GaN HEMT power device;

[0031] Figure 6 Schematic diagram of sequentially growing a buffer layer 3, a GaN layer 4, and an AlGaN layer 5 on a first substrate 8 according to the present invention;

[0032] Figure 7 Schematic diagram of spin coating or depositing a first intermediate layer 9 on the AlGaN layer 5 and bonding a second substrate 10 on the first intermediate layer 9 according to the present invention;

[0033] Figure 8Schematic diagram of sequentially etching the buffer layer 3 and the GaN layer 4 to form etching grooves according to the present invention;

[0034] Figure 9 It is a schematic diagram showing the formation of the cavity 6 according to the present invention.

[0035] Explanation of the numbers in the figure: 1. third substrate; 2. second intermediate layer; 3. buffer layer; 4. GaN layer; 5. AlGaN layer; 6. cavity; 7. p-type GaN; 8. first substrate; 9. first intermediate layer; 10. second substrate. DETAILED DESCRIPTION

[0036] The technical solution of the present invention is described clearly and completely below with reference to the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "up," "down," "left," "right," "vertical," "horizontal," "inside," and "outside" are based on the directions or positional relationships described in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] The present invention mainly increases the piezoelectric polarization of the AlGaN layer by setting a cavity in the GaN layer, thereby increasing the two-dimensional electron gas density at the AlGaN / GaN interface and reducing leakage channels, thereby achieving the purpose of improving device performance.

[0040] Example 1

[0041] In an exemplary embodiment, a GaN HEMT power device is provided, such as Figure 1As shown, the device includes, from bottom to top, a third substrate 1, a second intermediate layer 2, a buffer layer 3, a GaN layer 4, and an AlGaN layer 5. A source, a drain, and a gate are provided on the AlGaN layer 5, wherein the source and drain extend into the GaN layer 4. A cavity 6 is provided in the GaN layer 4, the lower end of which extends into the buffer layer 3, and the upper end of which is located below the source and drain channels. The third substrate 1 is a silicon substrate or an SOI wafer.

[0042] Specifically, during the epitaxial growth process, because the thermal expansion coefficient of the GaN layer 4 is greater than that of the silicon substrate, it is in a lattice expansion state when growing at high temperature. When cooled to room temperature, the silicon substrate and the GaN layer 4 lattice shrink simultaneously. However, due to the influence of the silicon substrate, the GaN layer 4 cannot shrink to the normal lattice at room temperature, but is larger than the normal lattice. Therefore, both the GaN layer 4 and the AlGaN layer 5 are subjected to tensile strain. The tensile strain of the GaN layer 4 is only due to the incomplete contraction due to thermal expansion. The direct reason for the tensile strain of the AlGaN layer 5 is that the AlGaN is very thin. It grows in a co-lattice with the GaN layer 4, but the lattice constant of AlGaN is smaller than that of GaN. When the co-lattice grows, the AlGaN lattice is the same as that of GaN, so it exhibits a large tensile strain. Therefore, the piezoelectric polarization phenomenon of AlGaN is stronger. Because the GaN layer 4 is very thick, although it has a small tensile strain, the piezoelectric polarization effect is not obvious and can be ignored.

[0043] Furthermore, the formation of cavity 6 leads to stress redistribution, and the lattice in the area on both sides of cavity 6 further shrinks, approaching the normal lattice state. The lattice in the area above the corresponding cavity 6 is further stretched, showing stronger tensile strain, which significantly increases the piezoelectric polarization of the corresponding AlGaN layer 5. Although the GaN layer 4 also has a piezoelectric polarization enhancement effect, due to its large film thickness, the piezoelectric polarization enhancement effect is not obvious. The overall effect is that the piezoelectric polarization enhancement of the AlGaN layer 5 leads to an increase in the two-dimensional electron gas density at the AlGaN / GaN interface, thereby improving device performance.

[0044] Furthermore, the cavity 6 in the figure is mainly located below the source and drain channels, which significantly reduces the thickness of the GaN layer 4, thereby reducing the leakage channel and facilitating the reduction of leakage.

[0045] Furthermore, the cavity 6 cannot completely etch away the GaN layer 4, otherwise the two-dimensional electron gas will not exist. The thickness of the GaN layer 4 above the cavity 6 is preferably 0.2 um-1 um.

[0046] Example 2

[0047] Based on Example 1, a normally-on GaN HEMT power device is provided, such as Figure 2As shown, p-type GaN 7 is epitaxially grown on the AlGaN layer 5 , and the gate is located on the p-type GaN 7 .

[0048] Specifically, the device obtained in Example 1 is a normally-on device (depletion mode DMODE). Most applications require a normally-off device (enhancement mode EMODE). This requires epitaxially growing a layer of p-type GaN 7 on top of the AlGaN layer 5, and then fabricating a gate on top of the p-type GaN. This device structure depletes electrons in the channel region below the gate, putting the device in a normally-off state. When fabricating this device, the pGaN layer can be grown epitaxially in the first step, or directly before fabricating the device structure in Example 1.

[0049] Example 3

[0050] Based on Example 1, a GaN HEMT power device is provided, such as Figure 3 As shown, an enhancement mode silicon MOSFET device is connected to the AlGaN layer 5 .

[0051] Specifically, the manufacturing of p-type GaN in Example 2 is very difficult because the activation efficiency of the p-type dopant element (generally magnesium) in GaN material is very low, P-type doping of GaN material is very difficult, and the p-type GaN quality is less than ideal. On the other hand, the threshold voltage of the EMODE device based on this structure is relatively low, and the design of a driving circuit support is required during use. Therefore, an alternative solution is provided in this embodiment. By connecting an enhancement-mode silicon MOSFET in series with a depletion-mode GaN HEMT, the source and gate of the silicon MOSFET are used as the source and gate of the entire device, and the drain of the GaN HEMT serves as the drain of the entire device, which is the so-called CASCODE mode.

[0052] Furthermore, the two devices are designed on the same substrate, and the silicon layer is isolated from the GaN layer below by an intermediate layer, and they do not affect each other. The two devices can be interconnected through the metal layer during the process, or they can be interconnected through packaging and bonding after the entire device is completed to realize the CASCODE structure. The reason why SOI material is used in this step is that SOI material can very well define the thickness of the silicon layer, making the process simple to implement. In theory, silicon can also be used directly instead of SOI, and then a certain thickness of silicon can be obtained through grinding and polishing processes, so that this structure can also be obtained, but it is more difficult to achieve.

[0053] Example 4

[0054] Based on Example 1, a GaN HEMT power device is provided, such as Figure 4As shown in the figure, the difference between this device and the previous device is that an SOI wafer is bonded downward on one side, a silicon layer is added on the middle layer, and the SOI with the top silicon is used as the initial substrate. Because the silicon layer is thinner, the dislocation of the GaN layer caused by lattice mismatch can be reduced, further improving the performance of the device.

[0055] Furthermore, in another example, Figure 5 As shown, another normally-on GaN HEMT power device is provided, which is bonded to the SOI substrate during spin coating or deposition of the intermediate layer.

[0056] Example 5

[0057] Based on the same inventive concept as Example 1, Figure 6-Figure 9 , provides a method for preparing a GaN HEMT power device, the method comprising the following steps:

[0058] S1, such as Figure 6 As shown, a buffer layer 3, a GaN layer 4 and an AlGaN layer 5 are sequentially epitaxially grown on a first substrate 8;

[0059] S2, such as Figure 7 As shown, a first intermediate layer 9 is spin-coated or deposited on the AlGaN layer 5, and a second substrate 10 is bonded on the first intermediate layer 9; wherein, when the first intermediate layer 9 is deposited, the deposited material can be SiO2 or other materials, and chemical mechanical polishing is required if necessary;

[0060] S3, grinding and selectively etching to remove the first substrate 8 to expose the buffer layer 3, spin-coating photoresist on the buffer layer 3 and opening a window;

[0061] S4, such as Figure 8 As shown, the buffer layer 3 and the GaN layer 4 are sequentially etched to form an etched groove, wherein the etching is stopped after the etched groove extends to the interior of the GaN layer 4 and the photoresist is removed;

[0062] S5, such as Figure 9 As shown, a third substrate 1 having a second intermediate layer 2 spin-coated or deposited thereon is bonded on the buffer layer 3, and the second intermediate layer 2 covers the etched groove to form a cavity 6;

[0063] S6, remove the first intermediate layer 9 and the second substrate 10, and manufacture the source, drain and gate on the AlGaN layer 5 to obtain Figure 1 The GaN HEMT power device shown.

[0064] Furthermore, the first substrate 8 , the second substrate 10 and the third substrate 1 are all silicon substrates. In the step S6 , the channels of the source and the drain are arranged at the upper end of the cavity 6 .

[0065] Furthermore, the method further comprises:

[0066] A p-type GaN 7 is epitaxially grown on the AlGaN layer 5 , and a gate is formed on the p-type GaN 7 .

[0067] Furthermore, the method further comprises:

[0068] An enhancement mode silicon MOSFET device is connected to the AlGaN layer 5 .

[0069] The above specific implementation methods are detailed descriptions of the present invention. It cannot be considered that the specific implementation methods of the present invention are limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, they can make several simple deductions and substitutions without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A normally-on GaN HEMT power device, characterized in that: The present invention comprises a third substrate (1), a second intermediate layer (2), a buffer layer (3), a GaN layer (4) and an AlGaN layer (5) connected in sequence from bottom to top; a source electrode, a drain electrode and a gate electrode are provided on the AlGaN layer (5), wherein the source electrode and the drain electrode are both extended and connected to the GaN layer (4); a cavity (6) is provided in the GaN layer (4), the lower end of the cavity (6) extends into the buffer layer (3), and the upper end of the cavity (6) is located below the channel of the source electrode and the drain electrode; The method for preparing the GaN HEMT power device comprises the following steps: S1, sequentially epitaxially growing a buffer layer (3), a GaN layer (4), and an AlGaN layer (5) on a first substrate (8); S2, spin coating or depositing a first intermediate layer (9) on the AlGaN layer (5), and bonding a second substrate (10) on the first intermediate layer (9); S3, grinding and selectively etching to remove the first substrate (8) to expose the buffer layer (3), spin-coating photoresist on the buffer layer (3) and opening a window; S4, etching the buffer layer (3) and the GaN layer (4) in sequence to form an etching groove, wherein the etching is stopped after the etching groove extends into the interior of the GaN layer (4) and the photoresist is removed; S5, bonding a third substrate (1) on which a second intermediate layer (2) is spin-coated or deposited on the buffer layer (3), and allowing the second intermediate layer (2) to cover the etched groove to form a cavity (6); S6, removing the first intermediate layer (9) and the second substrate (10), and manufacturing a source electrode, a drain electrode, and a gate electrode on the AlGaN layer (5) to obtain a GaN HEMT power device; A p-type GaN (7) is epitaxially grown on the AlGaN layer (5), and the gate is located on the p-type GaN (7); the GaN layer (4) above the cavity (6) has a thickness of 0.2 um to 1 um.

2. The normally-on GaN HEMT power device according to claim 1, characterized in that: The third substrate (1) is a silicon substrate or an SOI wafer.

3. The normally-on GaN HEMT power device according to claim 1, wherein: An enhancement-mode silicon MOSFET device is connected to the AlGaN layer (5).

4. The normally-on GaN HEMT power device according to claim 1, wherein: The first substrate (8), the second substrate (10) and the third substrate (1) are all silicon substrates.

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