Vertical Ga2O3 transistor with SiO2 barrier layer and its fabrication method

Abstract

This invention discloses a vertical Ga2O3 transistor with a SiO2 barrier layer and its fabrication method, mainly addressing the problem of poor device performance and reliability caused by the lack of a source-drain leakage current blocking structure in existing vertical gallium oxide field-effect transistors. From bottom to top, it includes a drain electrode, a gallium oxide substrate, a gallium oxide epitaxial layer, a gate oxide layer, and a gate electrode. A SiO2 current blocking layer is provided on the outer periphery of the epitaxial layer, with a vertically heavily doped conductive channel at its center. Above this channel is an n-type conductive layer grown by ALD, and above this n-type conductive layer is the source electrode. Due to the presence of a vertically heavily doped conductive channel, the on-resistance of the device is reduced compared to existing structures. Furthermore, the SiO2 barrier layer on the outer periphery of the epitaxial layer effectively reduces source-drain leakage current compared to existing structures, while simultaneously increasing the breakdown voltage, making it suitable for the fabrication of high-power integrated circuits.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a vertical structure Ga2O3 field-effect transistor, which can be used to fabricate high-voltage circuit transformer chips, high-speed railway power transmission systems, and civilian electric vehicle charging modules, etc. Technical Background

[0002] With the development of fourth-generation ultra-wide bandgap semiconductors, gallium oxide (GaO) has gradually become a focus of the next generation of semiconductor materials. Currently, five crystal forms of GaO can be prepared: α, β, γ, δ, and ε. Since the other metastable phases transform into β-Ga₂O₃ during high-temperature processing, monoclinic β-Ga₂O₃ exhibits the best thermal stability, and most current research focuses on it. β-Ga₂O₃ possesses an ultra-wide bandgap of 4.85 eV, resulting in a low ionization rate and thus a high breakdown field strength, theoretically exceeding 8 MV / cm, which is about 20 times that of first-generation semiconductor Si and one to two times that of third-generation semiconductors SiC and GaN. Furthermore, due to its high electron mobility, dielectric constant, and critical electric field strength, β-Ga₂O₃'s Baliga quality is three times that of 4H-SiC and 1.5 times that of GaN. Furthermore, β-Ga₂O₃ materials have a very low theoretical on-resistance. Therefore, for unipolar devices under the same breakdown voltage conditions, their conduction losses are at least an order of magnitude lower than those of SiC and GaN devices, which is beneficial for improving the efficiency of power devices. Thus, gallium oxide materials have enormous potential and promising prospects in the research and fabrication of power devices.

[0003] Gallium oxide (GaO) field-effect transistors (FETs) are mainly classified into two types: horizontal and vertical structures. Due to more mature manufacturing processes and structures, horizontal structures are still the dominant type of GaO FET in currently published articles. For horizontal structure FETs, to obtain a larger saturation current and a higher breakdown voltage, the channel size must be increased, thus sacrificing chip area. Furthermore, increasing the area introduces new reliability issues due to the increased total number of bulk material defects.

[0004] To fully leverage the advantages of gallium oxide materials in high voltage and high power resistance, vertically structured gallium oxide field-effect transistors are a better choice. For vertically structured devices, the reverse bias electric field is distributed throughout the entire bulk material. This not only increases the electric field bearing area but also avoids reliability issues caused by surface breakdown and achieves higher breakdown voltage. Furthermore, due to its structural characteristics, it is easy to obtain a large conduction current, and without sacrificing much chip area, a higher breakdown voltage can be achieved by increasing the thickness of the drift region.

[0005] However, due to the flat valence band of gallium oxide materials and the influence of excessive ionization energy, it is difficult to achieve P-type doping in the fabrication process of gallium oxide materials and devices, and it is impossible to use pn junctions to effectively block leakage between the source and drain as in traditional vertical structures.

[0006] Currently, there are two structures for vertical gallium oxide field-effect transistors:

[0007] The first type is the non-planar multi-fin structure used in early work, such as... Figure 1 As shown, the structure, from bottom to top, includes a drain electrode, a gallium oxide substrate, a gallium oxide drift layer, a fin channel, an aluminum oxide gate oxide layer, a silicon dioxide isolation layer, a gate electrode, and a source electrode. This structure achieves electrical isolation between the source and drain through sidewall modulation, successfully realizing the basic function of a vertical gallium oxide field-effect transistor. However, the corners of the trench gate oxide layer in the fin structure are subjected to strong field stress, reducing the device's reliability. The breakdown voltage is only 1000 V, and the complex fabrication and high precision requirements of the fin structure make device manufacturing extremely difficult.

[0008] The second type is a gallium oxide field-effect transistor with a full ion-implanted current-blocking layer structure, such as... Figure 2 As shown, the structure, from bottom to top, includes a drain electrode, a tin-doped gallium oxide substrate, a silicon-doped gallium oxide drift layer, a magnesium ion implantation current blocking layer, a silicon ion-doped gallium oxide channel, a source electrode, an aluminum oxide gate oxide layer, and a gate electrode. This structure reduces the manufacturing difficulty of vertical gallium oxide field-effect transistors by introducing a planar gate structure and avoids the problem of strong field stress at the device corners. However, since the fabrication process of this structure requires high-temperature annealing to activate the implanted ions, the high temperature will cause the introduced electron trap center ions to diffuse, resulting in a non-ideal leakage channel between the source and drain, thus generating a large leakage current. Its breakdown voltage cannot exceed 300 V, and the device performance is very unstable. Summary of the Invention

[0009] The purpose of this invention is to address the shortcomings of the prior art by proposing a vertical Ga2O3 transistor with a SiO2 barrier layer and its fabrication method, so as to improve the device breakdown voltage, avoid leakage current between the source and drain due to thermal diffusion, increase the drain output current of the transistor, and solve the problem of difficult growth process in highly doped ohmic regions.

[0010] To achieve the above objectives, the technical solution of the present invention is as follows:

[0011] 1. A vertical Ga2O3 transistor with a SiO2 barrier layer, comprising a gallium oxide substrate, a gallium oxide epitaxial layer, and a gate oxide layer, wherein a gate electrode is disposed above the gate oxide layer, and a drain electrode is disposed on the lower surface of the gallium oxide substrate, characterized in that:

[0012] The epitaxial layer has a SiO2 current blocking layer on its inner periphery to achieve effective source-drain electrical isolation, a vertically heavily doped conductive channel in its center to reduce the on-resistance of the device, and an n-type conductive layer on top of it to achieve the regrowth of gallium oxide material.

[0013] The source electrode is located above the n-type conductive layer.

[0014] Furthermore, the gallium oxide substrate layer has a thickness of 500um-700um and a concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 N-type highly doped β-Ga2O3 materials.

[0015] Furthermore, the gallium oxide epitaxial layer has a thickness of 3µm-10µm and a concentration of 1.5×10⁻⁶. 16 -1×10 17 cm -3 N-type low-doped β-Ga2O3 materials.

[0016] Furthermore, the transistor is characterized in that the SiO2 current blocking layer has a thickness of 500nm-1000nm.

[0017] Furthermore, the transistor is characterized in that: the n-type conductive layer has a thickness of 5nm-50nm and a concentration of 1×10⁻⁶. 17 -5×10 19 cm -3 N-type highly doped GaN, SiC, or In2O3 wide-bandgap or ultra-wide-bandgap n-type conductive materials.

[0018] Furthermore, the transistor is characterized in that: the vertically heavily doped conductive channel has a thickness of 1µm-10µm, a width of 2µm-20µm, and a concentration of 1×10⁻⁶. 17 -5×10 19 cm -3 N-type highly doped β-Ga2O3 material.

[0019] 2. A method for fabricating a vertical Ga2O3 transistor with a SiO2 barrier layer, characterized by comprising the following:

[0020] step:

[0021] 1) Clean the epitaxial wafer by immersing the homoepitaxial gallium oxide wafer in acetone solution, anhydrous ethanol solution and deionized water in sequence for ultrasonic cleaning for 5 min-10 min each, and then drying it with nitrogen gas.

[0022] 2) Photolithography is performed on the cleaned epitaxial wafer to form the area to be etched, and then it is placed in a reactive ion etching (RIE) system to etch away gallium oxide on the area to be etched on the epitaxial wafer to form a trench structure.

[0023] 3) Place the etched gallium oxide epitaxial wafer into the reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system (ICP-CVD), set the reaction chamber temperature to 80℃-90℃, deposit SiO2 with a thickness of 500nm-1000nm on the surface of the epitaxial wafer, and then place the deposited wafer into the stripping solution to form a SiO2 barrier layer through stripping.

[0024] 4) An n-type conductive material with a thickness of 10nm-20nm is deposited on the surface of a gallium oxide epitaxial wafer using atomic layer deposition (ALD) technology;

[0025] 5) Photolithography is performed on the deposited epitaxial wafer to form the area to be etched. Then, it is placed in a reactive ion etching (RIE) system to etch away the n-type conductive material on the area to be etched on the epitaxial wafer, forming an ohmic contact area.

[0026] 6) Photolithography is performed on the etched epitaxial wafer to form the region to be implanted with ions, and then n-type conductive ions are implanted into the region by ion implantation technology;

[0027] 7) Using atomic layer deposition (ALD) technology, Al2O3 with a thickness of 20nm-50nm is deposited on the surface of gallium oxide epitaxial wafers after ion implantation;

[0028] 8) Photolithographically print source electrode vias on the Al2O3 surface, and use a reactive ion etching (RIE) system to etch away the Al2O3 in the electrode via area;

[0029] 9) The etched epitaxial wafer is photolithographically etched again to form the source electrode region. Ti / Au is first deposited in the source electrode region by electron beam evaporation E-Beam system, and the source electrode is formed by lift-off. Then Ti / Au is deposited on the substrate surface to form the drain electrode, and annealed in N2 environment to form ohmic contact.

[0030] 10) Photolithography is performed on the gallium oxide epitaxial wafer after the ohmic contact is formed to form the gate region on the Al2O3 surface. Ni / Au is then deposited in the gate region by electron beam evaporation E-Beam system. The gate electrode is formed by lift-off to complete the device fabrication.

[0031] Compared with the prior art, the present invention has the following advantages:

[0032] 1. The present invention provides a heavily doped vertical conductive channel structure at the center of the epitaxial layer, which not only ensures that the withstand voltage capability of the device is not significantly affected, but also improves the output current of the device.

[0033] 2. The present invention achieves electrical isolation between the source and drain regions by providing a high-quality SiO2 current blocking layer structure on the upper part of the epitaxial layer. At the same time, due to the high dielectric constant of SiO2, the breakdown voltage of the vertical structure gallium oxide field-effect transistor device will be significantly improved.

[0034] 3. The present invention has a high-quality SiO2 current blocking layer structure on the upper part of the epitaxial layer. Compared with the existing technology of implanting Mg ions or N ions into the ion implantation region to form a current blocking layer between the source and drain, it avoids the problem of large leakage current caused by thermal diffusion of Mg ions or N ions in subsequent high-temperature processes.

[0035] 4. The present invention uses an atomic layer deposition (ALD) process to deposit n-type conductive material to form ohmic contacts, without using an ion implantation process to generate ohmic contacts. This reduces the damage to the crystal lattice caused by ion implantation, thereby reducing the semiconductor defect density, improving the crystal lattice integrity, and thus improving the device's withstand voltage capability.

[0036] 5. The present invention avoids the problem that the process of growing gallium oxide on the SiO2 barrier layer is impossible because it deposits an n-type conductive material on the deposited SiO2 current barrier layer through atomic layer deposition (ALD) to form a highly doped ohmic region. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of an existing multi-fin structure gallium oxide field-effect transistor.

[0038] Figure 2 This is a schematic diagram of a gallium oxide field-effect transistor with an existing all-ion implanted current blocking layer structure.

[0039] Figure 3 This is a schematic diagram of the vertical Ga2O3 transistor structure with a SiO2 barrier layer according to the present invention.

[0040] Figure 4 This is a schematic diagram illustrating the process of fabricating a vertical Ga2O3 transistor with a SiO2 barrier layer according to the present invention. Detailed Implementation

[0041] The following describes in further detail the vertical structure Ga2O3 transistor with SiO2 barrier layer and its fabrication process of the present invention with reference to the accompanying drawings.

[0042] Reference Figure 3 The vertical Ga2O3 transistor with a SiO2 barrier layer of the present invention includes: a drain electrode D, a source electrode S, a substrate layer 1, a drift layer 2, a gate oxide layer 3, a vertically heavily doped channel 5, a SiO2 layer 4, an n-type conductive material layer 6, and a gate-source electrode G, wherein:

[0043] The substrate layer 1 has a thickness of 500 μm-700 μm and a concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 N-type highly doped β-Ga2O3 materials;

[0044] The drift layer 2 has a thickness of 3 μm-10 μm and a concentration of 1.5 × 10⁻⁶. 16 -1×10 17 cm -3 The N-type low-doped β-Ga2O3 material is located on the substrate layer 1;

[0045] The gate oxide layer 3 is made of Al2O3 material with a thickness of 20 nm-50 nm and is located above the drift layer 2;

[0046] The SiO2 layer 4 has a thickness of 500 nm-1000 nm and is located inside the etched trench;

[0047] The vertically heavily doped channel 5 extends from the upper surface of the β-Ga2O3 drift layer 2 into the interior of the drift region, with a thickness of 1µm-10µm, a width of 2µm-20µm, and a concentration of 1×10⁻⁶. 17 -5×10 19 cm -3 ;

[0048] The n-type conductive material layer 6 is located above the SiO2 layer 4, and has a thickness of 5nm-50nm and a concentration of 1×10⁻⁶. 17 -5×10 19 cm -3 N-type highly doped GaN, SiC or In2O3 materials;

[0049] The gate electrode G is located on the upper part of the gate oxide layer 3;

[0050] The source electrode S is located on the upper part of the N-type conductive material layer 6;

[0051] The drain electrode D is located at the bottom of the N-type highly doped β-Ga2O3 substrate layer 1.

[0052] Reference Figure 4 The present invention provides three embodiments of the method for fabricating a vertical Ga2O3 transistor with a SiO2 barrier layer:

[0053] Example 1: Fabrication of an N-type β-Ga2O3 substrate with a thickness of 500 μm and a doping density of 1 × 10⁻⁶. 18 cm -3 The N-type β-Ga₂O₃ drift layer has a thickness of 3 μm and a doping density of 1.5 × 10⁻⁶. 16 cm -3The SiO2 thickness is 500 nm, the vertical heavily doped channel width is 2 μm, the thickness is 1 μm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 The n-type conductive material is In₂O₃, with a thickness of 5 nm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 A vertical Ga2O3 transistor with a gate oxide layer thickness of 20 nm.

[0054] Step 1: Clean the β-Ga2O3 epitaxial wafer, such as... Figure 4 (a) in the middle.

[0055] To clean the epitaxial wafer, the homogeneous gallium oxide wafer is sequentially immersed in acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes each, and then dried with nitrogen gas.

[0056] Step 2: Trench structure etching, as shown in Figure 4(b).

[0057] Photolithography is performed on the cleaned epitaxial wafer to form the area to be etched. Then, it is placed in a reactive ion etching (RIE) system to perform etching to a depth of 510 nm to remove gallium oxide from the area to be etched on the epitaxial wafer and form a trench structure.

[0058] The process conditions for a reactive ion etching (RIE) system are:

[0059] Reaction chamber pressure: 1500 mtorr

[0060] Reaction chamber gases: SF6, CHF3, He

[0061] Gas flow rate ratio in reaction chamber: SF6:CHF3:He = 5.5 sccm:32 sccm:150 sccm

[0062] RF power source: 150W.

[0063] Step 3: Deposit SiO2, as shown in Figure 4(c).

[0064] The etched gallium oxide epitaxial wafer is placed in the reaction chamber of an inductively coupled plasma enhanced chemical vapor deposition system (ICP-CVD) to deposit a 500 nm thick SiO2 layer on the surface of the epitaxial wafer. The deposited wafer is then placed in a stripping solution to form a SiO2 barrier layer through stripping.

[0065] The ICP-CVD process conditions for a chemical vapor deposition system are:

[0066] Reaction chamber temperature: 80℃

[0067] Reaction chamber pressure: 500 Pa

[0068] Gas flow rate in reaction chamber: 300 sccm

[0069] Step 4: Fabricate an n-type conductive material layer, as shown in Figure 4(d).

[0070] Atomic layer deposition (ALD) is used to deposit a 5 nm thick n-type conductive material In2O3 on the surface of a gallium oxide epitaxial wafer. Photolithography is then performed on the epitaxial wafer after deposition to form the area to be etched. The area is then placed in a reactive ion etching (RIE) system to etch away the n-type conductive material on the area to be etched, forming an ohmic contact area.

[0071] The atomic layer deposition (ALD) process conditions are:

[0072] Reaction chamber temperature: 200℃

[0073] Reaction chamber pressure: 800 Pa

[0074] Reaction chamber gas: High-purity nitrogen

[0075] Gas flow rate in reaction chamber: 300 sccm

[0076] The process conditions for a reactive ion etching (RIE) system are:

[0077] Reaction chamber pressure: 1500 mtorr

[0078] Reaction chamber gases: SF6, CHF3, He

[0079] Gas flow rate ratio in reaction chamber: SF6:CHF3:He = 5.5 sccm:32 sccm:150 sccm

[0080] RF power source: 150W.

[0081] Step 5: Ion implantation, such as Figure 4 (e) in the middle.

[0082] Photolithography is performed on the etched epitaxial wafer surface to form vertical conductive channel ion implantation regions. Then, Si ion implantation is performed twice in these regions, with an implantation dose of 1×10⁻⁶. 14 cm -2 The injected energy is 10 keV. A doping concentration of 1×10⁻⁶ is formed. 17 cm -3 A highly doped region with a depth of 1µm;

[0083] After ion implantation, the epitaxial wafer is placed in an N2 environment, and the temperature inside the annealing furnace is set to 900℃ for 30 minutes to activate the implanted ions.

[0084] Step 6: Growth gate medium, such as Figure 4 (f) in the middle.

[0085] A gate dielectric with a thickness of 20 nm of Al2O3 was deposited on the surface of a gallium oxide epitaxial wafer using atomic layer deposition (ALD) technology.

[0086] The atomic layer deposition (ALD) process conditions are:

[0087] Reaction chamber temperature: 200℃

[0088] Reaction chamber pressure: 800 Pa

[0089] Reaction chamber gas: High-purity nitrogen

[0090] Gas flow rate in reaction chamber: 300 sccm

[0091] Step 7: Photolithography forms the source metal region to be evaporated, such as... Figure 4 (g)-(h).

[0092] Photolithographically etch source electrode vias onto the Al2O3 surface, such as... Figure 4 (g) in

[0093] The Al2O3 in the electrode via region is removed by etching using a reactive ion etching (RIE) system, forming the source metal region to be evaporated, such as... Figure 4 (h)

[0094] The process conditions for a reactive ion etching (RIE) system are:

[0095] Reaction chamber pressure: 10-30 mTorr

[0096] Reaction chamber gases: BCl3, Ar

[0097] Gas flow rate ratio in reaction chamber: BCl3:Ar = 20 sccm: 10 sccm

[0098] Etching power: 200W.

[0099] Step 8: Fabricate source and drain ohmic electrodes, such as Figure 4 (i) in the middle.

[0100] 8.1) The etched epitaxial wafer is photolithographically etched again to form the source electrode region. Ti / Au with a thickness of 60nm / 120nm is deposited in the source electrode region using an electron beam evaporation E-Beam system.

[0101] 8.2) After electron beam evaporation, the wafer is placed in a stripping solution and the source electrode is formed by stripping.

[0102] 8.3) A Ti / Au layer with a thickness of 60nm / 120nm is deposited on the substrate surface to form a drain electrode. Annealing is then performed in an N2 environment at a furnace temperature of 475℃ for one minute to form an ohmic contact. Figure 4 (i) in the middle;

[0103] 8.4) Photolithography is performed on the Al2O3 surface to form the gate metal region to be evaporated.

[0104] Step 9: Fabricate the gate electrode, such as Figure 4 (j) in the middle.

[0105] Ni / Au with a thickness of 50nm / 100nm is deposited in the gate metal region to be evaporated using an electron beam evaporation E-Beam system. After electron beam evaporation, the wafer is placed in a stripping solution and the gate electrode is formed by stripping, thus completing the device fabrication.

[0106] Example 2: Fabrication of an N-type β-Ga2O3 substrate with a thickness of 600 μm and a doping density of 2.5 × 10⁻⁶ μm. 18 cm -3 The N-type β-Ga2O3 drift layer has a thickness of 7 μm and a doping density of 5 × 10⁻⁶. 16 cm -3 The SiO2 thickness is 750 nm, the vertical heavily doped channel width is 10 μm, the thickness is 5 μm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 The n-type conductive material is In₂O₃, with a thickness of 25 nm and a doping density of 5 × 10⁻⁶. 18 cm -3 A vertical Ga2O3 field-effect transistor with a SiO2 barrier layer and a vertically heavily doped channel.

[0107] Step A: Clean the β-Ga2O3 epitaxial wafer.

[0108] The specific implementation of this step is the same as step 1 in Example 1.

[0109] Step B: Trench structure etching.

[0110] Photolithography is performed on the cleaned epitaxial wafer to form the area to be etched. The wafer is then placed in a reactive ion etching (RIE) system. The reaction chamber pressure is set to 1500 mtorr, the reaction chamber gas is SF6, CHF3, and He, and the gas flow rate ratio is SF6:CHF3:He = 5.5 sccm:32 sccm:150 sccm. The RF source power is 175W. Etching is performed to a depth of 810 nm to remove gallium oxide from the area to be etched on the epitaxial wafer, forming a trench structure.

[0111] Step C: Deposit SiO2.

[0112] The etched gallium oxide epitaxial wafer is placed in the reaction chamber of an inductively coupled plasma enhanced chemical vapor deposition system (ICP-CVD). The process conditions are set as follows: reaction chamber temperature 85℃, reaction chamber pressure 550Pa, and reaction chamber gas flow rate 300sccm. A SiO2 layer with a thickness of 750nm is deposited on the surface of the epitaxial wafer. The deposited wafer is then placed in a stripping solution to form a SiO2 barrier layer through stripping.

[0113] Step D: Fabricate an n-type conductive material layer.

[0114] Atomic layer deposition (ALD) was used, with the following process conditions: reaction chamber temperature 200℃, reaction chamber pressure 850Pa, reaction chamber gas high-purity nitrogen, and reaction chamber gas flow rate 300sccm. A 25nm thick layer of n-type conductive material In₂O₃ was deposited on the surface of a gallium oxide epitaxial wafer. Photolithography was then performed on the deposited epitaxial wafer to form the etchable region. The wafer was then placed in a reactive ion etching (RIE) system, with the following process conditions: reaction chamber pressure 1500mtorr, reaction chamber gas SF₆, CHF₃, and He, reaction chamber gas flow rate ratio SF₆:CHF₃:He = 5.5sccm:32sccm:150sccm, and RF source power 175W. This etched away the n-type conductive material on the etchable region of the epitaxial wafer, forming an ohmic contact region.

[0115] Step E: Ion implantation.

[0116] Photolithography was performed on the etched epitaxial wafer surface to form vertical conductive channel ion implantation regions. Then, Ge ion implantation was performed twice in these regions, with an implantation dose of 3 × 10⁻⁶. 14 cm -2 The injected energy is 10 keV. A doping concentration of 5×10⁻⁶ was formed. 18 cm -3 A highly doped region with a depth of 5 μm;

[0117] After ion implantation, the epitaxial wafer is placed in an N2 environment, and the temperature inside the annealing furnace is set to 950℃ for 30 minutes to activate the implanted ions.

[0118] Step F: Growing the gate medium.

[0119] Atomic layer deposition (ALD) was used, with the following process conditions: reaction chamber temperature of 220℃, reaction chamber pressure of 850Pa, reaction chamber gas of high-purity nitrogen, and reaction chamber gas flow rate of 300sccm. A 35nm thick Al2O3 gate dielectric was deposited on the surface of a gallium oxide epitaxial wafer.

[0120] Step G: Photolithography is used to form the source electrode metal region to be evaporated.

[0121] Photolithography was performed on the source electrode via on the Al2O3 surface. The reaction chamber pressure of the reactive ion etching (RIE) system was set to 20 mTorr, the reaction chamber gas was BCl3 and Ar, the gas flow rate ratio of the reaction chamber was BCl3:Ar = 20 sccm:10 sccm, and the etching power was 300 W. The Al2O3 in the electrode via area was etched away to form the source electrode metal region to be evaporated.

[0122] Step H: Fabricate source and drain ohmic electrodes.

[0123] H.1) The etched epitaxial wafer is photolithographically etched again to form the source electrode region. Ti / Au with a thickness of 70nm / 130nm is first deposited in the source electrode region by electron beam evaporation E-Beam system.

[0124] H.2) After electron beam evaporation, the wafer is placed in a stripping solution and the source electrode is formed by stripping.

[0125] H.3) A Ti / Au layer with a thickness of 70nm / 130nm is deposited on the substrate surface to form a drain electrode, and annealed in an N2 environment at a furnace temperature of 475℃ for one minute to form an ohmic contact.

[0126] H.4) Photolithography is performed on the Al2O3 surface to form the gate metal region to be evaporated.

[0127] Step I: Fabricate the gate electrode.

[0128] Ni / Au with a thickness of 55nm / 110nm is deposited in the gate metal region to be evaporated using an electron beam evaporation E-Beam system. After electron beam evaporation, the wafer is placed in a stripping solution and the gate electrode is formed by stripping, thus completing the device fabrication.

[0129] Example 3: An N-type β-Ga2O3 substrate with a thickness of 700 μm and a doping density of 5 × 10⁻⁶ μm was fabricated. 18 cm -3 The N-type β-Ga2O3 drift layer has a thickness of 10 μm and a doping density of 1 × 10⁻⁶. 17 cm -3 The SiO2 thickness is 1000 nm, the vertical heavily doped channel width is 20 μm, the thickness is 10 μm, and the doping concentration is 5 × 10⁻⁶. 19 cm -3 The n-type conductive material is In₂O₃, with a thickness of 50 nm and a doping density of 5 × 10⁻⁶. 19 cm -3 A vertical Ga2O3 field-effect transistor with a SiO2 barrier layer and a vertically heavily doped channel.

[0130] Step 1: Clean the β-Ga2O3 epitaxial wafer.

[0131] The specific implementation of this step is the same as step 1 in Example 1.

[0132] Step 2: Trench structure etching.

[0133] Photolithography is performed on the cleaned epitaxial wafer to form the area to be etched. The wafer is then placed in a reactive ion etching (RIE) system. The reaction chamber pressure is set to 1500 mtorr, the reaction chamber gas is SF6, CHF3, and He, and the gas flow rate ratio is SF6:CHF3:He = 5.5 sccm:32 sccm:150 sccm. The RF source power is 200W. Etching is performed to a depth of 1010 nm to remove gallium oxide from the area to be etched on the epitaxial wafer, forming a trench structure.

[0134] Step 3: Deposit SiO2.

[0135] The etched gallium oxide epitaxial wafer is placed in the reaction chamber of an inductively coupled plasma enhanced chemical vapor deposition system (ICP-CVD). Under the process conditions of a reaction chamber temperature of 90°C, a reaction chamber pressure of 600 Pa, and a reaction chamber gas flow rate of 300 sccm, a SiO2 layer with a thickness of 1000 nm is deposited on the surface of the epitaxial wafer. The deposited wafer is then placed in a stripping solution to form a SiO2 barrier layer through stripping.

[0136] Step 4: Fabricate an n-type conductive material layer.

[0137] Using atomic layer deposition (ALD), under the following process conditions: reaction chamber temperature 200℃, reaction chamber pressure 900Pa, reaction chamber gas high-purity nitrogen, reaction chamber gas flow rate 300sccm, a 50nm thick n-type conductive material In2O3 is deposited on the surface of a gallium oxide epitaxial wafer. Photolithography is then performed on the deposited epitaxial wafer to form the etchable region. The wafer is then placed in a reactive ion etching (RIE) system with a reaction chamber pressure of 1500mtorr, reaction chamber gases SF6, CHF3, and He, and a gas flow rate ratio of SF6:CHF3:He = 5.5sccm:32sccm:150sccm. The RF source power is 200W. This process etches away the n-type conductive material on the etchable region of the epitaxial wafer, forming an ohmic contact region.

[0138] Step 5: Ion implantation.

[0139] Photolithography was performed on the etched epitaxial wafer surface to form a vertical conductive channel ion implantation region. Then, Sn ion implantation was performed twice in the ion implantation region, with an implantation dose of 5 × 10⁻⁶. 14cm -2 The injected energy is 10 keV. A doping concentration of 5×10⁻⁶ was formed. 18 cm -3 A highly doped region with a depth of 5 μm;

[0140] After ion implantation, the epitaxial wafer is placed in an N2 environment, and the temperature inside the annealing furnace is set to 950℃ for 30 minutes to activate the implanted ions.

[0141] Step 6: Growing the gate medium.

[0142] Atomic layer deposition (ALD) was used to deposit a 50 nm thick Al2O3 gate dielectric on the surface of a gallium oxide epitaxial wafer under the following process conditions: reaction chamber temperature of 240 °C, reaction chamber pressure of 900 Pa, reaction chamber gas of high purity nitrogen, and reaction chamber gas flow rate of 300 sccm.

[0143] Step 7: Photolithography is used to form the source electrode metal region to be evaporated.

[0144] Photolithography was performed on the source electrode via on the Al2O3 surface. The reaction chamber pressure of the reactive ion etching (RIE) system was set to 20 mTorr, the reaction chamber gas was BCl3 and Ar, the gas flow rate ratio of the reaction chamber was BCl3:Ar = 20 sccm:10 sccm, and the etching power was 400 W. The Al2O3 in the electrode via area was etched away to form the source electrode metal region to be evaporated.

[0145] Step 8: Fabricate source and drain ohmic electrodes.

[0146] The etched epitaxial wafer is photolithographically etched again to form the source electrode region. Using an electron beam evaporation (E-Beam) system, a Ti / Au layer with a thickness of 80 nm / 140 nm is first deposited in the source electrode region. The evaporated wafer is then placed in a stripping solution and stripped to form the source electrode. Next, a Ti / Au layer with a thickness of 80 nm / 140 nm is deposited on the substrate surface to form the drain electrode. Annealing is then performed in an N2 environment at 475°C for one minute to form an ohmic contact. Finally, photolithography is performed on the Al2O3 surface to form the gate metal region to be evaporated.

[0147] Step 9: Fabricate the gate electrode.

[0148] Ni / Au with a thickness of 60nm / 120nm is deposited in the gate metal region to be evaporated using an electron beam evaporation E-Beam system. After electron beam evaporation, the wafer is placed in a stripping solution and the gate electrode is formed by stripping, thus completing the device fabrication.

[0149] The above are merely three embodiments of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principle of the present invention, may make various modifications and changes in form and detail without departing from the principle and structure of the present invention. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A vertical Ga2O3 transistor with a SiO2 barrier layer, comprising, from bottom to top, a gallium oxide substrate layer, a gallium oxide epitaxial layer, and a gate oxide layer, wherein a gate electrode is disposed above the gate oxide layer, and a drain electrode is disposed on the lower surface of the gallium oxide substrate layer, characterized in that: The epitaxial layer has a SiO2 current blocking layer on its inner periphery to achieve effective source-drain electrical isolation; a vertically heavily doped conductive channel is provided at the top center to reduce the on-resistance of the device; an n-type conductive layer is formed using the ALD process, so that the n-type conductive layer is located only on the SiO2 current blocking layer to achieve the regrowth of the n-type conductive material. The vertical heavily doped conductive channel is made of highly doped Ga2O3 material; A source electrode is provided above the n-type conductive layer.

2. The transistor according to claim 1, characterized in that: The gallium oxide substrate has a thickness of 500µm-700µm and a concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 N-type highly doped β-Ga2O3 materials.

3. The transistor according to claim 1, characterized in that: The gallium oxide epitaxial layer has a thickness of 3µm-10µm and a concentration of 1.5×10⁻⁶. 16 -1×10 17 cm -3 N-type low-doped β-Ga2O3 materials.

4. The transistor according to claim 1, characterized in that: The SiO2 current blocking layer has a thickness of 500nm-1000nm.

5. The transistor according to claim 1, characterized in that: The n-type conductive layer has a thickness of 5nm-50nm and a concentration of 1×10⁻⁶. 17 -5×10 19 cm -3 N-type highly doped GaN, SiC, or In2O3 wide-bandgap or ultra-wide-bandgap n-type conductive materials.

6. The transistor according to claim 1, characterized in that: The vertically heavily doped conductive channel has a thickness of 1µm-10µm, a width of 2µm-20µm, and a concentration of 1×10⁻⁶. 17 -5×10 19 cm -3 N-type highly doped β-Ga2O3 material.

7. A method for fabricating a vertically structured Ga2O3 transistor with a SiO2 barrier layer, characterized in that, Includes the following steps: 1) Clean the epitaxial wafer by sequentially immersing the homogeneous gallium oxide wafer in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 5 min-10 min each, and then drying it with nitrogen gas; the epitaxial wafer includes a gallium oxide substrate and a gallium oxide epitaxial layer on it. 2) Photolithography is performed on the cleaned epitaxial wafer to form etchable areas on both sides. Then, the wafer is placed in a reactive ion etching (RIE) system to etch away gallium oxide on the etchable areas of the epitaxial wafer to form a trench structure. 3) Place the etched gallium oxide epitaxial wafer into the reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system (ICP-CVD), set the reaction chamber temperature to 80℃-90℃, deposit SiO2 with a thickness of 500nm-1000nm on the surface of the epitaxial wafer, and then place the deposited wafer into the stripping solution to form a SiO2 barrier layer only in the trench structure through stripping. 4) An n-type conductive material with a thickness of 10nm-20nm is deposited on the surface of a gallium oxide epitaxial wafer using atomic layer deposition (ALD) technology; 5) Photolithography is performed on the deposited epitaxial wafer to form the area to be etched. Then, it is placed in a reactive ion etching (RIE) system to etch away the n-type conductive material on the area to be etched on the epitaxial wafer, so that an ohmic contact area is formed only on the SiO2 barrier layer. 6) Photolithography is performed on the etched epitaxial wafer to form an ion implantation region at the top center. Then, n-type conductive ions are implanted into this region by ion implantation technology to form a heavily doped conductive channel. 7) Using atomic layer deposition (ALD) technology, Al2O3 with a thickness of 20nm-50nm is deposited on the surface of gallium oxide epitaxial wafers after ion implantation; 8) Photolithographically print source electrode vias on the Al2O3 surface, and use a reactive ion etching (RIE) system to etch away the Al2O3 in the electrode via area; 9) The etched epitaxial wafer is photolithographically etched again to form the source electrode region. Ti / Au is first deposited in the source electrode region by electron beam evaporation E-Beam system. The source electrode is formed by peeling. The source electrode is only located on the ohmic contact region. Then Ti / Au is deposited on the back side of the substrate to form the drain electrode. The ohmic contact is formed by annealing in N2 environment. 10) Photolithography is performed on the gallium oxide epitaxial wafer after the ohmic contact is formed to form the gate region on the Al2O3 surface. Ni / Au is then deposited in the gate region by electron beam evaporation E-Beam system. The gate electrode is formed by lift-off to complete the device fabrication.

8. The method according to claim 7, wherein step 2) employs reactive ion etching (RIE) process, and the process conditions are as follows: Reaction chamber pressure: 1500-2000 mtorr Reaction chamber gases: SF6, CHF3, He Gas flow rate ratio in reaction chamber: SF6:CHF3:He = 5.5 sccm:32 sccm:150 sccm RF power source: 150-300W.

9. The method according to claim 7, wherein the n-type material is deposited using atomic layer deposition (ALD) in step 4), and the process conditions are as follows: Reaction chamber pressure: 800-900 Pa Reaction chamber gas: High-purity nitrogen Gas flow rate in reaction chamber: 300 sccm.

10. The method of claim 7, wherein step 6) involves ion implantation in the ion implantation region, wherein an implantation dose of 1e14cm is performed on the epitaxial wafer. -2 -5e14cm -2 One of the ions Si, Ge, Sn, F, or Cl with an energy of 10 keV is used to form a doping concentration of 1e19cm⁻¹. -3 -5e19cm -3 Highly doped regions with an injection depth of 1-10 μm.

11. The method according to claim 7, wherein in step 7), Al2O3 material is deposited using atomic layer deposition (ALD) under the following process conditions: Reaction chamber pressure: 800-900 Pa Reaction chamber gas: High-purity nitrogen Gas flow rate in reaction chamber: 300 sccm.

12. The method according to claim 7, wherein in step 8), Al2O3 is etched using reactive ion etching (RIE) under the following process conditions: Reaction chamber pressure: 10-30 mTorr Reaction chamber gases: BCl3, Ar Gas flow rate ratio in reaction chamber: BCl3:Ar = 20 sccm: 10 sccm Etching power: 200-400W.

13. The method according to claim 7, wherein: The thickness of the Ti / Au deposited in step 9) is 60nm / 120nm-80nm / 140nm. The Ni / Au deposited in step 10) has a thickness of 50nm / 100nm-60nm / 120nm.

Images