Driving circuit and related control chip circuit, power adapter and electronic device

Abstract

The application provides a driving circuit and related control chip circuit, power adapter and electronic equipment. The driving circuit comprises: an operational amplifier circuit, a comparator, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a first driving control module and a second driving control module. The first resistor, the second resistor and the first NMOS tube are used to form an LDO negative feedback system. The application can solve the EMI problem caused by the GaN power tube in the charging application and meet the precision requirement of the driving voltage of the GaN power tube.

Description

Technical Field

[0001] This application relates to the field of electronic technology, specifically to a drive circuit and related control chip circuit, power adapter, and electronic equipment. Background Technology

[0002] With advancements in manufacturing processes and continuous reductions in defect rates, gallium nitride (GaN) is becoming increasingly advantageous in electronic power supplies that convert AC / DC power, change voltage levels, and ensure reliable power supply as a function of a certain number of factors.

[0003] Furthermore, in practical applications, GaN is considered as a material for GaN power transistors. However, during charging, GaN operates at a high frequency and has a large di / dt, which can cause severe electromagnetic interference (EMI). Therefore, it is urgent to solve the EMI problem caused by GaN power transistors in charging applications. Summary of the Invention

[0004] This application provides a driving circuit and related control chip circuit, power adapter, and electronic device, which can solve the EMI problem caused by GaN power transistors in charging applications and meet the accuracy requirements of GaN power transistor driving voltage.

[0005] In a first aspect, embodiments of this application provide a driving circuit, the driving circuit comprising: an operational amplifier circuit, a comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first driving control module, and a second driving control module, wherein...

[0006] The non-inverting input terminal of the operational amplifier circuit is connected to a first power supply, the output terminal of the operational amplifier circuit is connected to the first terminal of the first NMOS transistor, the third terminal of the first NMOS transistor is connected to a second power supply, the second terminal of the first MOS transistor is connected to one end of a first resistor, and the other end of the first resistor is connected to the inverting input terminal of the operational amplifier circuit and grounded through a second resistor.

[0007] The non-inverting input of the comparator is connected to a third power supply, the output of the comparator is connected to the first input of an OR gate circuit, the second input of the OR gate circuit is used to receive a drive signal, and the drive signal is also input to the first terminal of the first drive control module.

[0008] The output of the OR gate circuit is connected to the first terminal of the second drive control module, and the second terminal of the second drive control module is connected to the first terminal of the second PMOS transistor. The second terminal of the second PMOS transistor is connected to the second terminal of the first PMOS transistor and the second terminal of the second NMOS transistor. The third terminal of the second PMOS transistor is connected to the drive port, which is used to drive the GaN power transistor. The third terminal of the second NMOS transistor is also connected to one end of the third resistor, and the other end of the third resistor is connected to one end of the fourth resistor and the inverting input terminal of the comparator.

[0009] The first terminal of the second NMOS transistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the first terminal of the first NMOS transistor and grounded through the first capacitor; the third terminal of the second NMOS transistor is connected to the second power supply.

[0010] The second terminal of the first drive control module is connected to the first terminal of the first PMOS transistor, the third terminal of the first drive control module is connected to the first terminal of the third NMOS transistor and the third terminal of the second drive control module, the third NMOS transistor is connected to the third terminal of the second PMOS transistor, and the second terminal of the third NMOS transistor is grounded.

[0011] Secondly, embodiments of this application provide a control chip circuit, the control chip circuit including the driving circuit described in the first aspect above.

[0012] Thirdly, embodiments of this application provide a power adapter, which includes a drive circuit as described in the first aspect, or a control chip circuit as described in the second aspect.

[0013] Fourthly, embodiments of this application provide an electronic device, which includes a driving circuit as described in the first aspect, or a control chip circuit as described in the second aspect, or a power adapter as described in the third aspect.

[0014] Implementing the embodiments of this application has the following beneficial effects:

[0015] As can be seen, the driving circuit, chip control circuit, power adapter, and electronic device described in the embodiments of this application include the following: the driving circuit includes an operational amplifier circuit, a comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first driving control module, and a second driving control module. The non-inverting input of the operational amplifier circuit is connected to a first power supply, the output of the operational amplifier circuit is connected to the first terminal of the first NMOS transistor, the third terminal of the first NMOS transistor is connected to a second power supply, the second terminal of the first NMOS transistor is connected to one end of a first resistor, and the other end of the first resistor is connected to the inverting input of the operational amplifier circuit and grounded through a second resistor. The non-inverting input of the comparator is connected to a third power supply, the output of the comparator is connected to the first input of an OR gate circuit, the second input of the OR gate circuit is used to input a driving signal, the driving signal is also input to the first terminal of the first driving control module, the output of the OR gate circuit is connected to the first terminal of the second driving control module, and the second terminal of the second driving control module is connected to the first terminal of the second PMOS transistor. The second terminal of the second PMOS transistor is connected to the second terminal of the first PMOS transistor and the second terminal of the second NMOS transistor. The third terminal of the second PMOS transistor is connected to the drive port, which is used to drive the GaN power transistor. The third terminal of the second NMOS transistor is also connected to one end of the third resistor. The other end of the third resistor is connected to one end of the fourth resistor and the inverting input of the comparator. The first terminal of the second NMOS transistor is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the first terminal of the first NMOS transistor and grounded through the first capacitor. The third terminal of the second NMOS transistor is connected to the second power supply. The second terminal of the first drive control module is connected to the first terminal of the first PMOS transistor. The third terminal of the first drive control module is connected to the first terminal of the third NMOS transistor and the third terminal of the second drive control module. The third NMOS transistor is connected to the third terminal of the second PMOS transistor. The second terminal of the third NMOS transistor is grounded. This method uses an LDO op-amp to clamp the upper limit of the output drive voltage to ensure that the upper limit of the output drive voltage is strictly clamped to about 6V, meeting the drive requirements of GaN devices. At the same time, a two-stage drive method is adopted to detect the magnitude of the output drive voltage to improve EMI performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an NMOS transistor provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a PMOS transistor provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0020] Figure 4 This is another schematic diagram of a driving circuit provided in an embodiment of this application;

[0021] Figure 5 This is another schematic diagram of a driving circuit provided in an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the structure of a drive control circuit provided in an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of another drive control circuit provided in an embodiment of this application;

[0024] Figure 8 The embodiments provided in this application are based on Figure 5 A schematic diagram of the signal waveform of the drive circuit. Detailed Implementation

[0025] To help those skilled in the art better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the description of the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, software, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but also includes steps or units not listed, or other steps or units inherent to such processes, methods, products, or apparatus.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] The embodiments of this application are described below with reference to the accompanying drawings. In the drawings, the intersection of intersecting wires is indicated by dots, and the absence of dots indicates that the wires are not connected.

[0029] To better understand the solutions of the embodiments of this application, the relevant terms and concepts that may be involved in the embodiments of this application will be introduced below.

[0030] GaN devices feature low on-resistance and high operating frequency, meeting the requirements of next-generation electronic equipment for higher power, higher frequency, smaller size, and harsher high-temperature operation. GaN power devices offer superior overall performance and can be epitaxially grown on a silicon substrate. Considering area and overall cost, they are potentially more cost-effective than silicon carbide devices, thus finding applications in high-power, high-frequency semiconductor devices.

[0031] With advancements in manufacturing processes and continuously decreasing defect rates, GaN's advantages in electronic power supplies—specifically, AC / DC power conversion, voltage level modification, and ensuring reliable power supply as a function of a certain number of factors—are becoming increasingly apparent. Power supply designers are rethinking circuit design, seeking ways to fully realize the potential of new GaN transistors while avoiding negative impacts in creating power systems. A common approach to this is to find solutions within existing components—GaN switches, Si switch drivers, high-speed switching controllers, and components in the overall design such as power inductors, transformers, and capacitors. Integrated circuit (IC) manufacturers producing power supply products can significantly increase the possibilities of power supply design if they can provide system-level solutions using co-designed devices, or even integrate multiple chips in modular packages.

[0032] Compared with silicon (Si)-based power electronic devices, GaN-based power electronic devices have the following three advantages:

[0033] 1. High efficiency and energy saving: Due to the unique polarization characteristics of GaN materials, there is a very strong polarization effect between AlGaN / GaN heterojunctions, forming a high-concentration two-dimensional electron gas (2DEG) with a mobility of up to 2000 and an areal density on the order of 1000. GaN-based power switching devices (HFETs) operate using the AlGaN / GaN heterojunction 2DEG, and the devices have the advantages of low on-resistance and fast switching speed, which greatly reduces the conduction loss and switching performance of the devices.

[0034] 2. GaN enables miniaturization, weight reduction, and cost reduction of power electronic devices: GaN materials have a larger bandgap than Si, allowing GaN devices to operate in higher temperature environments, thus simplifying or even eliminating the need for heat dissipation devices. Furthermore, the high switching frequency of GaN devices significantly reduces the size of passive components such as capacitors and inductors. All of these factors contribute to the miniaturization and weight reduction of GaN-based power electronic devices, greatly lowering system manufacturing costs.

[0035] 3. High output power density and strong driving force: Due to its wide bandgap and other characteristics, GaN material has a critical breakdown electric field as high as 3.4 MV / cm, which is 10 times that of Si material. Therefore, GaN devices have higher breakdown voltage. At the same time, GaN-based devices operate using 2DEG, achieving low on-resistance and high current density, thus enabling GaN devices to achieve greater power density.

[0036] Compared to silicon MOSFETs, gallium nitride-based field-effect transistors (GaN) operate much faster at lower gate threshold voltages. Furthermore, GaN FETs have lower internal gate resistance, and their body diode reverse recovery characteristics are far superior to those of silicon MOSFETs. GaN FETs have some output capacitance, but it is significantly lower than that of silicon. In practical applications, GaN transistors exhibit lower resistance (RDS(ON)) and gate charge QG. More importantly, GaN transistors are not affected by the strong negative temperature coefficient found in MOSFETs. Therefore, the drive requirements for GaN FETs, whether they are on or off, will be completely different from those for silicon MOSFETs.

[0037] Compared to traditional Si drivers, GaN driver circuits offer higher switching frequencies, require lower drive voltages, and are more efficient. For power supply designers, factors to consider when driving GaN devices include:

[0038] (1) Low threshold voltage

[0039] The threshold voltage of GaN FETs is typically below 1.5V, with a minimum as low as 0.7V, which is lower than many MOSFETs, but it changes almost flat with temperature.

[0040] (2) Strict upper limit requirement for gate-source voltage: VGS(MAX) = 6V. On the one hand, VGS must be set below 5.5V to reserve a safety margin of 0.5V. On the other hand, it can be seen from the Rds(ON) vs. VGS curve that RDS(ON) can reach its minimum value when VGS = 4.5-5.5V, which means reduced conduction losses. Taking all factors into consideration, VGS is set at 5V. Problems brought about by the gate-source voltage design requirements: The gate-source voltage must be strictly controlled to avoid damaging the gate of the GaN FET power transistor, and the ordinary bias suitable for MOSFET driving cannot be used directly.

[0041] (3) EMI issues

[0042] Because GaN can operate at high frequencies, it exhibits a large dV / dt ratio. This can cause serious EMI problems.

[0043] In addition, in the embodiments of this application, such as Figure 1 As shown, for an NMOS transistor, the first terminal is the gate, the second terminal is the source, the third terminal is the drain, the fourth terminal is the substrate, and the fifth terminal is grounded; as shown... Figure 2 As shown, for a PMOS transistor, the first terminal is the gate, the second terminal is the source, the third terminal is the drain, and the fourth terminal is the substrate. The fourth terminal is used to connect to the power supply, such as VDD. For the drive control module, its first terminal is DR, the second terminal is DU, and the third terminal is DW.

[0044] In related technologies, such as Figure 3 As shown, Figure 3 This is a traditional drive control circuit, where the drive module drives the transistors stage by stage through an inverter chain. The output voltage drives the external MOS power transistors. The external MOS power transistors have a non-negligible capacitance between their gate and source. To quickly turn the drain current on or off, a large current is needed to drive the gate voltage up or down. The drive uses a single-stage control method: when the Drive signal is 0, the gate voltage of NMOS transistor N1 is high. Simultaneously, N1 turns on, outputting a large current, and the GATE voltage instantly rises. Similarly, when the Drive signal is 1, NMOS transistors N2 and N3 are turned on, instantly pulling the GATE voltage down.

[0045] Among them, based on Figure 1 The drawback of the driver circuit shown is that it uses a single-stage control method, resulting in large di / dt variations during switching and poor EMI performance. Furthermore, the output voltage is limited by the VCC voltage, with a maximum range of VCC-VGS. The output voltage changes with VCC, which is detrimental to GaN drivers. To use this driver, additional circuitry is needed to control VCC, increasing costs.

[0046] Furthermore, Figure 4 This is a driver circuit based on a resonant drive principle. The core idea is to incorporate an LC resonant circuit into the drive circuit, utilizing the parasitic capacitance inside the switching transistor and the resonance with an external inductor to drive the switching transistor, and effectively recovering the energy stored in the resonant inductor, thereby reducing drive losses. However, this control circuit is complex, requiring additional circuitry to control VCC, and the resonant drive only demonstrates its advantages in ultra-high frequency applications. It is not suitable for flyback structures.

[0047] Therefore, based on the deficiencies of the aforementioned related technologies, embodiments of this application provide a driving circuit, a chip control circuit, a power adapter, and an electronic device to address the aforementioned deficiencies.

[0048] Please see Figure 5 , Figure 5 This is a schematic diagram of a driving circuit provided in an embodiment of this application. The driving circuit includes: an operational amplifier circuit OP1, a comparator CMP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a first driving control module CTRL1, and a second driving control module CTR2.

[0049] The non-inverting input (+) of the operational amplifier circuit OP1 is connected to the first power supply S1. The output of the operational amplifier circuit OP1 is connected to the first terminal of the first NMOS transistor MN1. The third terminal of the first NMOS transistor MN2 is connected to the second power supply VDD. The second terminal of the first MOS transistor MN1 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the inverting input (-) of the operational amplifier circuit OP1 and grounded through the second resistor R2.

[0050] The non-inverting input (+) of the comparator CMP1 is connected to the third power supply S2, the output of the comparator CMP1 is connected to the first input of the OR gate circuit, the second input of the OR gate circuit is used to input the drive signal Drive_P, and the drive signal Drive_P is also input to the first terminal of the first drive control module CTRL1.

[0051] The output of the OR gate circuit is connected to the first terminal of the second drive control module, and the second terminal of the second drive control module is connected to the first terminal of the second PMOS transistor MP2. The second terminal of the second PMOS transistor MP2 is connected to the second terminal of the first PMOS transistor MP1 and the second terminal of the second NMOS transistor MN2. The third terminal of the second PMOS transistor MN2 is connected to the drive port GATE, which is used to drive the GaN power transistor. The third terminal of the second NMOS transistor MN2 is also connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the inverting input terminal (-) of the comparator CMP1.

[0052] The first terminal of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the first terminal of the first NMOS transistor NM1 and grounded through the first capacitor C1; the third terminal of the second NMOS transistor MN2 is connected to the second power supply VDD.

[0053] The second terminal of the first drive control module CTRL1 is connected to the first terminal of the first PMOS transistor MP1. The third terminal of the first drive control module CTRL1 is connected to the first terminal of the third NMOS transistor MN3 and the third terminal of the second drive control module CTRL2. The third NMOS transistor MN3 is connected to the third terminal of the second PMOS transistor MP2. The second terminal of the third NMOS transistor MN3 is grounded.

[0054] R1 and R2 can be replaced with a variable resistor, which adjusts the ratio between R1 and R2. R3 and R4 can also be replaced with a variable resistor, which adjusts the ratio between R3 and R4.

[0055] Optionally, the operational amplifier circuit OP1, the first resistor R1, the second resistor R2, and the first NMOS transistor MN1 are used to form an LDO negative feedback system;

[0056] The negative feedback system is used to dynamically adjust the current of the first NMOS transistor MN1 by using the ratio between the first resistor R1 and the second resistor R2, and the operational amplifier circuit OP1, so as to obtain the first output voltage V1 at the second terminal of the first NMOS transistor MN1.

[0057] When the first output voltage V1 is less than the first output voltage design value, the output of the operational amplifier circuit OP1 becomes high, the current through the first NMOS transistor NM1 increases, and the first output voltage V1 increases.

[0058] Conversely, when the first output voltage is greater than the design value of the first output voltage, the output of the operational amplifier circuit becomes lower, the current through the first NMOS transistor decreases, and the first output voltage decreases, thereby realizing the dynamic adjustment of the first output voltage at the second terminal of the first NMOS transistor.

[0059] The first output voltage design value can be preset or set by system default. For example, the first output voltage design value can be a set value, i.e., an empirical value.

[0060] Optionally, the absolute value of the difference between the second output voltage V2 at the second terminal of the second NMOS transistor MN2 and the first output voltage V1 is less than a preset threshold.

[0061] The preset threshold can be set in advance or be the system default. The preset threshold can be close to 0, for example, the preset threshold is 0.01.

[0062] Optionally, the first output voltage V1 is determined by the input voltage VREF at the non-inverting input terminal (+) of the operational amplifier circuit OP1, the first resistor R1, and the second resistor R2. The specific calculation formula is as follows:

[0063] V1 = VREF * (R1 + R2) / R2

[0064] Optionally, the second output voltage V2 is determined by the input voltage VREF at the non-inverting input terminal (+) of the operational amplifier circuit OP1, the first resistor R1, and the second resistor R2, and the specific calculation formula is as follows:

[0065] V2 = VREF * (R1 + R2) / R2

[0066] Optionally, the drive signal Drive_P is used to turn on the first PMOS transistor MP1 and turn off the third NMOS transistor MN3 through the first drive control module CTRL1. The third output voltage VO_ADOPT is obtained by voltage division through the third resistor R3 and the fourth resistor R4. The third output voltage VO_ADOPT is used as the first input signal of the inverting input terminal (-) of the comparator CMP1 and compared with the second input signal of the non-inverting input terminal (+) of the comparator CMP1 to obtain the drive control signal. The drive control signal and the drive signal Drive_P are passed through an OR gate circuit to obtain the output signal. The second PMOS transistor is turned on through the output signal, and the first PMOS transistor MP1 and the second PMOS transistor MP1 are charged simultaneously.

[0067] Optionally, the first drive control module CTRL1 includes M inverters, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, where M is an even number;

[0068] The first terminal of the first drive control module CTRL1 is connected to the second terminal of the first drive control module CTRL1 and the first terminal of the fifth NMOS transistor MN5 through the M inverters; the second terminal of the fifth NMOS transistor MN5 is grounded.

[0069] The first terminal of the first drive control module CTRL1 is connected to the first terminal of the fourth NMOS transistor MN4. The second terminal of the fourth NMOS transistor MN4 is grounded. The third terminal of the fourth NMOS transistor MN4 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the third terminal and the first terminal of the third PMOS transistor MP3. The first terminal of the third PMOS transistor MP3 is connected to the first terminal of the fourth PMOS transistor MP4. The third terminal of the fourth PMOS transistor MP4 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the third terminal of the first drive control module CTRL1 and the third terminal of the fifth NMOS transistor MN5. The second terminals of the third PMOS transistor MP3 and the second terminals of the fourth PMOS transistor MP4 are both connected to the second power supply VDD.

[0070] Specifically, such as Figure 6 As shown, Figure 6 In the diagram, M=4, meaning we'll use four inverters as an example. The inverters are represented by triangles in the diagram. Inverters can improve driving capability and also achieve a delay effect.

[0071] Optionally, the second drive control module CTRL2 includes N inverters, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6, where N is an even number;

[0072] The first terminal of the second drive control module CTRL2 is connected to the second terminal of the second drive control module CTRL2 and the first terminal of the seventh NMOS transistor MN7 through the N inverters; the second terminal of the seventh NMOS transistor MN7 is grounded.

[0073] The first terminal of the second drive control module CTRL is connected to the first terminal of the sixth NMOS transistor MN6. The second terminal of the sixth NMOS transistor MN6 is grounded. The third terminal of the sixth NMOS transistor MN6 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to the third and first terminals of the fifth PMOS transistor MP5. The first terminal of the fifth PMOS transistor MP5 is connected to the first terminal of the sixth PMOS transistor MP6. The third terminal of the sixth PMOS transistor MP6 is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the third terminal of the second drive control module CTRL2 and the third terminal of the seventh NMOS transistor MN7. The second terminals of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both connected to the second power supply VDD.

[0074] Specifically, such as Figure 7 As shown, Figure 7In the diagram, N=4, meaning we'll use 4 inverters as an example. The inverters are represented by triangles in the diagram. Inverters can improve driving capability and also achieve a delay effect.

[0075] In this embodiment, the OR gate circuit controls the first and second drive control circuits to operate at different times, thus forming a two-stage drive control. By employing two-stage drive control and LDO operational amplifier clamping of the output drive voltage upper limit, EMI is improved, and the accuracy of the chip drive voltage is increased, preventing damage to GaN devices due to output voltage fluctuations. Therefore, it is possible to improve chip EMI while meeting GaN drive requirements.

[0076] In the specific implementation, the operational amplifier OP1, resistors R1 and R2, and NMOS transistor MN1 constitute the LDO circuit.

[0077] The specific working principle of the above-mentioned driving circuit is as follows: The LDO is a negative feedback system. By utilizing the ratio of R1 and R2, and the dynamic adjustment of the current through MN1 by the operational amplifier, the precise value of the output voltage (V1) can be achieved. When the output voltage V1 is less than the design value, the output of OP1 increases, the current through MN1 increases, and the output voltage V1 increases. When the output voltage V1 is greater than the design value, the output of OP1 decreases, the current through MN1 decreases, and the output voltage V1 decreases. Thus, the output voltage V1 is maintained at the design value. Similarly, by connecting the first terminals of MN2 and MN1 together, and matching them as closely as possible, the output voltage V2 can be maintained at the design value, that is, V1 and V2 are equal or nearly equal. The function of capacitor C1 is to stabilize the gate voltage of the MOS transistor, reduce the bandwidth of the LDO, and increase the stability of the LDO system. At the same time, C1 and R5 form a low-pass filter, which can reduce the influence of the gate voltage of MN2 on the gate voltage of MN1.

[0078] The above settings can be determined based on the drive voltage of the GAN power amplifier of the device to be driven.

[0079] In the specific implementation, the two-stage drive works as follows: First, the drive signal Drive_P passes through the drive control module CTRL1 (circuit such as...). Figure 6 As shown, MP1 is turned on and MN3 is turned off, causing the output voltage to rise. Then, the output voltage is sampled by voltage division through resistors R3 and R4. The sampled output voltage is compared with the reference voltage VREF1 by comparator CMP1 to output two-stage drive control signals. These signals are then ORed with the signal Drive_P, which turns on PM2 through control module CTRL2. Finally, MP1 and MP2 simultaneously provide charging. This causes the drive current to change from small to large, and the drive voltage to change from low to high in a slow, gradual process. This reduces di / dt spikes and improves EMI performance.

[0080] In this embodiment, to address the driving requirements of GaN devices, an LDO operational amplifier is used to clamp the upper limit of the output drive voltage, ensuring that the upper limit of the output drive voltage is strictly clamped at around 6V. Simultaneously, a two-stage driving method is employed to detect the magnitude of the output drive voltage, improving EMI performance. This approach satisfies the GaN driving requirements, maintaining the output drive voltage well at 6V to prevent damage to the GaN from output voltage fluctuations, while also improving the chip's EMI performance. Figure 5 The driving circuit shown is Figure 3 Compared to the driving circuit shown, the embodiments of this application have lower EMI and lower cost; Figure 5 The driving circuit shown is Figure 4 Compared to the driving circuit shown, the embodiments of this application have lower EMI and are applicable to flyback structures.

[0081] The first power supply and the third power supply can both be AC / DC power supplies, DC / DC power supplies, regulated power supplies, communication power supplies, module power supplies, frequency converters, inverters, AC regulated power supplies, DC regulated power supplies, etc., and this application does not limit them. The first power supply and the second power supply can be the same power supply or different power supplies.

[0082] Furthermore, the GaN power transistor outputs power to the power-consuming device to charge it. The power-consuming device can be understood as a device that needs to be charged by the user. User equipment can include, but is not limited to: smartphones, tablets, smart robots, smart elevators, in-vehicle equipment, wearable devices, smart home devices, computing devices or other processing devices connected to a wireless modem, as well as various forms of user equipment (UE), mobile station (MS), terminal device, etc.

[0083] In specific implementation, such as Figure 8 As shown, the waveforms of the Drive_P, DU1, DU2, and GATE signals are displayed. It can be seen that the drive current can be varied from small to large, and the drive voltage can be gradually increased from low to high. This reduces di / dt spikes and improves EMI performance.

[0084] Furthermore, the aforementioned driving circuit can be applied to a control chip circuit, which may include at least one of the following: an AC-DC chip control circuit and a DC-DC chip control circuit, without limitation. The AC-DC chip control circuit may be a flyback AC-DC chip control circuit or a non-flyback AC-DC chip control circuit.

[0085] Thus, in practical implementation, a two-stage drive control and LDO op-amp clamping output drive voltage upper limit technology are used, which not only improves EMI but also increases the accuracy of the chip drive voltage, avoiding damage to GaN devices due to fluctuations in the output voltage value. For example, this drive can be used in a flyback ACDC control chip circuit to drive GaN power transistors.

[0086] Furthermore, both the aforementioned drive circuit and the aforementioned control chip circuit can be applied to power adapters.

[0087] Of course, embodiments of this application also provide an electronic device, which may include, for example: Figure 5 The described drive circuit, chip control circuit, or power adapter, for example, an electronic device, can be a power bank or charger.

[0088] The above are the implementation methods of the embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the embodiments of this application, and these improvements and modifications are also considered to be within the protection scope of this application.

Claims

1. A drive circuit characterized by comprising: The driving circuit includes: an operational amplifier circuit, a comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first driving control circuit, and a second driving control circuit, wherein... The non-inverting input terminal of the operational amplifier circuit is connected to a first power supply, the output terminal of the operational amplifier circuit is connected to the first terminal of the first NMOS transistor, the third terminal of the first NMOS transistor is connected to a second power supply, and the second terminal of the first NMOS transistor is connected to the inverting input terminal of the operational amplifier circuit through a first resistor; the first resistor is a variable resistor. The non-inverting input of the comparator is connected to a third power supply, the output of the comparator is connected to the first input of an OR gate circuit, the second input of the OR gate circuit is used to receive a drive signal, and the drive signal is also input to the first terminal of the first drive control circuit. The output of the OR gate circuit is connected to the first terminal of the second drive control circuit, and the second terminal of the second drive control circuit is connected to the first terminal of the second PMOS transistor. The second terminal of the second PMOS transistor is connected to the second terminal of the first PMOS transistor and the second terminal of the second NMOS transistor. The third terminal of the second PMOS transistor is connected to the drive port, which is used to drive the GaN power transistor. The third terminal of the second PMOS transistor is also connected to one end of the fourth resistor and the inverting input terminal of the comparator through the third resistor. The first terminal of the second NMOS transistor is connected to the first terminal of the first NMOS transistor through one end of the fifth resistor and grounded through the first capacitor; the third terminal of the second NMOS transistor is connected to the second power supply. The second terminal of the first drive control circuit is connected to the first terminal of the first PMOS transistor, the third terminal of the first drive control circuit is connected to the first terminal of the third NMOS transistor and the third terminal of the second drive control circuit, the third terminal of the third NMOS transistor is connected to the third terminal of the second PMOS transistor, and the second terminal of the third NMOS transistor is grounded.

2. The drive circuit according to claim 1, characterized in that, The operational amplifier circuit, the first resistor, the second resistor, and the first NMOS transistor are used to form an LDO negative feedback system; The negative feedback system is used to dynamically adjust the current of the first NMOS transistor by using the ratio between the first resistor and the second resistor, and the operational amplifier circuit, so as to obtain the first output voltage at the second terminal of the first NMOS transistor. When the first output voltage is less than the design value of the first output voltage, the output of the operational amplifier circuit becomes higher, the current through the first NMOS transistor increases, and the first output voltage increases. Conversely, when the first output voltage is greater than or equal to the first output voltage design value, the output of the operational amplifier circuit becomes lower, the current through the first NMOS transistor decreases, and the first output voltage decreases, thereby dynamically adjusting the first output voltage at the second terminal of the first NMOS transistor.

3. The drive circuit according to claim 2, characterized in that, The absolute value of the difference between the second output voltage at the second terminal of the second NMOS transistor and the first output voltage is less than a preset threshold.

4. The drive circuit according to claim 3, characterized in that, The first output voltage is determined by the input voltage at the non-inverting input terminal of the operational amplifier circuit, the first resistor, and the second resistor; And / or, the second output voltage is determined by the input voltage at the non-inverting input terminal of the operational amplifier circuit, the first resistor, and the second resistor.

5. The drive circuit according to any one of claims 1 to 4, characterized by The drive signal is used to turn on the first PMOS transistor and turn off the third NMOS transistor through the first drive control circuit. A third output voltage is obtained by voltage division through the third resistor and the fourth resistor. The third output voltage is used as the first input signal of the inverting input terminal of the comparator. The second input signal of the non-inverting input terminal of the comparator is compared to obtain the drive control signal. The drive control signal and the drive signal are passed through an OR gate circuit to obtain an output signal. The second PMOS transistor is turned on through the output signal, and the first PMOS transistor and the second PMOS transistor are charged simultaneously.

6. The drive circuit according to any one of claims 1 to 4, characterized by The first drive control circuit includes M inverters, a fourth NMOS transistor, a fifth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, where M is an even number; The first terminal of the first drive control circuit is connected to the second terminal of the first drive control circuit and the first terminal of the fifth NMOS transistor through the M inverters; the second terminal of the fifth NMOS transistor is grounded. The first terminal of the first drive control circuit is connected to the first terminal of the fourth NMOS transistor, the second terminal of the fourth NMOS transistor is grounded, the third terminal of the fourth NMOS transistor is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the third terminal and the first terminal of the third PMOS transistor, the first terminal of the third PMOS transistor is connected to the first terminal of the fourth PMOS transistor; the third terminal of the fourth PMOS transistor is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to the third terminal of the first drive control circuit and the third terminal of the fifth NMOS transistor; the second terminals of the third PMOS transistor and the second terminal of the fourth PMOS transistor are both connected to the second power supply.

7. The drive circuit according to any one of claims 1 to 4, characterized by The second drive control circuit includes N inverters, a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor, where N is an even number; The first terminal of the second drive control circuit is connected to the second terminal of the second drive control circuit and the first terminal of the seventh NMOS transistor through the N inverters; the second terminal of the seventh NMOS transistor is grounded. The first terminal of the second drive control circuit is connected to the first terminal of the sixth NMOS transistor, the second terminal of the sixth NMOS transistor is grounded, the third terminal of the sixth NMOS transistor is connected to one end of the eighth resistor, the other end of the eighth resistor is connected to the third and first terminals of the fifth PMOS transistor, the first terminal of the fifth PMOS transistor is connected to the first terminal of the sixth PMOS transistor; the third terminal of the sixth PMOS transistor is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to the third terminal of the second drive control circuit and the third terminal of the seventh NMOS transistor; the second terminals of the fifth PMOS transistor and the second terminal of the sixth PMOS transistor are both connected to the second power supply.

8. A control chip circuit, characterized by The control chip circuit includes the drive circuit described in any one of claims 1-7.

9. A power adapter, characterized by The power adapter includes the drive circuit described in any one of claims 1-7, or the control chip circuit described in claim 8.

10. An electronic device, comprising: The electronic device includes a drive circuit as described in any one of claims 1-7, or a control chip circuit as described in claim 8, or a power adapter as described in claim 9.

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