A fiber optic bidirectional transmission module and method of transmission

Abstract

The application discloses a kind of optical fiber bidirectional transmission module and optical fiber bidirectional ring network time and frequency stable transmission method, including by two equal length optical fibers connection, respectively as master station and slave station two transmission module board cards based on TDC on FPGA, each transmission module board card includes left optoelectronic conversion module, right optoelectronic conversion module, TDC time measurement module one and TDC time measurement module two, master station is synchronized with external time reference, after obtaining higher precision time and frequency signal, time information is transmitted to left and right ends by encoding and decoding module and optoelectronic conversion module, high-precision time stamp is forwarded back and forth between master station and slave station to calculate compensation optical fiber link delay, complete optical fiber bidirectional time and frequency synchronization;Master station and slave station both have left and right two optical fiber interfaces, can realize optical fiber ring network transmission, single optical fiber line failure does not affect the normal transmission of time frequency in ring network, in the process of time and frequency synchronization, it does not affect the information interaction between the sites in ring network.

Description

Technical Field

[0001] This invention belongs to the field of optical fiber and time-frequency technology, specifically relating to an optical fiber bidirectional transmission module and its transmission method. Background Technology

[0002] With the rapid development of industries such as power, communications, and finance, the requirements for time synchronization accuracy are becoming increasingly stringent. Fiber optic time synchronization, with its advantages of low cost, high stability, and anti-interference, is widely used in various industries.

[0003] Currently, the mainstream fiber optic time synchronization technologies include fiber optic time synchronization technology and fiber optic frequency synchronization technology.

[0004] Fiber optic time synchronization technology is primarily based on DWDM time synchronization. This scheme calculates and compensates for transmission delay through methods such as link symmetry, enabling a high degree of time synchronization between the two ends. It is suitable for long-distance, high-precision scenarios and is a common choice for achieving fiber optic time synchronization. Currently, it is mainly accomplished through two methods: loopback and bidirectional comparison.

[0005] Fiber optic frequency synchronization technology achieves extremely high stability and is widely used for frequency comparison between timekeeping laboratories, as well as for the transmission, traceability, and comparison of various physical quantities in precision measurement. Based on the transmission frequency, it can be divided into three synchronization technologies: microwave frequency transmission, optical frequency compensation transmission, and optical comb signal transmission.

[0006] However, these technologies can only achieve one type of transmission and synchronization, either in time or frequency, and therefore have limitations. Summary of the Invention

[0007] One of the objectives of this invention is to provide a fiber optic bidirectional transmission module that can simultaneously transmit frequency and time, addressing the shortcomings of existing technologies.

[0008] The technical solution adopted by this invention to solve its technical problem is: a fiber optic bidirectional transmission module, comprising two FPGA-based TDC transmission module boards connected by two equal-length optical fibers, serving as a master station and a slave station respectively. The FPGA has a Niso II soft core and a digital phase-locked loop. Each transmission module board includes a left photoelectric conversion module, a right photoelectric conversion module, a TDC time measurement module one, and a TDC time measurement module two. Both the left and right photoelectric conversion modules are composed of two O / E modules connected in series. One O / E module of the right photoelectric conversion module is connected to an encoding module and one O / E module of the left photoelectric conversion module. The encoding module is connected to a temperature-controlled crystal oscillator, which is connected to the TDC time measurement module two. The other O / E module of the right photoelectric conversion module is connected to a decoding module and another O / E module of the left photoelectric conversion module. The module is connected to TDC time measurement module one, which is connected to the second generation module. The second generation module is connected to the temperature-controlled crystal oscillator. TDC time measurement module one and TDC time measurement module two receive external second reference signals and external frequency reference signals, respectively. After completing clock difference measurement and frequency difference measurement, the second output and frequency output are respectively generated through the second generation module and the temperature-controlled crystal oscillator. The temperature-controlled crystal oscillator simultaneously outputs a 4M frequency waveform to the second generation module, the encoding module and TDC time measurement module two. The left photoelectric conversion module of the slave station is connected to the right photoelectric conversion module of the master station as an extension terminal, and they communicate via optical fiber.

[0009] Furthermore, the FPGA used is Altera's EP4CE115F23I7, and the TDC uses the TDC_GPX chip.

[0010] The second objective of this invention is to provide a method for stable time and frequency transmission in a bidirectional ring network, comprising the following steps:

[0011] S1 divides the fiber optic communication network into four layers, from lowest to highest: the physical layer, the encoding and decoding layer, the link control layer, and the general service layer. Each layer processes its corresponding data stream according to its function: the physical layer (network layer-0) includes the transmission of intermediate media, the interface of the photoelectric conversion module, and how the receiver and transmitter work; the encoding and decoding layer (network layer-1) mainly converts the high and low level signals of the physical layer into 0 and 1 signals, and also converts the byte data from the link control layer into 0 and 1 signals for processing by the physical layer; the link control layer (network layer-2) is mainly responsible for marking received and transmitted data frames with high-precision timestamps, verifying and extracting received data, and integrating transmitted data frames; the general service layer (network layer-3) mainly includes data forwarding and receiving for upper-layer applications. The data format and protocol of upper-layer applications can be freely defined, facilitating subsequent expansion and improvement.

[0012] S2, the slave station achieves frequency following and synchronization with the master station. The 4M frequency waveform transmitted from the physical layer is divided into a 2M signal. At the same time, the 10M frequency signal of the local constant temperature crystal oscillator is also divided into 2M by the PLL. The phase difference between the two signals is measured by the TDC time measurement module and the local frequency after division. Data filtering is then performed to achieve digital phase locking. A PI controller is used to achieve frequency following and synchronization between the slave station and the master station, ensuring frequency stability between the master and slave stations.

[0013] S3 encodes and parses the data stream in the data link layer. After parsing, it performs high-precision timestamp marking on the sending and receiving times of each data packet frame. These timestamps are provided to upper-layer service applications to realize fiber optic bidirectional data link delay and clock bias analysis and calculation. The data link delay and clock bias analysis and calculation is performed through bidirectional communication between the master station and the slave station. When the outbound and return data link delays are equal, the clock bias Δ is calculated and transmitted to the second generation module to adjust the local second and realize time synchronization between the master and slave stations.

[0014] S4, the general service layer packages the data information to be sent, source address, and target address and passes them to the underlying layer of the FPGA (written in pure Verilog under the soft core Niso II). The FPGA sends the initial parameters of each module after power-on, according to the conversion data format of each external interface, and the buffered fiber optic communication parsing data to Niso II for the upper-layer Niso II program to read and call, and generates an interrupt signal from the FPGA to Niso II. The underlying layer realizes automatic forwarding of information, and the data content can be customized, which facilitates the subsequent expansion and adjustment of the upper-layer protocol. The custom protocol is to leave a common data interface for the upper-layer application. The upper-layer application can build the link topology through the custom protocol. Niso II initializes the variables of each interrupt response program of the soft core, reads the initialization information in EEPROM to distinguish the initial working mode of the board, responds to the interrupt from the FPGA to Niso II, identifies the interrupt trigger source, and enters different response functions according to different trigger sources. The synchronous processing programs include: fiber optic transmission processing, fiber optic reception processing, crystal oscillator discipline, external second synchronization, etc.

[0015] Furthermore, the encoding and decoding in step S1 adopts the encoding method of IRIG-B(DC) code, using different pulse widths to represent logic "1" and logic "0", removing the flag bit "P", with each symbol duration of 250ns, a logic "1" pulse width of 100ns, and a logic "0" pulse width of 200ns; data is transmitted serially in the optical fiber link in byte form, with each data byte containing 10 bits, including a 1-bit start bit, 8-bit data bits, and 1 stop bit. The optical fiber data transmission line maintains a logic "1" signal when idle, and when the device sends a logic "0" signal, the start bit represents... The start byte indicates the beginning of the data transmission. In the main byte, after the valid data transmission in the fiber optic cable is completed, the stop bit is represented by a logic "1". In the start byte and stop byte, the stop bit is represented by a logic "0". The width of the data bits is generally 8 bits, consistent with ASCII code. Fiber optic data is transmitted in the link in the form of data frames. Each data frame consists of several bytes. The data bytes are divided into start byte, stop byte, and main byte. The start byte is the first byte of the data frame, representing the beginning of the data packet. The stop byte is the last byte of the data frame, representing the end of the data packet. The main byte represents the valid data of the data packet, and the stop bit is 1.

[0016] Furthermore, the frequency following and synchronization in step S2 is as follows: the optical signal input from the fiber optic interface is converted into a 4MHz pulse width modulation signal by the photoelectric conversion module, and then divided to 2MHz by the digital phase-locked loop of the FPGA. The divided signal enters the phase measurement module for phase comparison, and the resulting phase difference is filtered by the Niso II kernel and processed by singular value removal. This phase difference is then used as the input parameter of the PI controller, which uses an algorithm model... The output is then frequency-calibrated by a DA converter module. The voltage signal enters a temperature-controlled crystal oscillator, and the frequency difference is measured using the frequency difference formula based on the phase difference nominal frequency. The frequency shift of the temperature-controlled crystal oscillator can be obtained.

[0017] Furthermore, in step S3, the clock difference θ between the master station (server) and the slave station (client) is expressed by the formula... The calculation is performed, where T1 is the time when the client sends the request, T2 is the time when the server receives the request, T3 is the time when the server responds to the request, T4 is the time when the client receives the server's response, δ1 is the client request path propagation delay, δ2 is the server response path propagation delay, and δ is the total path propagation delay.

[0018] Since the round-trip fiber optic transmission lengths are equal, the client request path propagation delay is approximately equal to the server response path propagation delay. Simplifying the above equation, we get Based on this equation, the total path propagation delay δ and the clock difference θ between the client and the server can be calculated, and the result is: This invention uses Altera's FPGA and ACAM's TDC-GPX chip to measure time intervals, and adds high-precision timestamps to the sending and receiving of messages. Upper-layer applications can obtain the values ​​of T1, T2, T3, and T4 by reading the high-precision timestamps carried in the data frames.

[0019] These timestamps are provided to upper-layer service applications to realize the calculation of fiber optic bidirectional data link delay and clock difference. The calculation of data link delay and clock difference is achieved through bidirectional communication between the master station and the slave station. When the outbound and return data link delays are equal, the clock difference Δ is calculated and transmitted to the second generation module to adjust the local seconds and achieve time synchronization between the master and slave stations.

[0020] The beneficial effects of this invention are:

[0021] Each station of the master and slave stations in this invention has two fiber optic interfaces, one on the left and one on the right, enabling serial or ring topologies for fiber optic links, and supporting "one master, multiple slaves" or "multiple masters, multiple slaves" operating modes. When one fiber in the link fails, the devices in the ring network have the ability to autonomously negotiate priorities, without affecting the normal transmission of time and frequency.

[0022] This invention decodes the original fiber optic signal from the slave station to obtain a 4MHz reference frequency and a high-precision timestamp. It measures the phase difference using a TDC time module, calculates the local isothermal crystal oscillator frequency difference, and performs DA voltage-controlled correction using a PI controller. This enables the fiber optic master station to synchronize with an external high-precision time and frequency reference, providing time synchronization and frequency discipline functions. Time and frequency are transmitted bidirectionally to the slave station via fiber optic cable. The slave station has encoding and decoding capabilities, acquiring the high-precision frequency signal and timestamp information from the fiber optic cable and performing synchronization. By designing the underlying encoding and upper-layer protocol, the invention ensures that the transmission of time and frequency does not affect the interaction of information between stations, achieving synchronized transmission of time, frequency, and messages.

[0023] The bidirectional transmission module and method of this invention can simultaneously achieve stable time and frequency transmission while transmitting data information, realize the establishment of a fiber optic link ring topology, and the failure of a single fiber in the ring network will not affect the time transmission of the overall system, thus not affecting the fiber optic bidirectional synchronization technology for information interaction. Attached Figure Description

[0024] Figure 1 This is a block diagram of the module functions of the present invention;

[0025] Figure 2 This is a block diagram of the network layer partitioning of the present invention;

[0026] Figure 3 This is the software flow of the present invention;

[0027] Figure 4This is the encoding and decoding data flow diagram of the present invention;

[0028] Figure 5 This is the byte definition diagram of the present invention;

[0029] Figure 6 This is a block diagram of fiber optic frequency discipline of the present invention;

[0030] Figure 7 This is a block diagram of the PI controller of the present invention;

[0031] Figure 8 This is a diagram of the time synchronization transmission model of the present invention;

[0032] Figure 9 This is the link control layer data frame format of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0034] Reference Figure 1 As shown, this invention discloses a fiber optic bidirectional transmission module, comprising two fiber optic bidirectional time and frequency transmission module boards based on an FPGA-based TDC (Time-to-Digital Converter), connected by two optical fibers of equal length, serving as a master station and a slave station respectively. The FPGA has a Niso II soft core and a digital phase-locked loop, and the master and slave station functional modules are interchangeable after software configuration. Each transmission module board includes a left photoelectric conversion module, a right photoelectric conversion module, a TDC time measurement module one, and a TDC time measurement module two. Both the left and right photoelectric conversion modules consist of two O / E modules connected in series. One O / E module of the right photoelectric conversion module is connected to an encoding module and one O / E module of the left photoelectric conversion module. The encoding module is connected to a temperature-controlled crystal oscillator, which is connected to the TDC time measurement module two. The other O / E module of the right photoelectric conversion module is connected to a decoding module and the left photoelectric conversion module. Another O / E module connects the decoding module to TDC time measurement module one, which in turn connects to the second generation module. The second generation module is connected to a temperature-controlled crystal oscillator. TDC time measurement modules one and two receive external second and frequency reference signals, respectively. After clock difference and frequency difference measurements, they output seconds and frequency signals via the second generation module and the temperature-controlled crystal oscillator, respectively. The temperature-controlled crystal oscillator simultaneously outputs a 4MHz frequency waveform to the second generation module, the encoding module, and TDC time measurement module two. The left photoelectric conversion module of the slave station acts as an extension terminal, connecting to the right photoelectric conversion module of the master station, and they communicate via optical fiber. This can be expanded to form "one master, multiple slaves" and "multiple master, multiple slaves" links. The master station supports external time and frequency input, transmitting time and frequency references bidirectionally to the slave stations via optical fiber to achieve time reproduction.

[0035] This invention uses an FPGA in conjunction with ACAM's TDC-GPX to measure time intervals and output high-precision timestamps. The upper-layer application is written in the soft core Niso II of Altera's EP4CE115F23I7 FPGA, and information transmission and time and frequency synchronization between ring network sites are completed by establishing a ring network communication protocol.

[0036] This invention discloses a method for stable time and frequency transmission in a fiber optic bidirectional ring network, comprising the following steps:

[0037] S1 divides the fiber optic communication network into four layers, such as... Figure 2 As shown, from lowest to highest, they are the physical layer, encoding and decoding layer, link control layer, and general service layer, each processing the corresponding data stream according to its function.

[0038] In step S1, the network undergoes layered processing; the logic block diagram is shown below. Figure 2 As shown, the functions of each network layer include: 1) Network layer-0 is the physical layer, which includes the transmission of intermediate media, the interface of photoelectric conversion modules, and how receivers and transmitters work; 2) Network layer-1 is the encoding and decoding layer, which mainly converts the high and low level signals of the physical layer into 0 and 1 signals, and converts the byte data from the link control layer into 0 and 1 signals for processing by the physical layer; 3) Network layer-2 is the link control layer, which is mainly responsible for marking the received and transmitted data frames with high-precision timestamps, verifying and extracting received data, and integrating transmitted data frames; 4) Network layer-3 is the general service layer, which mainly includes the forwarding and receiving of data from upper-layer applications. The data format and protocol of upper-layer applications can be freely defined, which facilitates subsequent expansion and improvement.

[0039] S2: Based on the 4MHz frequency waveform transmitted from the physical layer, the local frequency is divided and its phase is compared. A PI controller is used to achieve frequency following and synchronization between the slave station and the master station. This step of frequency following and synchronization between the slave station and the master station involves dividing the 4MHz frequency signal transmitted from the physical layer to 2MHz, and simultaneously dividing the 10MHz frequency signal from the local temperature-controlled crystal oscillator to 2MHz via a PLL. The phase difference between the two signals is measured using a TDC time measurement module, and data filtering is performed to achieve digital phase-locked loop (PLL), ensuring frequency stability between the master and slave stations.

[0040] S3 involves encoding and parsing the data stream in the data link layer. After parsing, high-precision timestamps are used to mark the sending and receiving times of each data packet frame. These timestamps are provided to upper-layer service applications to perform data link delay and clock bias analysis and calculation. This step, fiber optic bidirectional data delay and clock bias calculation, is achieved through bidirectional communication between the master and slave stations. Assuming equal outbound and return data link delays, the clock bias Δ is calculated and transmitted to the seconds generation module to adjust the local seconds, thus achieving time synchronization between the master and slave stations.

[0041] In step S4, the general service layer packages the data information to be sent, the source address, and the destination address, and passes them to the lower layer. The lower layer automatically forwards the information, and the data content can be customized, facilitating subsequent expansion and adjustment of the upper-layer protocol. The custom protocol in this step is to provide a common data interface for upper-layer applications. Upper-layer applications can use the custom protocol to construct the link topology. This patent provides a ring topology construction method that can achieve time and frequency synchronization of all stations within the ring network. In the event of a single fiber optic line failure, the ring network will adaptively switch the master station priority and follow accordingly, ensuring that the overall time of the ring network is not affected.

[0042] Applying this method to a fiber optic bidirectional time and frequency transmission module board yields the following benefits: the master station synchronizes with an external high-precision time and frequency source with a synchronization accuracy on the order of picoseconds. During bidirectional single-level transmission via fiber optics, the slave station can stably follow the master station's frequency, with a time synchronization accuracy better than 150 picoseconds. Through a designed upper-layer protocol, time and frequency synchronization can be achieved within the link, and commands can be freely extended, providing a convenient interface for subsequent development and improvement. When the fiber optic link is closed into a loop, removing any fiber in the link does not affect the transmission of time and frequency, improving the stability of the ring network link.

[0043] This patented method enables time and frequency synchronization across all stations within a ring network. In the event of a single fiber optic line failure, the ring network adaptively switches the master station priority and follows accordingly, ensuring the overall ring network time remains unaffected. The system architecture of this invention is relatively easy to implement, suitable for fiber optic bidirectional time and frequency transmission module boards, and has a low cost. Testing shows that in a two-stage cascade test, the output second pulse accuracy is better than 150 ps; in a five-stage cascade test, the accuracy of comparing the second pulse output from the furthest point with the master station is better than 1 ns. Using simultaneous frequency and time transmission effectively improves the performance of fiber optic bidirectional time synchronization.

[0044] The software flow of this invention is as follows: Figure 3As shown: After the FPGA powers on, it first initializes the initial parameters of each module, converts the data format according to each external interface, buffers the parsed data for fiber optic communication, and generates an interrupt signal from the FPGA to the Niso II program. The Niso II initializes the variables of each interrupt response program in the soft core, reads the initialization information from the EEPROM to distinguish the initial operating mode of the board, responds to interrupts from the FPGA to the Niso II, identifies the interrupt trigger source, and enters different response functions according to different trigger sources. Synchronization processes include: fiber optic transmission processing, fiber optic reception processing, crystal oscillator discipline, and external second synchronization. The key aspects of each part are detailed below.

[0045] (1) Fiber optic data encoding and decoding.

[0046] The standard IRIG-B(DC) code is encoded using pulse width modulation (PWM) and has three code elements. The three pulse widths represent logic "1", logic "0", and the flag bit "P", respectively, with a standard transmission rate of 100 code elements / s. This invention borrows the encoding method of IRIG-B(DC) code, using different pulse widths to represent logic "1" and logic "0". However, due to the relatively low transmission rate of the standard IRIG-B(DC) code, this invention increases the fiber optic transmission rate to 4 Mbps and removes the flag bit "P". The encoded and decoded data streams are as follows: Figure 4 As shown, each symbol duration is 250ns, the pulse width of logic "1" is 100ns, and the pulse width of logic "0" is 200ns.

[0047] The advantages of this approach are: 1) Pulse width modulation can conveniently use the rising edge of the transmitted signal as a disciplining signal to provide a reference for frequency transmission; 2) The larger fiber optic transmission rate increases the communication bandwidth, and removing the flag bit results in more effective data bits, improving data transmission efficiency and information diversity.

[0048] Data is transmitted serially in the fiber optic link in byte form. Each data byte contains 10 bits, including a 1-bit start bit, 8-bit data bits (which can also be set as needed), and 1 stop bit. The flag bits are defined as follows: 1) Start bit: The fiber optic data transmission line maintains a logic "1" signal when idle. When the device sends a logic "0" signal, it indicates the start of data. 2) Stop bit: In the main byte, the stop bit is represented as a logic "1" after the effective data transmission in the fiber optic link is completed. In the start byte and stop byte, the stop bit is represented as a logic "0". 3) Data bits: The width of the data bits is generally 8 bits, consistent with ASCII code, but can also be set according to specific needs.

[0049] Fiber optic data is transmitted in the link in the form of data frames. Each frame consists of several bytes, which are further divided into start bytes, stop bytes, and main bytes. (See reference...) Figure 5 As shown, the definitions of each byte are as follows: 1) Start byte: The first byte of the data frame, representing the beginning of the data packet, represented in binary as 10'b0000000000; 2) Stop byte: The last byte of the data frame, representing the end of the data packet, represented in binary as 10'b0111111110; 3) Valid byte: Represents the valid data of the data packet, with a stop bit of 1, represented in binary as 10'b0101101011 as decimal 181.

[0050] (2) Frequency transmission.

[0051] The fiber optic frequency discipline block diagram is as follows: Figure 6 As shown, the optical signal input through the fiber optic interface is converted into an electrical signal by the photoelectric conversion module. Since the fiber optic signal is a 4MHz pulse width modulation signal, it needs to be divided by two before entering the phase measurement module. The temperature-controlled crystal oscillator has good short-term stability but poor long-term stability, so it needs to be calibrated by a DA conversion module. The temperature-controlled crystal oscillator has a frequency of 10MHz, which is divided to 2MHz by the digital phase-locked loop of the FPGA before finally entering the phase measurement module. Phase comparison is performed, and the phase difference is processed by Niso II filtering and singular value removal before being used as the input parameter of the PI controller. The frequency difference measurement formula is then used. The frequency offset of the thermostatic crystal oscillator can be obtained from the nominal frequency based on the phase difference.

[0052] Mainstream closed-loop automatic control technologies are based on the concept of feedback to reduce uncertainty. Feedback theory comprises three elements: measurement, comparison, and execution. Measurement is crucial; the actual value of the controlled variable is compared with the desired value. This deviation is used to correct the system's response and execute regulatory control. In engineering practice, the most widely used regulator control law is proportional-integral control, or PI control for short.

[0053] A PI controller (proportional-integral controller) is a common feedback loop component in industrial control applications, consisting of a proportional unit (P) and an integral unit (I). The basis of PI control is proportional control; integral control can eliminate steady-state errors. A PI control block diagram is shown below. Figure 7 As shown. In discrete systems, the integral is replaced by accumulation, and the algorithm model is as follows.

[0054] (3) Time synchronization.

[0055] The time synchronization method abandons the traditional approach of using a flag bit as the 1pps rising edge, which is affected by fiber length. This invention compensates for fiber link delay by recording the sending and receiving times of the client and server. The designed transmission model is as follows: Figure 8As shown, T1 is the time when the client sends the request, T2 is the time when the server receives the request, T3 is the time when the server responds to the request, T4 is the time when the client receives the server's response, δ1 is the client request path propagation delay, δ2 is the server response path propagation delay, δ is the total path propagation delay, and θ is the clock difference between the client and the server. Therefore, the equation can be obtained. Since the round-trip fiber optic transmission lengths are equal, the client request path propagation delay is approximately equal to the server response path propagation delay. Simplifying the above equations, we get Based on this equation, the total path propagation delay δ and the clock difference θ between the client and the server can be calculated, and the result is:

[0056] It can be seen that the total path propagation delay δ, the clock difference θ between the client and the server, and (T3-T2) are unrelated, meaning they are unrelated to the time it takes for the server to receive the client's request and then respond. As long as the time for sending and receiving messages back and forth is equal, FPGA is very suitable for completing this type of task.

[0057] This invention uses Altera's FPGA and ACAM's TDC-GPX chip to measure time intervals, giving high-precision timestamps to the sending and receiving of messages. Upper-layer applications can obtain the values ​​of T1, T2, T3, and T4 by reading the high-precision timestamps carried in the data frames.

[0058] (4) Fiber optic data frame design.

[0059] refer to Figure 9As shown, the data frame format of the link control layer includes: start byte, frame header, upper layer transmit or receive data, checksum, and stop byte. The following is a description of each part: 1) Start Byte: Defined as the start byte of the encoding and decoding layer, consisting of 10 bits (10'b0000000000) indicating the start of a data frame; 2) Frame Header: The frame header contains the total length of the data frame, the data transmission timestamp, and the data reception timestamp. The timestamp format is represented by two 6-byte unsigned integers, the former representing the time in seconds and the latter representing the time to date (the number of seconds since January 1, 1970); 3) Upper Layer Data: Data sent or received by the upper layer application. The upper layer application is only responsible for handing over the transmitted data and data length to the link control layer. The frame header, timestamp, and checksum calculation are all automatically completed by the underlying FPGA program, which facilitates the writing of the upper layer application; 4) Checksum: This invention uses cumulative checksum. All bytes from the header to the upper layer data are cumulatively checked, and the checksum is automatically calculated by the underlying FPGA; 5) Stop Byte: Defined as the stop byte of the encoding and decoding layer, consisting of 10 bits (10'b0111111110) indicating the end of a data frame.

[0060] The ring network topology is established.

[0061] A ring network can consist of multiple hosts and slaves. Each host negotiates priorities autonomously based on its own operating status, and slaves select a time source to follow based on their priority. The link can be a single connection or a closed ring. This invention designs a ring network priority topology establishment protocol, with instructions including: topology request instruction (0x00), topology response instruction (0x01), time synchronization request instruction (0x02), and custom extended instructions. The instructions are explained below.

[0062] 1) Topology Request Command (0x00): The master station broadcasts a topology establishment request every second, therefore setting the target address to 0xFF. When other stations receive this command, they will return the current station's status data and continue forwarding the command downwards. If the link is in a loop, the current master station will also receive its own 0x00 command, but at this point, it will stop forwarding the command downwards. When a slave station receives the master station's topology request command, it can resolve the address information and priority of the previous station in the link, which will be used as the basis for time source selection. The specific command format is shown in the table below.

[0063] Data content Number of bytes occupied Specific meaning Source address 1 Target address 1 0xFF Instruction Number 1 0x00 Parent forwarding address 1 Previous level forwarding physical ID 1 upstream forwarding fiber optic port 1 Left: 0, Right: 1 Upper-level time source priority 1

[0064] 2) Topology response command (0x01): When the slave station receives the topology request command, it will return the currently known left and right topology information along the original path. When the master station receives the left and right topology information of all stations in the link, it can complete the construction of the topology of the entire link. At this time, the target address is the master station that sent the request, and the source address is itself. The working status information of the local machine can be customized in the status reporting field.

[0065] The specific command format is shown in the table below.

[0066] Data content Number of bytes occupied Specific meaning Source address 1 Target address 1 Instruction Number 1 0x01 physical ID of the source 1 Source priority 1 The adjacent address on the side receiving the topology message 1 Received topology message side physical ID 1 Received topology message side 1 Left: 0 Right: 1 Adjacency priority of receiving topology messages 1 Adjacent address on the other side 1 Adjacent physical IDs on the other side 1 The other side 1 Left: 0 Right: 1 Adjacent priority on the other side 1 Specific details of status report Length Add according to specific circumstances.

[0067] 3) Time Synchronization Request Command (0x02): After the priority is determined, the slave station can decide on the time source based on the left and right priorities. The time synchronization request command is issued by the slave station. In the protocol, both the client-sent timestamp t1 and the server-received timestamp t2 can be filled with zero. The client-sent timestamp t1 is automatically generated in the underlying FPGA. When an adjacent time source station receives a time synchronization request, the server-received timestamp t2 is automatically generated in the underlying FPGA. The upper-layer application reads t1 and t2, fills in the corresponding bytes of the 0x02 command, and then returns the command along the same path. When sending, timestamp t3 is generated. Finally, after the slave station receives the time synchronization response, timestamp t4 is generated. t1, t2, t3, and t4 can be parsed to calculate the fiber optic line delay and clock bias. The specific command format is shown in the table below.

[0068]

[0069] 4) Custom Extension Commands: Custom extension commands provide users with an extensible framework interface, allowing users to customize command formats according to their own needs and accomplish more complex functions. The basic command formats are shown in the table below.

[0070] Data content Number of bytes occupied Specific meaning Source address 1 Target address 1 Instruction Number 1 0x03 Specific instructions Length

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention, as well as some of the application examples. For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for stable time and frequency transmission in a bidirectional ring network using an optical fiber bidirectional transmission module, characterized in that, The fiber optic bidirectional transmission module includes two FPGA-based TDC (Time Controlled Transmission) module boards connected by two equal-length optical fibers, serving as the master and slave stations respectively. The FPGA features a Niso II core and a digital phase-locked loop. Each transmission module board includes a left photoelectric conversion module, a right photoelectric conversion module, a TDC time measurement module one, and a TDC time measurement module two. The left photoelectric conversion module consists of two O / E modules connected in series, as does the right photoelectric conversion module. One O / E module of the right photoelectric conversion module is connected to both an encoding module and an O / E module of the left photoelectric conversion module. The encoding module is connected to a temperature-controlled crystal oscillator, which is connected to TDC time measurement module two. The other O / E module of the right photoelectric conversion module is connected to both a decoding module and another O / E module of the left photoelectric conversion module. The decoding module is connected to TDC time measurement module one, which is connected to a second generation module, which is also connected to the temperature-controlled crystal oscillator. TDC time measurement module one and TDC time measurement module two receive external second reference signals and external frequency reference signals, respectively. After completing clock difference and frequency difference measurements, they output seconds and frequency through a second generation module and a temperature-controlled crystal oscillator, respectively. The left photoelectric conversion module of the slave station is connected to the right photoelectric conversion module of the master station as an extension terminal, and they communicate via optical fiber. The process includes the following steps: S1, the optical fiber communication network is divided into physical layer, encoding and decoding layer, link control layer and general service layer from low to high; the physical layer includes the interface of the photoelectric conversion module and the master station and slave station transmission and reception modules; the encoding and decoding layer is used to convert the high and low level signals of the physical layer into 0 and 1 signals, and at the same time convert the byte data from the link control layer into 0 and 1 signals and send them to the physical layer for processing; the link control layer is used to mark the received and transmitted data frames with high-precision timestamps, verify and extract the received data, and integrate the transmitted data frames; the general service layer is used for data forwarding and reception. S2, the slave station achieves frequency following and synchronization with the master station. The 4M frequency signal transmitted from the physical layer is divided into a 2M signal, and the 10M frequency signal from the local temperature-controlled crystal oscillator is also divided into 2M by a PLL. The phase difference between the two signals is measured by comparing the phase difference after being divided by the local frequency through the TDC time measurement module, and data filtering is performed to achieve digital phase-locked loop. A PI controller is used to achieve frequency following and synchronization between the slave station and the master station. S3 encodes and parses the data stream in the data link layer. After parsing, it performs high-precision timestamp marking on the sending and receiving times of each data packet frame, providing it to upper-layer service applications. It realizes the calculation of optical fiber bidirectional data link delay and clock difference. The calculation of data link delay and clock difference is achieved through bidirectional communication between the master station and the slave station. When the outbound and return data link delays are equal, the calculated clock difference is transmitted to the second generation module to adjust the local second to achieve time synchronization between the master and slave stations. S4, the general service layer packages the data information to be sent, source address and target address and passes them to the FPGA. The FPGA sends the initial parameters after power-on, the conversion data of each interface and the buffered fiber optic communication parsing data to Niso II, and generates an interrupt signal from the FPGA to Niso II. Niso II responds to the interrupt, identifies the interrupt trigger source, and enters fiber optic transmission processing, fiber optic reception processing, crystal oscillator discipline, or external second synchronization according to different trigger sources.

2. The method for stable time and frequency transmission in a bidirectional ring network of an optical fiber bidirectional transmission module according to claim 1, characterized in that, The encoding and decoding in step S1 adopt the encoding method of IRIG-B code, using pulse widths of 100ns and 200ns to represent logic "1" and logic "0" respectively, with each symbol duration of 250ns. Pulse width modulation encoded data is transmitted serially in the optical fiber link in byte form. Each data byte contains 10 bits, including a 1-bit start bit, 8-bit data bits, and 1 stop bit. The optical fiber data transmission line maintains a logic "1" signal when idle. When the device sends a logic "0" signal, it indicates the start of data. In the formal bytes, the stop bit is represented as a logic "1" after the effective transmission of optical fiber data is completed. In the start byte and stop byte, the stop bit is represented as a logic "0". The data bits use 8-bit data consistent with ASCII code. Optical fiber data is transmitted in the link in the form of data frames. Each data frame consists of several bytes. The start byte is the first byte of the data frame, representing the beginning of the data packet. The stop byte is the last byte of the data frame, representing the end of the data packet. The formal bytes represent the effective data of the data packet.

3. The method for stable time and frequency transmission in a bidirectional ring network of an optical fiber bidirectional transmission module according to claim 1, characterized in that, The frequency tracking and synchronization in step S2 is as follows: The optical signal input from the optical fiber is converted into a 4MHz pulse width modulation signal by the photoelectric conversion module, and then divided to 2MHz by the digital phase-locked loop of the FPGA. The divided signal enters the phase measurement module for phase comparison. The phase difference is then filtered by the Niso II kernel and processed by singular value removal before being used as the input to the PI controller. The PI controller then uses an algorithm model... The output is then frequency-calibrated by a DA converter module. The voltage signal enters a temperature-controlled crystal oscillator, and the frequency difference is measured using the frequency difference formula based on the phase difference nominal frequency. The frequency shift of the thermostatic crystal oscillator is obtained.

4. The method for stable time and frequency transmission in a bidirectional ring network of an optical fiber bidirectional transmission module according to claim 1, characterized in that, In step S3, the clock difference between the master station (server) and the slave station (client) θ Through formula Calculation, where T 1 The time when the client sends the request. T 2 The time when the server receives the request. T 3 The time it takes for the server to respond to a request. T 4 The time it takes for the client to receive the server's response. Delay for client request path propagation. To delay the propagation of the server response path, This represents the total propagation delay along the path. The client request path propagation delay is equal to the server response path propagation delay. Simplifying the equation, we get The total path propagation delay is calculated. and the clock difference between the client and the server θ : ,in T 1 , T 2 , T 3 , T 4 The value is obtained by reading the high-precision timestamp carried in the data frame.

5. The method for stable time and frequency transmission in a bidirectional ring network of an optical fiber bidirectional transmission module according to claim 1, characterized in that, The FPGA uses Altera's EP4CE115F23I7, and the TDC uses the TDC_GPX chip.

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