Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method. The preparation method comprises: forming a peripheral high-voltage circuit in a first region defined on a composite substrate, and covering the first region with a first filling layer; forming a laminated structure on the composite substrate and the first filling layer; removing part of the laminated structure in a boundary region adjacent to the first region to form a groove exposing the composite substrate, and filling the groove with an insulating medium filling layer; and forming a channel structure and a step structure in part of the laminated structure on the side of the filled groove away from the peripheral circuit. Through the preparation method provided by the application, the peripheral high-voltage circuit and the three-dimensional memory array are formed on the same plane of the same substrate, which can effectively reduce the size of the peripheral circuit wafer and improve the storage density of the three-dimensional memory without affecting the performance of the three-dimensional memory structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] Three-dimensional memory (3D memory) can retain stored information for extended periods without power, and it also boasts advantages such as high integration density, fast access speed, and ease of erasure and rewriting. Therefore, it has found widespread application in microcomputers, automation control, and many other fields. To further accelerate the development and application of 3D memory, it is necessary to continuously improve its bit density while simultaneously reducing its bit cost.

[0003] In conventional 3D memory fabrication methods, the memory array structure and peripheral circuit structure are typically formed on two separate wafers. The peripheral circuit wafer is then bonded to the memory array wafer using processes such as bonding to connect the two circuits. However, as 3D memory structures continue to evolve towards higher layer counts and densities, the area of ​​the peripheral circuit wafer is increasingly becoming a critical factor determining the overall chip size.

[0004] Therefore, how to effectively reduce the size of the peripheral circuit wafer without affecting the performance of the three-dimensional memory structure is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a three-dimensional memory and its fabrication method that can at least partially solve the above-mentioned problems existing in related technologies.

[0006] This application provides a method for fabricating a three-dimensional memory, the method comprising: forming a peripheral circuit in a first region defined on a composite substrate, and covering the first region with a first filler layer; forming a stacked structure on the composite substrate and the first filler layer; removing a portion of the stacked structure located in a boundary region adjacent to the first region to form a groove exposing the composite substrate, and filling the groove with an insulating dielectric filler layer; and forming a channel structure and a step structure in the portion of the stacked structure located on the side of the filled groove away from the peripheral circuit.

[0007] In one embodiment of this application, before forming a peripheral circuit in a first region defined on the composite substrate, the method further includes forming the composite substrate, the forming of the composite substrate including: bonding the surface of the first substrate to the surface of a single-crystal silicon layer in silicon-on-insulator; and removing the substrate of the silicon-on-insulator to form the composite substrate including the single-crystal silicon layer and the first substrate.

[0008] In one embodiment of this application, the first substrate includes a substrate, a substrate barrier layer, and a substrate semiconductor layer formed sequentially, the substrate semiconductor layer including a first substrate semiconductor layer and a second substrate semiconductor layer, and the first substrate semiconductor layer is directly opposite the first region and the boundary region. The method further includes, after forming the channel structure,: removing the substrate and the substrate barrier layer, and removing the second substrate semiconductor layer to expose the single-crystal silicon layer and the functional layer of the channel structure; removing the exposed functional layer to expose the channel layer of the corresponding channel structure; and forming conductive layers on the surface of the exposed single-crystal silicon layer that are in contact with the first substrate semiconductor layer and the exposed channel layer, respectively.

[0009] In one embodiment of this application, forming a conductive layer on the surface of the exposed monocrystalline silicon layer that contacts the exposed channel layer and the first substrate semiconductor layer respectively includes: forming an initial conductive layer on the surface of the exposed monocrystalline silicon layer and the surface of the first substrate semiconductor layer, wherein the initial conductive layer contacts the exposed channel layer; removing a portion of the initial conductive layer located on the surface of the first substrate semiconductor layer; and flushing the surface of the first substrate semiconductor layer with the surface of the remaining initial conductive layer to form the conductive layer.

[0010] In one embodiment of this application, the composite substrate includes a first substrate and a second substrate disposed sequentially, wherein a source region, a drain region, and a bias region of the peripheral circuit are formed in the second substrate, and a gate structure of the peripheral circuit is formed on the second substrate. The method further comprises: removing portions of the first substrate corresponding to the source region, the drain region, and the bias region respectively to form a first opening, and filling the first opening with an insulating dielectric layer; forming a second opening exposing a first substrate semiconductor layer in the first substrate, the second opening being directly opposite the gate structure; and filling the second opening with a metal layer to form a voltage control capacitor of the peripheral circuit.

[0011] In one embodiment of this application, forming a peripheral circuit in the first region and covering the first region with a first filling layer includes: forming a shallow trench isolation structure of the peripheral circuit in the first region, wherein the shallow trench isolation structure penetrates the monocrystalline silicon layer and extends into the first substrate; forming a gate structure of the peripheral circuit in the region between the shallow trench isolation structures; forming a source region, a drain region, and a bias region in the portion of the monocrystalline silicon layer located on both sides of the gate structure; and covering the first region with the first filling layer.

[0012] In one embodiment of this application, the memory further includes a gate gap structure, characterized in that conductive impurities located in the source region, the drain region, and the bias region are annealed by the heat generated during the formation of the channel structure, the gate gap structure, and the step structure.

[0013] In one embodiment of this application, after forming the stepped structure, the method further includes forming a peripheral contact in the insulating dielectric filling layer in the boundary region.

[0014] In one embodiment of this application, after forming the channel structure and the step structure, the method further includes: connecting a peripheral circuit chip to the side of the stacked structure away from the composite substrate, wherein the peripheral circuit chip includes any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

[0015] In one embodiment of this application, the peripheral circuit includes any one or a combination of peripheral high-voltage circuit, peripheral low-voltage circuit, and peripheral ultra-low-voltage circuit.

[0016] Another aspect of this application provides a three-dimensional memory, the memory comprising: a substrate; peripheral circuitry disposed on the substrate; a stacked structure disposed on the substrate, including alternately stacked sacrificial layers and gate layers; and a channel structure extending through the stacked structure and into the substrate, wherein a boundary region is provided between the stacked structure and the peripheral circuitry, and the boundary region is filled with an insulating dielectric filling layer.

[0017] In one embodiment of this application, the substrate includes a first part and a second part made of different materials, wherein the peripheral circuit is disposed on the first part and the stacked structure is disposed on the second part.

[0018] In one embodiment of this application, the first portion includes a single-crystal silicon layer of silicon-on-insulator retained by removing the substrate of silicon-on-insulator, wherein the peripheral circuit is directly disposed on the single-crystal silicon layer.

[0019] In one embodiment of this application, the first portion and the second portion are adjacent in a first direction, and the first portion includes the monocrystalline silicon layer, the spacer layer and the voltage control capacitor arranged sequentially along a second direction perpendicular to the first direction.

[0020] In one embodiment of this application, the memory further includes a peripheral circuit chip disposed on the side of the stacked structure away from the composite substrate, wherein the peripheral circuit chip includes any one or a combination of peripheral high voltage circuit, peripheral low voltage circuit and peripheral ultra-low voltage circuit.

[0021] In one embodiment of this application, the peripheral circuit includes any one or a combination of peripheral high-voltage circuit, peripheral low-voltage circuit, and peripheral ultra-low-voltage circuit.

[0022] In one embodiment of this application, the stacked structure is located between the substrate of the peripheral circuit chip and the substrate, and the memory pad leads are located on the side of the substrate away from the stacked structure.

[0023] In one embodiment of this application, the boundary region is located on the first portion or the second portion.

[0024] In one embodiment of this application, the memory further includes: the memory further includes: an insulating dielectric filling layer formed in the boundary region and extending to the peripheral contact of the substrate.

[0025] According to at least one embodiment of the present application, the three-dimensional memory and its fabrication method are provided. By forming the peripheral circuit and the three-dimensional memory array on the same plane, that is, distributing the peripheral circuit on the memory array wafer, the number of peripheral circuits on the peripheral circuit wafer can be reduced without affecting the structural performance of the three-dimensional memory, thereby effectively reducing the size of the peripheral circuit wafer, and thus reducing the overall size of the three-dimensional memory and increasing the storage density of the three-dimensional memory.

[0026] The peripheral circuitry of a 3D memory can include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits. The peripheral high-voltage circuits require thicker substrates and are heat-resistant, thus their fabrication process is easily compatible with that of the 3D memory array. Alternatively, the peripheral high-voltage circuits and the 3D memory array can be formed on the same plane of the same substrate, while a relatively large number of peripheral low-voltage and ultra-low-voltage circuits are placed on the peripheral circuit chip, effectively reducing the overall size of the 3D memory and increasing its storage density. Furthermore, by forming a boundary region filled with an insulating dielectric layer between the peripheral circuits and the 3D memory array located on the same plane, diffusion of substances such as hydrogen or other plasmas generated or used during the fabrication of the 3D memory array into the peripheral circuits can be prevented, thereby improving the reliability of the 3D memory.

[0027] Furthermore, according to at least one embodiment of this application, the three-dimensional memory and its fabrication method provided in this application use an ultrathin single-crystal silicon layer in silicon-on-insulator (SiI) as the substrate for peripheral circuits to improve latch-up effects, short-channel effects, and radiation resistance in peripheral circuits such as high-voltage MOS transistors. Further, in device structures such as MOS transistors fabricated using SiI, by providing a highly doped bias region on the front side of the substrate, its back gate can be led out and polarized, thereby effectively removing parasitic transistors and improving the overall performance of the peripheral circuits.

[0028] Furthermore, according to at least one embodiment of this application, the three-dimensional memory and its fabrication method provided in this application can improve the heat utilization rate of heat treatment and thermal processing during the fabrication of memory devices by annealing the conductive impurities in the source region, drain region and bias region of the peripheral circuit located on the same substrate with the heat generated during the formation of the channel structure, gate gap structure and step structure of the three-dimensional memory array.

[0029] Furthermore, according to at least one embodiment of this application, in the three-dimensional memory and its fabrication method provided in this application, the peripheral circuit also includes an electrical isolation structure (e.g., an insulating dielectric layer in the substrate of the peripheral circuit) that is in contact with the conductive layer of the three-dimensional memory array, so as to improve the electrical reliability of the peripheral high-voltage circuit.

[0030] In addition, according to one embodiment of the present application, a three-dimensional memory and its fabrication method are provided. By setting the peripheral contacts of the three-dimensional memory in the boundary region, the winding between the peripheral circuit and the three-dimensional memory array can be reduced, thereby improving the pressure transmission effect.

[0031] Furthermore, according to one embodiment of the present application, the three-dimensional memory and its fabrication method provide that by forming a voltage-controlled capacitor on the side of the peripheral circuit close to the substrate, the voltage of the peripheral circuit can be effectively controlled, thereby improving the electrical reliability of the peripheral circuit. Attached Figure Description

[0032] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0033] Figure 1 This is a flowchart illustrating a method for fabricating a three-dimensional memory according to one embodiment of this application; and

[0034] Figures 2 to 24 These are schematic diagrams illustrating the preparation method according to one embodiment of this application. Detailed Implementation

[0035] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first part discussed herein may also be referred to as the second part, and the first region may also be referred to as the second region, and vice versa.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0038] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0039] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0042] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to one embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0043] S1, a peripheral circuit is formed in a first region defined on the composite substrate, and a first filling layer is used to cover the first region.

[0044] S2, a stacked structure is formed on the composite substrate and the first filler layer.

[0045] S3, remove the portion of the stacked structure located in the boundary region adjacent to the first region to form a groove that exposes the composite substrate, and fill the groove with an insulating dielectric filling layer.

[0046] S4, a channel structure and a step structure are formed in the portion of the stacked structure located on the side of the filled groove away from the peripheral circuit.

[0047] The following will combine Figures 2 to 24 The specific processes for each step of the above preparation method 1000 are described in detail.

[0048] Step S1

[0049] Figure 2 A cross-sectional schematic diagram of the structure formed after forming the first substrate 101 according to a preparation method according to one embodiment of this application. Figure 3 A cross-sectional schematic diagram of the structure formed by bonding a first substrate 101 with silicon-on-insulator 102' according to one embodiment of the present application. Figure 4 A cross-sectional schematic diagram of the structure formed after forming a composite substrate 100 according to one embodiment of the present application. Figure 5 A cross-sectional view of the structure formed after forming a shallow trench isolation structure 701 for a peripheral high-voltage circuit 700 according to one embodiment of the present application. Figure 6A cross-sectional schematic diagram of the structure formed after forming the peripheral high-voltage circuit 700 according to one embodiment of the present application. Figure 7 A cross-sectional schematic diagram of the structure formed after forming a first filling layer 710 covering the first region 01 according to one embodiment of the present application.

[0050] The following description uses a three-dimensional memory comprising a peripheral high-voltage circuit and a three-dimensional memory array formed on the same plane of a substrate (composite substrate) as an example to illustrate the fabrication process of a three-dimensional memory. However, those skilled in the art should understand that the three-dimensional memory provided in this application includes peripheral circuits and a three-dimensional memory array formed on the same plane. The peripheral circuits may include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits. Therefore, the fabrication process and structure of the three-dimensional memory described below can be fully or partially applied to three-dimensional memories comprising peripheral circuits and a three-dimensional memory array on the same plane, and related or similar content will not be repeated. Figures 2 to 7 As shown, step S1, which involves forming a peripheral high-voltage circuit within a first region defined on the composite substrate and covering the first region with a first filling layer, may include, for example,: preparing a composite substrate 100; forming a peripheral high-voltage circuit 700 within a first region 01 defined on the composite substrate 100; and covering the first region 01 with a first filling layer 710.

[0051] Specifically, in one embodiment of this application, the material used to prepare the composite substrate 100 can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds.

[0052] In one embodiment of this application, the composite substrate 100 for supporting the device structure thereon is formed by sequentially depositing multiple layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0053] like Figure 4 As shown, in one embodiment of this application, the composite substrate 100 may include a first substrate 101 and a substrate 102 for the peripheral high-voltage circuit.

[0054] Specifically, such as Figure 2As shown, the first substrate 101 may include a substrate (not shown) and a substrate sacrificial stack 110 formed on the surface of the substrate. Alternatively, the substrate sacrificial stack 110 may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Furthermore, the substrate sacrificial stack 110 may also include a high-dielectric-constant dielectric layer. Alternatively, the substrate sacrificial stack 110 may include a substrate barrier layer 113, a substrate semiconductor layer 112, and a second barrier layer 111 sequentially disposed, wherein the substrate barrier layer 113 and the second barrier layer 111 may be, for example, silicon oxide layers, and the substrate semiconductor layer 112 may be, for example, a polysilicon layer. Further, a well region formed by doping with an N-type or P-type dopant via ion implantation or diffusion processes may be formed in the substrate semiconductor layer 112. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of this application, the well regions may be prepared using the same dopant or different dopants. Furthermore, the doping concentration of the well regions may be the same or different, and this application does not limit this.

[0055] Furthermore, the substrate barrier layer 113 may be disposed on the surface of the substrate and may include a single layer, multiple layers, or a suitable composite layer. Alternatively, when the substrate barrier layer 113 is a composite layer, it may include any one or more of dielectric materials, semiconductor materials, and conductive materials.

[0056] like Figure 3 As shown, a single-crystal silicon layer, such as that in silicon-on-insulator (SOI), can be selected as the substrate 102 for the peripheral high-voltage circuit. SOI includes a substrate and a single-crystal silicon layer, wherein the substrate may include a relatively thick bulk substrate layer (e.g., a silicon substrate layer) and a relatively thin insulating silicon dioxide interlayer. The substrate primarily serves to provide mechanical support. The single-crystal silicon layer is very thin relative to the substrate and is disposed above the substrate, allowing for the formation of etched circuitry. Using an ultra-thin single-crystal silicon layer in SOI as the substrate 102 for the peripheral high-voltage circuit can improve latch-up effects, short-channel effects, and radiation resistance in peripheral high-voltage circuits such as high-voltage MOS transistors.

[0057] Furthermore, combined Figure 3 and Figure 4 The surface of the single-crystal silicon layer 102 in the silicon-on-insulator 102' can be bonded to the surface of the first substrate 101 using, for example, a bonding process. After forming, for example, a bonding connection, the substrate portion of the silicon-on-insulator 102' can be removed using any suitable etching process (including any one or a combination of dry etching and wet etching processes) to obtain a completely independent single-crystal silicon layer 102, thereby forming the composite substrate 100.

[0058] Three-dimensional memory (3D memory) can include a memory array and peripheral circuitry. The array structure and peripheral circuitry differ and must be manufactured separately. Peripheral circuitry can include high-voltage circuits, low-voltage circuits, and ultra-low-voltage circuits. The fabrication process for high-voltage peripheral circuitry is easily compatible with that of the 3D memory array. Alternatively, the high-voltage peripheral circuitry and the 3D memory array can be formed on the same plane of the same substrate, while a relatively large number of low-voltage and ultra-low-voltage peripheral circuits can be placed on a separate peripheral circuit chip. This effectively reduces the overall size of the 3D memory and increases its storage density. Figure 5 As shown, the composite substrate 100 may include a first region 01 for forming peripheral high-voltage circuitry and a second region 02 for forming a three-dimensional memory array. The second region 02 may specifically include a core region and a step region. In subsequent processes, the channel structure, gate gap structure, etc., of the three-dimensional memory can be formed in the portion of the stacked structure located in the core region, and virtual channels, word line contacts, etc., can be formed in the portion of the stacked structure located in the step region. The core region and the step region are adjacent in a first direction (X direction), and the first region 01 is adjacent to the step region of the second region 02 in the first direction.

[0059] Furthermore, the aforementioned peripheral circuitry may include one or more of page buffers, decoders (e.g., row decoders and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuitry. In some embodiments, the peripheral circuitry may be formed using CMOS technology, but is not limited thereto, and will not be elaborated upon herein.

[0060] like Figures 5 to 6 As shown, in one embodiment of this application, the composite substrate 100 has opposing first and second sides. After the composite substrate 100 is formed, a peripheral high-voltage circuit 700 can be formed within a first region 01 of the composite substrate 100.

[0061] Specifically, the fabrication process of the peripheral high-voltage circuit 700 can employ existing conventional processes, fabricated according to actual needs. A shallow trench isolation structure 701 of the peripheral high-voltage circuit 700 can be formed in the first region 01, wherein the shallow trench isolation structure 701 penetrates the single-crystal silicon layer 102 and extends into the first substrate 101. The shallow trench isolation structure 701 can effectively isolate adjacent devices in the peripheral high-voltage circuit. Subsequently, a gate structure 702 of the peripheral high-voltage circuit 700 can be formed in the region between the shallow trench isolation structures 701. The gate structure 702 includes a gate dielectric layer (not shown) formed in the single-crystal silicon layer 102; a source region 703, a drain region 704, and a bias region 705 are formed in the portions of the single-crystal silicon layer 102 located on both sides of the gate structure 702, respectively.

[0062] As the size of devices such as MOS transistors in peripheral high-voltage circuits decreases, the dimensions of their source, drain, channel, and gate regions also shrink. Therefore, extremely shallow source or drain junctions are required to prevent lateral diffusion of injected dopants into the channel, which could lead to leakage current or poor breakdown performance. Peripheral high-voltage circuits formed on silicon-on-insulator (SOI) can have high-speed shallow junctions, thus reducing parasitic junction capacitance and improving latch-up, short-channel effects, and radiation immunity in peripheral high-voltage circuits such as high-voltage MOS transistors.

[0063] Furthermore, in device structures such as MOS transistors fabricated using silicon-on-insulator (SiI), by setting a highly doped bias region 705 on the front side of the substrate, the back gate can be led out and polarized, thereby effectively removing parasitic transistors and improving the overall performance of the peripheral high-voltage circuit.

[0064] like Figure 7 As shown, after forming the peripheral high-voltage circuit 700, a first filling layer 710 can be prepared to cover the first region 01 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, an initial first filling layer covering the surface of the composite substrate 100 can be formed first using the above process, and then the first filling layer 710 can be formed by removing the portion of the initial first filling layer other than the first region 01. The first filling layer 710 fully covering the first region 01 can prevent plasma gas introduced during the manufacturing process of the three-dimensional memory device from diffusing into the peripheral high-voltage circuit, thereby improving the reliability of the product. Further, the surface of the first filling layer 710 can be planarized. Optionally, the first filling layer 710 can be an insulating dielectric layer such as oxide, nitride, or oxynitride. In addition, the first filling layer 710 can also be a composite structure to better isolate the peripheral high-voltage circuit.

[0065] Step S2

[0066] Figure 8 A cross-sectional schematic diagram of the structure formed after forming an initial stacked structure 200' according to one embodiment of the present application. Figure 9 A cross-sectional schematic diagram of the structure formed after planarization of the initial stacked structure 200' according to one embodiment of the present application.

[0067] like Figures 8 to 9 As shown, step S2, forming a stacked structure on the composite substrate and the first filler layer, may include, for example, forming an initial stacked structure 200' on the surface of the first filler layer 710 and the surface of the second region 02 of the composite substrate 100; and performing a planarization process on the initial stacked structure 200' to form the stacked structure 200.

[0068] Specifically, in one embodiment of this application, such as Figure 8 As shown, after the first filler layer 710 is formed, an initial stacked structure 200' can be formed on the surface of the first filler layer 710 (top and side surfaces) and on the surface of the second region 02 of the composite substrate 100 (the portion of the composite substrate 100 excluding the first region 01). One or more thin film deposition processes can be used to form the initial stacked structure 200' on the aforementioned surfaces. These thin film deposition processes may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, and this application does not limit the specific processes used.

[0069] The initial stack structure 200' may include multiple pairs of insulating layers 210 and gate sacrificial layers 220 stacked alternately. For example, the initial stack structure 200' may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210 and gate sacrificial layers 220. In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may each include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductive layer comprising a conductive material.

[0070] The fabrication method for a single stacked structure has been described above. In fact, with the increasing demand for 3D memory storage, the size of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used to form an initial stacked structure 200' by sequentially stacking multiple sub-stacked structures along the thickness direction of the initial stacked structure 200'. Each sub-stacked structure may include multiple alternately stacked insulating layers and gate sacrificial layers. The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process of the single stacked structure described above is fully or partially applicable to the stacked structure comprising multiple sub-stacked structures described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on multi-stacked or single-stacked structures.

[0071] Combination Figure 8 and Figure 9A planarization process, such as a low-rate chemical mechanical polishing (Buffer CMP), is performed on the surface of the initial stacked structure 200' that is far from the composite substrate 100 to achieve planarization, thereby forming a flat surface 201'. This planarization process makes it easier to maintain consistent heights of portions formed on different surfaces in the initial stacked structure 200', for example, to maintain consistent heights between portions formed on the surface of the first filler layer 710 and portions formed on the surface of the second region 02. This facilitates subsequent processes such as etching on the flat surface 201' to form the stacked structure 200.

[0072] Refer again Figure 8 and Figure 9 After the stacked structure 200 is formed in the second region 02 of the composite substrate 100, a three-dimensional memory array can be formed in the stacked structure 200. The three-dimensional memory array and the peripheral high voltage circuit 700 formed in the first region 01 of the composite substrate 100 (which can be understood as part of the peripheral circuit of the three-dimensional memory array) are formed on the same plane of the same substrate. Without affecting the performance of the three-dimensional memory structure, the number of peripheral circuits on the peripheral circuit wafer can be reduced, thereby effectively reducing the size of the peripheral circuit wafer, and thus reducing the overall size of the three-dimensional memory and increasing the storage density of the three-dimensional memory.

[0073] Step S3

[0074] Figure 10 A cross-sectional schematic diagram of a structure formed after forming a groove 12 in the boundary region 0211 according to a preparation method of one embodiment of this application. Figure 11 A cross-sectional schematic diagram of the structure formed after filling the groove 12 with an insulating dielectric filling layer 13 according to one embodiment of the present application.

[0075] like Figures 10 to 11 As shown, step S3 removes a portion of the stacked structure located in the boundary region adjacent to the first region to form a groove exposing the composite substrate, and fills the groove with an insulating dielectric filling layer. This may include, for example, forming a groove 12 in the boundary region 0211 adjacent to the second region 02 in the first direction; and filling the groove 12 with an insulating dielectric filling layer 13 to separate the peripheral high voltage circuit 700 and the second portion 202 of the stacked structure.

[0076] like Figure 10As shown, the portion of the stacked structure 200 located in the boundary region 0211 can be removed through processes such as dry etching or a combination of dry and wet etching, or other suitable manufacturing processes, until the composite substrate 100 (e.g., the outermost monocrystalline silicon layer 102 in the composite substrate 100 adjacent to the stacked structure 200) is exposed to form the recess 12. The composite substrate 100 may include a first region 01 for forming peripheral high-voltage circuitry and a second region 02 for forming a three-dimensional memory array in subsequent steps, with the first region 01 adjacent to the boundary region 0211 of the second region 02 in a first direction. The recess 12 divides the stacked structure 200 into two parts in the first direction (X direction), a first part 201 and a second part 202, wherein the first part 201 is formed on the first fill layer 710 and faces the peripheral high-voltage circuitry 700.

[0077] like Figure 11 As shown, an insulating dielectric filling layer 13 can be filled in the groove 12 using one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, and this application does not limit the specific processes. The insulating dielectric filling layer 13 may include one or more layers, which may include one or more materials. Materials used for the insulating dielectric filling layer 13 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, etc., and this application does not limit the specific materials used.

[0078] Since multiple heat treatment and thermal processing processes are inevitably used in the subsequent formation of structures such as three-dimensional memory arrays, and plasmas such as hydrogen or others are generated or used, an insulating dielectric filling layer is required in the boundary region between the peripheral high-voltage circuit and the three-dimensional memory array to prevent the plasma from diffusing into the peripheral high-voltage circuit on the same substrate.

[0079] Furthermore, the dimensions of the insulating dielectric filling layer in the first direction (word line direction) or the thickness in the direction perpendicular to the composite substrate 100 can be changed, or the structure of the insulating dielectric filling layer can be changed, for example, forming a composite insulating dielectric filling layer, so that the heat generated by the above heat treatment and heat processing can be uniformly transferred to the peripheral high voltage circuit of the same substrate, and the conductive impurities in the source region, drain region and bias region of the peripheral high voltage circuit can be annealed.

[0080] Step S4

[0081] Figure 12 A cross-sectional schematic diagram of the structure formed after forming the channel structure 300 according to one embodiment of the present application. Figure 13 A cross-sectional schematic diagram of the structure formed after forming the stepped structure 500 according to one embodiment of the present application.

[0082] like Figures 12 to 13 As shown, step S4, which involves forming a channel structure and a step structure in the portion of the stacked structure located on the side of the filled groove away from the peripheral high-voltage circuit, may include, for example, forming a channel structure 300 in the second portion 202 and forming a step structure 500 in the second portion 202.

[0083] Specifically, as an alternative, in one embodiment of this application, the first portion 201 of the stacked structure 200 may be removed, leaving only the second portion 202 of the stacked structure 200, and a three-dimensional memory array (including channel structures and step structures, etc.) may be formed in the second portion 202. Alternatively, in another embodiment of this application, the first portion 201 of the stacked structure 200 may not be removed, but may be used as a stacked capacitor for use in a three-dimensional memory. Simultaneously, a three-dimensional memory array (including channel structures and step structures, etc.) may be formed in the second portion 202 of the stacked structure 200.

[0084] like Figure 12 and Figure 13 As shown, a three-dimensional memory array is formed in a second region 02, which may specifically include a core region 022 and a step region 021. A channel structure 300, gate gap structure, etc., of the three-dimensional memory can be formed in the core region 022, and a step structure 500, virtual channels, and word line contacts can be formed in the step region 021. The core region 022 and the step region 021 are adjacent in a first direction (X direction), and the first region 01 is adjacent to the step region 021 of the second region 02 in the first direction. A boundary region 0211 is located in the step region 021 and is adjacent to the first region 01.

[0085] The channel hole can be formed first in the second part 202 by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing. The channel hole can have a cylindrical or columnar shape that extends through the second part 202 and into the composite substrate 100.

[0086] Furthermore, after forming a stacked structure using dual-stack or multi-stack technology, the stacked structure may include N sub-stacked structures, and correspondingly, the channel holes may also include N×M sub-channel holes, wherein each sub-stacked structure may include M sub-channel holes, where M≥1 and N≥2. Forming vias in the second part of a stacked structure using a dual-stack or multi-stack technique may include: forming a first sub-stacked structure on one side of an initial composite substrate and forming M first sub-channels extending through the first sub-stacked structure and into the initial composite substrate; continuing to form subsequent sub-stacked structures and sub-channels until an Nth sub-stacked structure and M sub-channels located in the Nth sub-stacked structure are formed; then filling the corresponding sub-channels in the N-1 sub-stacked structures other than the Nth sub-stacked structure with a via-filling sacrificial layer; and removing the via-filling sacrificial layer in the N-1 sub-stacked structures based on the M sub-channels of the Nth sub-stacked structure, such that adjacent sub-channels in the N sub-stacked structures are at least partially aligned with each other to obtain M vias.

[0087] After being formed in the channel hole, a channel structure 300 can be formed in the channel hole: a channel structure 300 including a functional layer 320 and a channel layer 330 is formed sequentially in the channel hole, wherein the functional layer 320 includes a barrier layer, a charge trapping layer and a tunneling layer sequentially disposed in the channel hole; and a channel plug and a filling medium layer are formed in the channel hole.

[0088] In one embodiment of this application, a barrier layer, a charge trapping layer and a tunneling layer may be sequentially formed on the inner wall of the channel hole, and a channel layer 330 may be formed on the surface of the tunneling layer.

[0089] The functional layer 320 and the channel layer 330 can be formed in the channel holes by thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0090] Specifically, functional layer 320 may include a barrier layer that blocks charge outflow, a charge trapping layer formed on the surface of the barrier layer to store charge during operation of the three-dimensional memory, and a tunneling layer formed on the surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or other wide-bandgap materials. The charge trapping layer may include one or more layers, which may include one or more materials. Materials for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, or other wide-bandgap materials. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or other wide-bandgap materials.

[0091] In some embodiments, functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, functional layer 320 may have a structure different from the ONO configuration. For example, functional layer 320 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0092] The channel layer 330 can be used to transport the required charge (electrons or holes). According to an exemplary embodiment of this application, the channel layer 330 can be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0093] In some embodiments, the channel layer 330 may comprise silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 330 includes, but is not limited to, p-type doped polycrystalline silicon. Similar to the channel via 310, the channel layer 330 also extends through the stacked structure 200 and into the composite substrate 100.

[0094] In one embodiment of this application, a substrate sacrificial stack 110 (e.g., including a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer 330) penetrates the second portion 202 and extends to the composite substrate 100. Figure 2 As shown in the figure.

[0095] like Figure 13 As shown, forming a step region 500 in the second portion 202 can be achieved by performing multiple "trimming-etching" cycles on the edge portions of the second portion 202 (e.g., step region 021) to give the second portion 202 one or more sloping edges and a dielectric layer pair (e.g., near the bottom, close to the composite substrate 100) with a greater slope than the bottom (closer to the composite substrate 100). Figure 8The insulating layer 210 and gate sacrificial layer 220 shown are shorter at the top (away from the composite substrate 100) of the dielectric layer pair. Any suitable etching process (including any combination of dry and wet etching processes) can be used in the step formation process. Furthermore, a dielectric layer may be formed to cover the step. The step region 500 of the second portion 202 may be formed in an edge portion (step region 021) on the side closest to the peripheral high-voltage circuit 700.

[0096] Combination Figure 12 and Figure 13 The applicant may choose not to remove the first portion 201, or may choose to remove the first portion 201. When choosing to remove the first portion 201, in some embodiments of this application, the first portion 201 may be removed after the step area 500 is formed; in some other embodiments, the first portion 201 may be removed before the step area 500 is formed; or, in some other embodiments, the first portion 201 may be removed simultaneously during the process of forming the step structure 500. This application does not limit this.

[0097] Specifically, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove the first portion 201 until the top surface of the first filling layer 710 of the peripheral high voltage circuit 700 is exposed.

[0098] Figure 14 A cross-sectional schematic diagram of the structure formed after forming the gate gap structure 400 and the gate layer 230 according to one embodiment of the present application.

[0099] After forming the step structure 500, the method for fabricating the three-dimensional memory provided in this application further includes: forming a gate gap structure 400 with a spacing from the channel structure 300 in the second part 202; forming a gate layer 230; and annealing conductive impurities located in the source region 703, drain region 704 and bias region 705 in the peripheral high voltage circuit by using the heat generated during the formation of the channel structure 300, gate gap structure 400 and step structure 500.

[0100] Specifically, the stepped structure 500 also includes a virtual channel structure 600, which provides structural support for the removal of the gate sacrificial layer during the subsequent formation of the gate layer. Its formation process is similar to that of the channel structure 300, and will not be described in detail here.

[0101] like Figure 14 As shown, after the channel structure 300 and the step structure 500 are formed, a gate gap 410 with a spacing from the channel structure 300 in the first direction (X direction) can be formed in the second part 202.

[0102] The gate gap 410 extends through the second portion 202 and into the composite substrate 100 in a direction perpendicular to the composite substrate 100. The gate gap 410 can be formed, for example, by a dry etching process or a combination of dry and wet etching processes.

[0103] Furthermore, the gate gap 410 can be used as a pathway to provide etchant and chemical precursors, and processes such as wet etching can be used to remove all of the gate sacrificial layer 220 in the second part 202 (e.g., Figure 8 (As shown) to form a sacrificial gap.

[0104] After the sacrificial gap is formed, a gate layer 230 can be formed in the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 can be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0105] Furthermore, prior to forming the gate layer 230, the method 1000 for fabricating a three-dimensional memory according to one embodiment of this application further includes forming a dielectric layer (not shown) on the inner wall of the sacrificial gap and on the inner sidewall of the gate gap 410 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Alternatively, the dielectric layer may be a high-dielectric-constant dielectric layer. Further, an adhesive layer (e.g., a titanium nitride (TiN) layer, not shown) may be formed between the insulating layer 210 and the gate layer 230 or between the dielectric layer and the gate layer 230 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0106] The gate layer 230 may extend laterally (perpendicular to the thickness direction of the stack structure 200) as a word line and terminate at one or more step structures 500 of the stack structure 200.

[0107] Furthermore, in some embodiments of this application, after forming the gate layer 230, a gate gap structure 400 can also be formed by filling the gate gap 410. Specifically, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the gate gap 410 with a dielectric layer to form the gate gap structure 400.

[0108] like Figure 6 and Figure 14As shown, in the method 1000 for fabricating a three-dimensional memory provided in this application, the formation of the channel structure 300, gate gap structure 400, and step structure 500 (including the virtual channel structure) on one side of the composite substrate 100 requires extensive heat treatment and thermal processing, such as deep-hole etching processes for forming channel holes, gate gaps, and virtual channel holes. Furthermore, in the peripheral high-voltage circuit 700 formed on the other side of the composite substrate 100, conductive impurities in the source region 703, drain region 704, and bias region 705 require rapid thermal annealing to achieve thermal activation and repair. Therefore, through the isolation structure between the three-dimensional memory array and the peripheral high-voltage circuit, the heat generated by the aforementioned heat treatment and thermal processing can be transferred to the peripheral high-voltage circuit on the same substrate, and the conductive impurities in the source region, drain region, and bias region can be annealed. Furthermore, the dimensions of the isolation structure in the first direction (word line direction) or its height in the direction perpendicular to the composite substrate 100 can be changed to allow the aforementioned heat to be transferred more uniformly to the peripheral high-voltage circuit on the same substrate.

[0109] Figure 15 A cross-sectional view of a structure formed after connecting a peripheral circuit chip 3000 to the side of the stacked structure 200 away from the composite substrate 100, according to one embodiment of the present application.

[0110] like Figure 15 As shown, the method 1000 for fabricating a three-dimensional memory further includes forming a word line contact 171 electrically connected to the gate layer 230 in the stacked structure 200; and forming a peripheral contact 172 in the stacked structure 200 that forms an ohmic contact with the well layer of the composite substrate 100.

[0111] Specifically, after forming the gate line slot structure 400, openings for the peripheral contact 172 and word line contact 171 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, wherein the openings for the word line contact 171 can be formed in the step structure 500, and the openings for the peripheral contact 172 can be formed in the boundary region 0211.

[0112] The openings for the peripheral contact 172 and the word line contact 171 are then filled with a conductive material using CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material forming the peripheral contact 172 and the word line contact 171 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when preparing the peripheral contact and the word line contact, a layer of conductive material (e.g., titanium nitride TiN) may be deposited as a contact layer before depositing another conductive material.

[0113] Furthermore, openings for vias can be formed using a dry etching process or a combination of dry and wet etching processes. Some vias are configured for peripheral contacts 172 and word line contacts 171. Other vias are configured for each bit line contact, which electrically contacts the upper end of the corresponding memory cell and individually addresses the corresponding memory cell. Similar to the via formation process, openings can be fabricated and then filled to form contacts used for interconnection with peripheral devices. These contacts are electrically connected to the aforementioned vias. After forming the interconnect contacts, peripheral circuit chips can be connected to the side of the stacked structure 200 away from the composite substrate 100.

[0114] According to one embodiment of the present application, a method for fabricating a three-dimensional memory can reduce the winding between the peripheral high-voltage circuit and the three-dimensional memory array by setting the peripheral contacts of the three-dimensional memory in the boundary region, thereby improving the pressure transmission effect.

[0115] Figure 16 A cross-sectional schematic diagram of the structure formed after removing the substrate from the composite substrate 100 according to one embodiment of the present application. Figure 17 A cross-sectional schematic diagram of the structure formed after removing part of the substrate barrier layer 113 according to one embodiment of the present application. Figure 18 A cross-sectional schematic diagram of the structure formed after removing a portion of the substrate semiconductor layer 112 according to one embodiment of the present application. Figure 19 A cross-sectional schematic diagram of the structure formed after removing the portion other than the first substrate stack 110' and the partially exposed functional layer 320 according to an embodiment of this application. Figure 20 A cross-sectional schematic diagram of the structure formed after forming the initial conductive layer 120' according to one embodiment of the present application. Figure 21 A cross-sectional schematic diagram of the structure formed after forming the conductive layer 120 according to one embodiment of the present application.

[0116] like Figures 15 to 21 As shown, a method 1000 for fabricating a three-dimensional memory according to one embodiment of this application further includes: connecting a peripheral circuit chip 3000 to the side of the stacked structure 200 away from the composite substrate 100; removing the substrate of the composite substrate 100 and removing a portion of the substrate sacrificial stack 110 to retain a first substrate stack 110', wherein the first substrate stack 110' includes a first substrate semiconductor layer 112' and exposes a single-crystal silicon layer 102 and a functional layer 320; removing the exposed functional layer 320 to expose a corresponding channel layer 330; doping the exposed channel layer 330; and forming a conductive layer 120 on the surface of the exposed single-crystal silicon layer 102 that contacts the first substrate semiconductor layer 112' and the exposed channel layer 330, respectively.

[0117] Refer again Figure 15 After forming interconnect contacts, peripheral circuit chips 3000 can be connected to the side of the stacked structure 200 away from the composite substrate 100. Peripheral circuit chips 3000 may include peripheral low-voltage circuits and peripheral ultra-low-voltage circuits. However, those skilled in the art should understand that the peripheral circuit chips of the three-dimensional memory and its fabrication method provided in this application may include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits. In other words, the three-dimensional memory and its fabrication method provided in this application divide the peripheral circuit of the three-dimensional memory into two parts: one part is formed on the same plane as the three-dimensional memory array on the same substrate, and the other part is disposed on the peripheral circuit chip and bonded to the memory array wafer where the three-dimensional memory array is located through processes such as bonding, thereby reducing the overall size of the three-dimensional memory and increasing its storage density.

[0118] As an alternative, the substrate required for the peripheral high-voltage circuit is relatively thick and resistant to high temperatures, and its fabrication process is easily compatible with the fabrication process of three-dimensional memory arrays. The peripheral high-voltage circuit and the three-dimensional memory array can be formed on the same plane, while the relatively large number of peripheral low-voltage circuits and peripheral ultra-low-voltage circuits are placed on the peripheral circuit chip.

[0119] In addition, in one embodiment of this application, the pad leads of the three-dimensional memory may be disposed on the side of the composite substrate 100 away from the stacked structure 200, which will be described in detail in the subsequent process section below.

[0120] Specifically, the peripheral circuit chip 3000 can be placed above the top surface of the memory device where contacts are provided. Then, an alignment step is performed and one surface of the peripheral circuit chip 3000 is bonded to the top surface of the stacked structure 200 by, for example, a bonding process.

[0121] By forming the peripheral high-voltage circuitry and the three-dimensional memory array on the same plane of the same substrate, and placing the peripheral low-voltage circuitry and peripheral ultra-low-voltage circuitry on another chip, the overall size of the peripheral chips can be relatively reduced, thereby improving the storage density and integrability of the three-dimensional memory.

[0122] Figure 16 To be Figure 15 A cross-sectional view of the structure formed after the structure is flipped 180° and the substrate in the composite substrate 100 is removed. (See diagram below.) Figure 16As shown, a portion of the composite substrate 100, such as the outermost part of the composite substrate 100 and the substrate away from the stacked structure 200, can be removed by means of, for example, chemical mechanical polishing (CMP), dry etching, or a combination of dry and wet etching processes, to expose the substrate barrier layer 113 in the composite substrate 100.

[0123] like Figure 17 As shown, furthermore, processes such as Chemical Mechanical Polishing (CMP), dry etching, or a combination of dry and wet etching can be used to continue removing portions of the composite substrate 100. In one embodiment of this application, the composite substrate 100 includes a substrate sacrificial stack 110 (e.g., Figure 2 As shown), the substrate sacrificial stack 110 includes a substrate barrier layer 113 formed on the substrate (e.g., ...). Figure 2 As shown, the above-described process can be used to remove part of the substrate barrier layer 113, while retaining at least its portion located in the first region 01. Alternatively, a portion of the substrate barrier layer 113' facing the first region 01 and the boundary region 0211 can be retained. The portion of the substrate barrier layer 113' can then work together with the insulating dielectric filling layer of the boundary region 0211 to protect the peripheral high-voltage circuit 700 in subsequent steps.

[0124] like Figure 18 As shown, furthermore, processes such as Chemical Mechanical Polishing (CMP), dry etching, or a combination of dry and wet etching can be used to continue removing portions of the composite substrate 100. In one embodiment of this application, the composite substrate 100 includes a substrate sacrificial stack 110 (e.g., Figure 2 As shown), the substrate sacrificial stack 110 includes a substrate barrier layer 113 (as shown). Figure 2 The substrate semiconductor layer 112 (as shown) on the substrate semiconductor layer 112 Figure 2 As shown, the substrate semiconductor layer 112 includes a first substrate semiconductor layer 112' and a second substrate semiconductor layer, wherein the first substrate semiconductor layer 112' faces the first region 01 and the boundary region 0211. The second substrate semiconductor layer can be removed using the process described above, and at least the first substrate semiconductor layer 112' is located in a portion of the first region 01. Alternatively, the first substrate semiconductor layer 112' may have the same extension length as a portion of the substrate barrier layer 113'.

[0125] Combination Figure 4 and Figure 19As shown, processes such as Chemical Mechanical Polishing (CMP), dry etching, or a combination of dry and wet etching can be used to further remove portions of the composite substrate 100. In one embodiment of this application, the composite substrate 100 includes a substrate sacrificial stack 110, which includes a second barrier layer 111, a substrate semiconductor layer 112, and a substrate barrier layer 113. The aforementioned processes can be used to remove portions of the substrate barrier layer 113, retaining the portion 113' located in the first region 01 and the boundary region 0211. Alternatively, portions of the substrate barrier layer 113' and the first substrate semiconductor layer 112' may have the same extension length as portions of the second barrier layer 111'.

[0126] Through the above steps, the substrate sacrificial stack 110 is preserved (e.g. Figure 2 The first substrate stack 110' located in the first region 01 and the boundary region 0211 (as shown) further exposes the single crystal silicon layer 102 and the functional layer 320 while forming the retained first substrate stack 110'.

[0127] The first substrate stack 110' faces the peripheral high voltage circuit 700 and the insulating dielectric filling layer 13, and can thus protect the peripheral high voltage circuit 700 together with the insulating dielectric filling layer 13 in subsequent steps. For example, it can prevent conductive impurities in the subsequently formed conductive layer from entering the peripheral high voltage circuit 700.

[0128] Furthermore, such as Figure 20 As shown, processes such as chemical mechanical polishing (CMP), dry etching, or a combination of dry and wet etching can be used to remove the exposed functional layer 320 to expose the corresponding 330.

[0129] Specifically, the exposed functional layer 320 can be removed to expose the channel layer 330 by employing multiple, for example, dry etching processes or a combination of dry and wet etching processes. In other words, the barrier layer, charge trapping layer, and tunneling layer of the exposed functional layer 320 can be removed sequentially by employing multiple, for example, dry etching processes or a combination of dry and wet etching processes until a portion of the channel layer 330 is exposed.

[0130] In some embodiments, the functional layer 320, which includes a barrier layer, a charge storage layer, and a tunneling layer, may have an oxide-nitride-oxide (ONO) structure surrounding the channel layer 330. An ONO removal process may be performed to sequentially remove each layer in the exposed functional layer 320 until a portion of the channel layer 330 is exposed.

[0131] In addition, during the process of removing the exposed functional layer 320, the outermost portion of the substrate barrier layer 113' located in the first substrate stack 110' will also be removed, thereby exposing the first substrate semiconductor layer 112'.

[0132] Combination Figure 19 and Figure 20 After exposing the single-crystal silicon layer 102 and the channel layer 330, a conductive layer 120 can be formed on the surface of the exposed single-crystal silicon layer 102, which is in contact with the first substrate semiconductor layer 112' and the exposed channel layer 330, respectively.

[0133] Specifically, an initial conductive layer 120' can be formed on the surface of the exposed single-crystal silicon layer 102 and the surface of the first substrate semiconductor layer 112', wherein the initial conductive layer 120' is in contact with the exposed channel layer 330. The initial conductive layer 120' can be formed using thin film deposition processes such as any one or any combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and metal-organic chemical vapor deposition (MOCVD).

[0134] Alternatively, the initial conductive layer 120' can be a composite structure formed by multiple thin film deposition processes and other processes, such as a composite structure formed by a semiconductor layer encapsulating an insulating layer.

[0135] Alternatively, the initial conductive layer 120' may also be a highly doped semiconductor layer formed using any one or a combination of processes including chemical vapor deposition, physical vapor deposition, atomic layer deposition, and metal-organic chemical vapor deposition. The semiconductor layer may be doped with any suitable, for example, N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Further, the initial conductive layer 120' may be a polycrystalline silicon layer doped with, for example, an N-type dopant (e.g., P, Ar, or Sb).

[0136] like Figure 21 As shown, a portion of the initial conductive layer 120' located on the surface of the first substrate semiconductor layer 112' can be removed using, for example, photolithography, dry etching, or a combination of dry and wet etching processes, or other suitable manufacturing processes can be performed; and the surface of the remaining initial conductive layer 120' can be treated with, for example, a low-rate chemical mechanical polishing process (Buffer CMP) to make the surface of the first substrate semiconductor layer 112' flush with the surface of the remaining initial conductive layer 120', thereby forming the conductive layer 120.

[0137] Furthermore, in one embodiment of this application, to achieve a good and stable electrical connection between the channel layer 330 and the conductive layer 120, thereby improving the electrical performance of the three-dimensional memory, the exposed channel layer 330 can be heavily doped again before the step of forming the initial conductive layer 120. The exposed channel layer 330 can be doped, for example, by a process such as ion implantation (IMP). The aforementioned N-type doping can include any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Figure 21 As shown, after the exposed channel layer 330 is highly doped again, the channel layer 330 may include a first channel layer 331 formed by a secondary doping process.

[0138] Figure 22 A cross-sectional schematic diagram of the structure formed after forming the conductive layer 120 according to one embodiment of the present application.

[0139] like Figure 4 , Figures 22 to 24 As shown, in one embodiment of this application, the method 1000 for fabricating a three-dimensional memory further includes a voltage-controlled capacitor for forming a peripheral circuit. For example, the composite substrate 100 includes a first substrate 101 and a second substrate 102 (the second substrate 102 may be, for example, the single-crystal silicon layer mentioned above) disposed sequentially. A source region 703, a drain region 704, and a bias region 705 of a peripheral high-voltage circuit 700 are formed in the second substrate 102, and a gate structure 702 of the peripheral high-voltage circuit 700 is formed on the second substrate 102. The voltage-controlled capacitor for forming the peripheral circuit may include: removing portions of the first substrate 101 corresponding to the source region 703, the drain region 704, and the bias region 705 respectively to form a first opening 14, and filling the first opening 14 with an insulating dielectric layer 15; forming a second opening (not shown) exposing a first substrate semiconductor layer (e.g., the first substrate semiconductor layer 112') in the first substrate 101, the second opening facing the gate structure 702; and filling the second opening with a metal layer 16 to form a voltage-controlled capacitor 706 for the peripheral circuit.

[0140] Specifically, in one embodiment of this application, portions of the first substrate semiconductor layer 112' corresponding to the source region 703, drain region 704, and bias region 705 of the peripheral high-voltage circuit 700 are removed to form a first opening 14, and the first opening 14 is filled with an insulating dielectric layer 15; an insulating support layer 130 is formed on the surface of the conductive layer 120 and on the filled first opening 14; and the portion of the insulating support layer 130 facing the gate structure 702 of the peripheral high-voltage circuit 700 is removed to form a second opening exposing the first substrate semiconductor layer 112'; the second opening is filled with a metal layer 16 to form a voltage control capacitor 706 of the peripheral high-voltage circuit 700.

[0141] like Figure 22 As shown, in one embodiment of this application, a first opening 14 may be formed by removing portions of the first substrate semiconductor layer 112' that correspond to the source region 703, drain region 704, and bias region 705 of the peripheral high-voltage circuit 700, respectively. The first opening 14 may expose a portion of the second barrier layer 111'.

[0142] like Figure 23 As shown, one or more thin film deposition processes can be used in the first opening 14 (e.g. Figure 22 The thin film deposition process (shown) is filled with an insulating dielectric layer 15. This process can include, but is not limited to, CVD, PVD, ALD, or any combination thereof, and is not limited thereto in this application. The insulating dielectric layer 15 may include one or more layers, which may include one or more materials. Materials used for the insulating dielectric layer 15 may include silicon oxide, silicon nitride, silicon oxynitride, high-K dielectric materials such as aluminum oxide or hafnium oxide, etc., and are not limited thereto in this application.

[0143] Furthermore, an insulating support layer 130 may be formed on the surface of the conductive layer 120, the surface of the remaining first substrate semiconductor layer 112', and the filled first opening 14. The insulating support layer 130 may be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Alternatively, the insulating support layer 130 may be prepared from an insulating material such as an oxide, for example, silicon oxide. Furthermore, the insulating support layer 130 may be treated with, for example, a low-rate chemical mechanical polishing process (buffered CMP) to facilitate the subsequent formation of a metal layer with good contact.

[0144] like Figure 24 As shown, a portion of the insulating support layer 130 facing the gate structure 702 of the peripheral high-voltage circuit 700 can be removed using, for example, photolithography, dry etching, or a combination of dry and wet etching processes, or other suitable manufacturing processes, to form a second opening exposing the first substrate semiconductor layer 112'. Alternatively, a well region formed by doping with N-type or P-type dopant via ion implantation or diffusion processes can be formed in the substrate semiconductor layer 112. Thus, the first substrate semiconductor layer 112' can have a certain concentration of conductive impurities. A metal layer 16 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to fill the second opening, thereby forming the first contact 707 of the peripheral high-voltage circuit 700. The metal layer 16 can be selected from, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc.

[0145] The final three-dimensional memory structure also includes a source contact 132 that is away from the stacked structure 200 and in contact with the conductive layer 120, and a contact 142 that is in contact with the peripheral contact 172.

[0146] Each contact 142 may include one or more metal layers (e.g., tungsten (W), cobalt (Co), copper (Cu), aluminum (Al)) or adhesive layers (e.g., titanium nitride (TiN)). Additionally, each contact 142 may include a spacer layer (e.g., a dielectric layer) to insulate the contact 142 from the conductive layer 120.

[0147] The source contact 132 may include one or more conductive layers, such as metal layers (e.g., tungsten (W), cobalt (Co), copper (Cu), aluminum (Al)) or adhesive layers (e.g., titanium nitride (TiN)).

[0148] Alternatively, while filling the second opening with metal layer 16 to form the first contact 707, the source contact 132 of the three-dimensional memory and the contact 142 that contacts the peripheral contact 172 can be formed.

[0149] Refer again Figure 24 After the second opening is filled with metal layer 16, the gate structure 702 of the peripheral high voltage circuit 700, the metal layer 16 filled in the opening 15, and the dielectric layer (insulating dielectric layer 15 and part of the second barrier layer 111') located between them constitute the voltage control capacitor 706 of the peripheral high voltage circuit 700.

[0150] According to one embodiment of the present application, a method for fabricating a three-dimensional memory is provided. By forming a voltage control capacitor on the side of the peripheral high-voltage circuit close to the substrate, the voltage of the peripheral high-voltage circuit can be effectively controlled, thereby improving the electrical reliability of the peripheral high-voltage circuit.

[0151] like Figure 24 As shown, another aspect of this application provides a three-dimensional memory 2000. This three-dimensional memory 2000 can be fabricated using any of the above-described fabrication methods. The three-dimensional memory 2000 may include: a substrate 100', peripheral circuitry 700 (optionally, it may be peripheral high-voltage circuitry 700), a stacked structure 200, and a channel structure 300, wherein the stacked structure 200 and the peripheral circuitry 700 are both disposed on the substrate 100', and a boundary region 0211 is provided between them, the boundary region 0211 being filled with an insulating dielectric filling layer 13. The stacked structure 200 includes alternately stacked gate layers 230 and insulating layers 210.

[0152] Alternatively, the peripheral circuitry 700 may be disposed within a first region 01 of the substrate 100' and covered by a first filler layer 710. The stacked structure 200 may be disposed within a second region 02 of the substrate 100'. The boundary region 0211 of the second region 02 is adjacent to the first region 01.

[0153] According to one embodiment of the present application, a three-dimensional memory is provided. By forming the peripheral circuitry and the three-dimensional memory array on the same plane of the same substrate, the size of the peripheral circuitry wafer can be effectively reduced, thereby increasing the storage density of the three-dimensional memory without affecting its structural performance. Furthermore, by forming a boundary region filled with an insulating dielectric layer between the peripheral circuitry and the three-dimensional memory array, the diffusion of substances such as hydrogen or other plasmas generated or used during the fabrication of the three-dimensional memory array into the peripheral circuitry can be prevented, thereby improving the reliability of the three-dimensional memory.

[0154] The peripheral circuitry of a 3D memory can include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits. The peripheral high-voltage circuits require thicker substrates and are heat-resistant; therefore, their fabrication process is easily compatible with that of the 3D memory array. Alternatively, the peripheral high-voltage circuits and the 3D memory array can be formed on the same plane of the same substrate, while a relatively large number of peripheral low-voltage and ultra-low-voltage circuits can be placed on a peripheral circuit chip. This effectively reduces the overall size of the 3D memory and increases its storage density.

[0155] However, those skilled in the art should understand that the three-dimensional memory provided in this application includes peripheral circuitry and a three-dimensional memory array formed on the same plane. The peripheral circuitry may include any one or a combination of peripheral high-voltage circuitry, peripheral low-voltage circuitry, and peripheral ultra-low-voltage circuitry. This application only uses the peripheral high-voltage circuitry and the three-dimensional memory array disposed on the same plane as an example to describe the structure and fabrication process of the three-dimensional memory, and does not limit the number, type, or specific structure of the aforementioned peripheral circuitry disposed on the same plane.

[0156] In other words, the peripheral circuitry of the three-dimensional memory provided in this application may include any one or a combination of peripheral high-voltage circuitry, peripheral low-voltage circuitry, and peripheral ultra-low-voltage circuitry. In the three-dimensional memory provided in at least one embodiment of this application, the substrate 100' includes a first part and a second part made of different materials, such as a first region 01 and a second region 02 of the substrate 100'. Furthermore, as an option, the first part and the second part may be adjacent in a first direction (X direction). In addition, the peripheral circuitry of the three-dimensional memory may also be divided into two parts, one part of which may be formed on the same plane of the same substrate as the three-dimensional memory array. For example, a part of the peripheral circuitry (e.g., peripheral circuitry 700) may be disposed on the first part of the substrate 100', while the stacked structure 200 (including the three-dimensional memory array) may be disposed on the second part of the substrate 100'. At the same time, the other part of the peripheral circuitry may be disposed on the peripheral circuitry chip and bonded to the memory array wafer where the three-dimensional memory array is located through a bonding process, thereby reducing the overall size of the three-dimensional memory and increasing the storage density of the three-dimensional memory.

[0157] Therefore, in one embodiment of this application, the three-dimensional memory 2000 further includes a peripheral circuit chip 3000 disposed on the side of the stacked structure 200 away from the substrate 100'. The peripheral circuit chip 3000 includes any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

[0158] Furthermore, in one embodiment of this application, the boundary region 0211 is disposed in the second region 02 and adjacent to the first region 01. Therefore, in this embodiment, the boundary region 0211 may be made of the same material as the first portion of the substrate 100' that forms the stacked structure 200 (including the three-dimensional memory array). Alternatively, the boundary region may be disposed in the first region and adjacent to the second region. The boundary region may be made of the same material as the second portion of the substrate that forms the peripheral circuit. In other words, the substrate 100' may include a first portion and a second portion of different materials. A portion of the peripheral circuit (e.g., peripheral circuit 700) may be disposed on the first portion of the substrate 100', while the stacked structure 200 (including the three-dimensional memory array) may be disposed on the second portion of the substrate 100', with the boundary region 0211 disposed between them. The boundary region 0211 may be disposed on the first portion or on the second portion; this application does not limit this.

[0159] The three-dimensional memory 2000 provided in this application arranges peripheral circuits for controlling signals entering and exiting the memory array on peripheral circuit chip 3000 and substrate 100', respectively. By forming, for example, peripheral high-voltage circuits and the three-dimensional memory array on the same plane of the same substrate, and placing, for example, peripheral low-voltage circuits and peripheral ultra-low-voltage circuits on another chip, the overall size of the peripheral chips can be relatively reduced, and the storage density and integrability of the three-dimensional memory can be improved.

[0160] Alternatively, the substrate 100' containing the peripheral circuitry and the three-dimensional memory array can be a composite substrate on which the peripheral circuitry 700 can be formed. The first portion may include a single-crystal silicon layer of silicon-on-insulator (SiI) retained by removing the substrate of SiI, on which the peripheral circuitry 700 can be formed directly.

[0161] Specifically, such as Figures 5 to 7 As shown, in one embodiment of this application, the substrate 100' includes a single-crystal silicon layer 102, the peripheral high-voltage circuit 700 is directly disposed on the single-crystal silicon layer 102, and includes a shallow trench isolation structure 701 penetrating the single-crystal silicon layer, a gate structure 702 disposed in the region between the shallow trench isolation structures 701, and a source region 703, a drain region 704, and a bias region 705 disposed in the portion of the single-crystal silicon layer 102 and located on both sides of the gate structure 702.

[0162] According to at least one embodiment of the three-dimensional memory provided in this application, an ultrathin single-crystal silicon layer in silicon-on-insulator (SiI) is used as the substrate for peripheral high-voltage circuits to improve latch-up effects, short-channel effects, and radiation resistance in peripheral high-voltage circuits such as high-voltage MOS transistors. Furthermore, in device structures such as MOS transistors fabricated using SiI, by providing a highly doped bias region on the front side of the substrate, its back gate can be led out and polarized, thereby effectively removing parasitic transistors and improving the overall performance of the peripheral high-voltage circuits.

[0163] Furthermore, refer again Figures 5 to 7 and Figure 24 In one embodiment of this application, the first portion of the substrate 100' used to form the peripheral circuit 700 may include a single-crystal silicon layer 102, a spacer layer (insulating dielectric layer 15 and a portion of the second barrier layer 111') and a voltage control capacitor 706 arranged sequentially along the second direction (Z direction), wherein the first direction (X direction) and the second direction (Z direction) may be substantially perpendicular.

[0164] Specifically, the substrate 100' further includes a semiconductor layer (first substrate semiconductor layer 112') facing the gate structure 702, an insulating support layer 130 surrounding the semiconductor layer, and a spacer layer disposed between the semiconductor layer and the single-crystal silicon layer 102. The peripheral high-voltage circuit 700 also includes a first contact 707 filled with a metal layer 16, wherein the first contact 707 extends into the first substrate semiconductor layer 112' to form a voltage control capacitor 706 for the peripheral high-voltage circuit with the gate structure 702 and the spacer layer.

[0165] According to one embodiment of the present application, a three-dimensional memory is provided in which a voltage control capacitor is formed on the side of the peripheral high-voltage circuit close to the substrate, thereby effectively controlling the voltage of the peripheral high-voltage circuit and improving the electrical reliability of the peripheral high-voltage circuit.

[0166] Furthermore, in one embodiment of this application, the three-dimensional memory 2000 further includes a conductive layer 120 and a channel structure penetrating the stacked structure 200 and contacting the conductive layer 120. The channel structure includes a channel hole and a functional layer and a channel layer 330 sequentially formed on the inner wall of the channel hole. The channel layer 330 also includes a first channel layer 331 formed by secondary doping. In other words, the portion of the channel layer 330 extending into and adjacent to the conductive layer 120 is doped to a higher doping concentration than other portions of the channel layer 330 through a secondary doping process. The inclusion of a first channel layer formed by two doping processes in the channel layer 330 enables a good and stable electrical connection between the channel layer and the conductive layer, improving the electrical performance of the three-dimensional memory.

[0167] In one embodiment of this application, the conductive layer 120 contacts both the channel layer 330 and a portion 110' of the substrate 100', wherein a portion 112' of the substrate faces the peripheral high-voltage circuit 700 and the boundary region 0211. Alternatively, the portion 112' of the substrate may include a semiconductor layer. For example, the portion 110' of the substrate may be part of a substrate sacrificial stack in the initial composite substrate for fabricating the three-dimensional memory 2000, comprising a semiconductor layer or an insulating dielectric layer, which may constitute an electrical isolation structure in the substrate to improve the electrical reliability of the peripheral high-voltage circuit.

[0168] Furthermore, in one embodiment of this application, the three-dimensional memory 200 further includes a word line contact 171 formed in the stepped structure 500 and connected to the gate layer 230, and a peripheral contact 172 formed in the insulating dielectric filling layer 13 in the boundary region 0211 and extending to the substrate 100'. According to at least one embodiment of the three-dimensional memory provided in this application, by providing the peripheral contacts of the three-dimensional memory in the boundary region, the wiring between the peripheral circuitry and the three-dimensional memory array can be reduced, thereby improving the voltage transmission effect.

[0169] In another embodiment of this application, the stacked structure 200 is located between the substrate and the substrate 100' of the peripheral circuit chip 3000. The pad leads of the three-dimensional memory 2000 are located on the side of the substrate 100' away from the stacked structure 200. For example, the pad leads may include source contacts 132 located on the side of the substrate 100', facing away from the stacked structure 200 and in contact with the conductive layer 120, and contacts 142 in contact with the peripheral contacts 172, etc.

[0170] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0171] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. For example, various well regions may be formed in the substrate as needed. Furthermore, the materials of the layers described are merely exemplary.

[0172] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The method includes: A peripheral circuit is formed in a first region defined on the surface of the composite substrate, and the first region is covered by a first filler layer; A stacked structure is formed on the surface of the composite substrate and the first filler layer; The portion of the stacked structure located in the boundary region adjacent to the first region is removed to form a groove exposing the composite substrate, and the groove is filled with an insulating dielectric filling layer; and A channel structure and a step structure are formed in the portion of the laminated structure located on the side of the groove away from the peripheral circuit after filling.

2. The method according to claim 1, characterized in that, Before forming a peripheral circuit within a first region defined on the surface of the composite substrate, the method further includes forming the composite substrate, wherein forming the composite substrate includes: The surface of the first substrate is bonded to the surface of the single-crystal silicon layer in silicon-on-insulator; and The silicon-on-insulator substrate is removed to form the composite substrate comprising the single-crystal silicon layer and the first substrate.

3. The method according to claim 2, wherein the first substrate comprises a substrate, a substrate barrier layer, and a substrate semiconductor layer formed sequentially, the substrate semiconductor layer comprising a first substrate semiconductor layer and a second substrate semiconductor layer, and the first substrate semiconductor layer being directly opposite the first region and the boundary region, characterized in that, After forming the channel structure, the method further includes: Remove the substrate and the substrate barrier layer, and remove the second substrate semiconductor layer to expose the single-crystal silicon layer and the functional layer of the channel structure; Remove the exposed functional layer to expose the channel layer of the corresponding channel structure; and Conductive layers are formed on the surface of the exposed single-crystal silicon layer, respectively contacting the first substrate semiconductor layer and the exposed channel layer.

4. The method according to claim 3, characterized in that, Forming conductive layers on the surface of the exposed single-crystal silicon layer that are in contact with the exposed channel layer and the first substrate semiconductor layer respectively includes: An initial conductive layer is formed on the surface of the exposed single-crystal silicon layer and on the surface of the first substrate semiconductor layer, wherein the initial conductive layer is in contact with the exposed channel layer; Remove the portion of the initial conductive layer located on the surface of the first substrate semiconductor layer; and The surface of the first substrate semiconductor layer is flush with the surface of the remaining initial conductive layer to form the conductive layer.

5. The method according to claim 1, wherein the composite substrate comprises a first substrate and a second substrate disposed sequentially, a source region, a drain region, and a bias region of the peripheral circuit are formed in the second substrate, and a gate structure of the peripheral circuit is formed on the second substrate, characterized in that, The method further includes: The portions of the first substrate corresponding to the source region, the drain region, and the bias region are removed to form a first opening, and the first opening is filled with an insulating dielectric layer. Forming a second opening that exposes a first substrate semiconductor layer in the first substrate, the second opening being directly opposite the gate structure; and A metal layer is used to fill the second opening to form a voltage-controlled capacitor for the peripheral circuit.

6. The method according to claim 2, characterized in that, Forming a peripheral circuit within the first region and covering the first region with a first filling layer includes: A shallow trench isolation structure for the peripheral circuit is formed in the first region, wherein the shallow trench isolation structure penetrates the single-crystal silicon layer and extends into the first substrate; The gate structure of the peripheral circuit is formed in the region between the shallow trench isolation structures; A source region, a drain region, and a bias region are respectively formed in the portions of the single-crystal silicon layer located on both sides of the gate structure; and The first filling layer is used to cover the first area.

7. The method according to claim 6, characterized in that, The memory further includes a gate gap structure, characterized in that, The conductive impurities located in the source region, the drain region, and the bias region are annealed by the heat generated during the formation of the channel structure, the gate gap structure, and the step structure.

8. The method according to claim 1, characterized in that, After forming the stepped structure, the method further includes: A peripheral contact is formed in the insulating dielectric filling layer of the boundary region.

9. The method according to any one of claims 1 to 8, characterized in that, After forming the channel structure and the step structure, the method further includes: A peripheral circuit chip is connected to the side of the stacked structure away from the composite substrate. The peripheral circuit chip includes any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

10. The method according to any one of claims 1 to 8, characterized in that, The peripheral circuit includes any one or a combination of peripheral high-voltage circuit, peripheral low-voltage circuit, and peripheral ultra-low-voltage circuit.

11. A three-dimensional memory, characterized in that, The memory includes: Substrate; An external high-voltage circuit is disposed on the surface of the substrate; A stacked structure is disposed on the surface and includes alternately stacked sacrificial layers and gate layers; A channel structure extending through the stacked structure and into the substrate; and The peripheral circuit chip is disposed on the side of the stacked structure away from the substrate, and includes any one or a combination of peripheral low-voltage circuits and peripheral ultra-low-voltage circuits. A boundary region is provided between the stacked structure and the peripheral high-voltage circuit, and the boundary region is filled with an insulating dielectric filling layer.

12. The memory according to claim 11, characterized in that, The substrate includes a first part and a second part made of different materials, wherein the peripheral high-voltage circuit is disposed on the first part and the stacked structure is disposed on the second part.

13. The memory according to claim 12, characterized in that, The first part includes a monocrystalline silicon layer of silicon-on-insulator (SOI) retained by removing the substrate of SOI, wherein the peripheral high-voltage circuit is directly disposed on the monocrystalline silicon layer.

14. The memory according to claim 13, wherein the first portion and the second portion are adjacent in a first direction, characterized in that, The first part includes the monocrystalline silicon layer, the spacer layer, and the voltage control capacitor arranged sequentially along a second direction perpendicular to the first direction.

15. The memory according to claim 11, characterized in that, The stacked structure is located between the substrate of the peripheral circuit chip and the substrate, and the memory pad leads are located on the side of the substrate away from the stacked structure.

16. The memory according to claim 12, characterized in that, The boundary region is located on the first part or the second part.

17. The memory according to claim 11, characterized in that, The memory also includes: The insulating dielectric filling layer is formed in the boundary region and extends to the peripheral contact of the substrate.

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