Optical assembly undercut by a sealed cavity

Abstract

The present invention relates to optical assemblies with a seal cavity undercut, structures including optical assemblies, such as edge couplers, and methods of fabricating structures including optical assemblies, such as edge couplers. The structures include a substrate having a seal cavity, an optical assembly, and a dielectric layer between the optical assembly and the seal cavity. The optical assembly is vertically above the substrate and the dielectric layer, and the optical assembly overlaps the seal cavity in the substrate.

Description

TECHNICAL FIELD

[0001] The present invention relates to photonic chips, and in particular to structures including optical components such as edge couplers and methods of fabricating structures including optical components such as edge couplers. BACKGROUND

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. Photonic chips integrate optical components (e.g., waveguides, photodetectors, modulators, and optical power splitters) with electronic components (e.g., field effect transistors) on a unified platform. By integrating both types of components on the same chip, factors such as layout area, cost, and operational overhead can be reduced.

[0003] Edge couplers (also known as spot size converters) are commonly used to couple light of a given mode from a light source, such as a laser or an optical fiber, to an optical component on a photonic chip. The edge coupler can include a waveguide core segment that defines an inverse taper disposed adjacent to the light source. An inverse taper refers to a tapered segment of a waveguide core characterized by a gradually increasing width along a direction of mode propagation. In the edge coupler configuration, the narrow end of the inverse taper provides a facet disposed adjacent to the light source, and the wide end of the inverse taper is connected to another segment of the waveguide core to route the light to the optical component of the photonic chip.

[0004] As light propagates from the light source to the edge coupler, the gradually varying cross-sectional area of the inverse taper supports mode conversion and mode size change associated with mode conversion. The narrow end at the top end of the inverse taper cannot completely confine the incident mode received from the light source because the cross-sectional area at the top end of its narrow end is much smaller than the mode size. As a result, a significant portion of the electromagnetic field of the incident mode is distributed around the top end of the inverse taper. As the width increases, the inverse taper can support the entire incident mode and confine the electromagnetic field.

[0005] Conventional edge couplers can exhibit significant leakage loss to the substrate of the photonic chip, especially for large mode sizes. It has proven difficult to implement satisfactory corrective measures.

[0006] There is a need for improved structures including optical components such as edge couplers and methods of fabricating structures including optical components such as edge couplers. SUMMARY

[0007] In one embodiment of the present invention, a structure includes a substrate having a sealed cavity, an optical component, and a dielectric layer between the optical component and the sealed cavity. The optical component is vertically above the substrate and the dielectric layer, and the optical component overlaps the sealed cavity in the substrate.

[0008] In one embodiment of the present application, a method includes forming an optical component and forming a sealed cavity in a substrate. A dielectric layer is disposed between the optical component and the sealed cavity. The optical component is vertically positioned above the substrate and the dielectric layer, and the optical component overlaps the sealed cavity in the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate various embodiments of the present application and, together with the description, serve to explain the embodiments of the present application. In the drawings, like reference numerals refer to similar parts throughout the various views and embodiments disclosed herein.

[0010] Figure 1 A top view of a structure at an initial fabrication stage of a processing method in accordance with an embodiment of the present application is shown.

[0011] Figure 2 A cross-sectional view of the structure taken generally along line 2-2 in Figure 1

[0012] A cross-sectional view of the structure taken generally along line 2A-2A in Figure 2A Figure 1 A cross-sectional view of the structure taken generally along line 2B-2B in

[0013] Figure 2B Figure 1 A cross-sectional view of the structure taken generally along line 4B-4B in

[0014] Figure 3 A top view of the structure at a fabrication stage of the processing method after Figure 1

[0015] A cross-sectional view of the structure taken generally along line 4-4 in Figure 4 Figure 3 A cross-sectional view of the structure taken generally along line 4A-4A in

[0016] Figure 4A Figure 3 A cross-sectional view of the structure taken generally along line 4B-4B in

[0017] Figure 4B A cross-sectional view of the structure taken generally along line 4B-4B in Figure 3

[0018] A cross-sectional view of the structure taken generally along line 4B-4B in Figure 5 Figure 3 A top view of the structure at a fabrication stage of the processing method after

[0019] Figure 6 Figure 5 ​​​​​​The cross-sectional view of the structure is shown in line 6-6.

[0020] Figure 6A Showing the general outline Figure 5 The cross-sectional view of the structure is taken along line 6A-6A.

[0021] Figure 6B Showing the general outline Figure 5 The cross-sectional view of the structure is drawn along line 6B-6B.

[0022] Figure 7 Display in Figure 5 A top view of the structure during the manufacturing stage of this processing method.

[0023] Figure 8 Showing the general outline Figure 7 The cross-sectional view of the structure is shown in line 8-8.

[0024] Figure 8A Showing the general outline Figure 7 The cross-sectional view of the structure is drawn along line 8A-8A.

[0025] Figure 8B Showing the general outline Figure 7 The cross-sectional view of the structure is drawn along line 8B-8B.

[0026] Figure 9 Display in Figure 7 A top view of the structure during the manufacturing stage of this processing method.

[0027] Figure 10 Showing the general outline Figure 9 The cross-sectional view of the structure is shown in line 10-10.

[0028] Figure 10A Showing the general outline Figure 9 The cross-sectional view of the structure is drawn along line 10A-10A.

[0029] Figure 10B Showing the general outline Figure 9 The cross-sectional view of the structure is made along line 10B-10B.

[0030] Figure 11 A top view showing a structure according to an alternative embodiment of the present invention. Detailed Implementation

[0031] Please refer to Figure 1 , 2In accordance with the embodiments of the present application, edge coupler 10 includes a plurality of segments 12 and segments 20, 22 of waveguide core 14 disposed adjacent segments 12. Segments 12 and segments 20, 22 of waveguide core 14 are arranged along a longitudinal axis 13 of edge coupler 10. Segments 12 are arranged along longitudinal axis 13 as a feature in the portion of edge coupler 10 that initially receives light from a light source, such as an optical fiber or a laser. The light propagates within edge coupler 10 in a direction from segments 12 toward segments 20, 22 of waveguide core 14. Each segment 12 has opposing sidewalls 16, 17 along its sides, and waveguide core 14 includes opposing sidewalls 18, 19 along its sides. Segment 20 of waveguide core 14 includes notches or indentations in sidewalls 18, 19, and segment 22 of edge coupler 10 is tapered.

[0032] In alternative embodiments, edge coupler 10 can have different configurations. In alternative embodiments, edge coupler 10 can be replaced by different types of optical components, such as a rib waveguide core, a tapered waveguide core, a flat waveguide core, etc.

[0033] Edge coupler 10 can be disposed above a dielectric layer 24. In one embodiment, dielectric layer 24 can be composed of silicon dioxide. In one embodiment, dielectric layer 24 can be a buried oxide layer of a silicon-on-insulator substrate, and the silicon-on-insulator substrate can further include a substrate 26 composed of a semiconductor material, such as monocrystalline silicon. Segments 12 and waveguide core 14 can be composed of a semiconductor material, such as monocrystalline silicon. In one embodiment, segments 12 and waveguide core 14 can be formed simultaneously by patterning a monocrystalline silicon device layer of a silicon-on-insulator substrate using photolithography and etching processes. In one embodiment, segments 12 and waveguide core 14 can be patterned from the device layer by photolithography and etching processes without etching completely through the device layer, thereby forming a connecting plate layer that is thinner than segments 12 and waveguide core 14.

[0034] In alternative embodiments, edge coupler 10 can be composed of different materials. In one embodiment, segments 12 and waveguide core 14 can be composed of a dielectric material, such as silicon nitride. Segments 12 and waveguide core 14 can be formed by depositing a layer of the composition material and patterning the deposited layer using photolithography and etching processes.

[0035] Reference is made to Figure 3 4 , 4A, 4B, wherein like reference numerals refer to like features in Figure 1 2 , 2A, 2B, and at a next stage of fabrication, a dielectric layer 25 can be deposited above edge coupler 10 and dielectric layer 24. Dielectric layer 25 can be composed of a dielectric material, such as silicon dioxide, which is deposited by chemical vapor deposition and planarized by chemical mechanical polishing.

[0036] ​​The dielectric layers 24, 25 are patterned using photolithography and etching processes to define openings 28, 29 that extend completely through the dielectric layers 24, 25 to the substrate 26. The photolithography process can entail forming an etch mask that includes a photoresist layer that is applied by a spin-on process, pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer to form respective openings over the predetermined locations of the openings 28, 29. The etching process can be a non-isotropic etching process, such as a reactive ion etching process, and after the openings 28, 29 are formed, the etch mask can be removed by, for example, plasma ashing.

[0037] The openings 28, 29 can be elongated or slit-shaped, having a length that is substantially greater than a width, and can be arranged in parallel rows in a rectangular array at a given pitch that is symmetrically disposed with respect to the longitudinal axis 13 of the edge coupler 10. The openings 28 can be disposed in the dielectric layer 24 adjacent the sidewalls 16 of the segments 20, 22 of the waveguide core 14 and the sidewalls 18 of the slab 12. The openings 29 can be disposed in the dielectric layer 24 adjacent the sidewalls 17 of the segments 20, 22 of the waveguide core 14 and the sidewalls 19 of the slab 12. Along a direction transverse to the longitudinal axis 13, the openings 28 are spaced apart from the openings 29 by a pitch S. The openings 28, 29 define vias that extend through the dielectric layer 24 to the substrate 26 to perform a subsequent isotropic etching process to etch the substrate 26. Portions of the dielectric layer 24 are disposed as bridges between adjacent pairs of openings 28 and as bridges between adjacent pairs of openings 29 to maintain mechanical support after the substrate 26 underlying the dielectric layer 24 is removed by performing the subsequent isotropic etching process.

[0038] The openings 28, 29 can have a uniform pitch to define a periodic arrangement. In alternative embodiments, the pitch of the openings 28, 29 can be apodized (i.e., non-uniform) to define a non-periodic arrangement. In one embodiment, the openings 28, 29 can have a rectangular patterned shape. In alternative embodiments, the openings 28, 29 can have different patterned shapes, such as an elliptical shape or a trapezoidal shape. The openings 28, 29 can have a major axis (i.e., length) that is aligned with the longitudinal axis 13 of the edge coupler 10, or, alternatively, the major axis of the openings 28, 29 can be angled or tilted with respect to the longitudinal axis 13 of the edge coupler 10, or even arranged perpendicular to the longitudinal axis 13 of the edge coupler 10. In alternative embodiments, multiple adjacent rows of openings 28 and / or multiple adjacent rows of openings 29 can be formed.

[0039] Reference is made to Figure 5 , 6 , 6A, 6B, wherein like reference numerals refer to like parts throughout Figure 3 , 4Similar features to those in 4A and 4B, and in the next manufacturing stage, using a patterned dielectric layer 24 as a hard mask, a cavity 30 is formed in the substrate 26 via a wet or dry isotropic etching process. Openings 28 and 29 provide entry points into the substrate 26 for the isotropic etching process performed to form the cavity 30. This isotropic etching process includes deepening the lateral etch component of the cavity 30 and widening the vertical etch component of the cavity 30. In one embodiment, the cavity 30 may be centered between rows of openings 28 and 29. The length, width, and spacing of openings 28 and 29 can be adjusted to modify the properties of the cavity 30.

[0040] Cavity 30 is disposed in substrate 26 below segments 20 and 22 of segment 12 and waveguide core 14. Edge coupler 10 is located on dielectric layer 24 to overlap with cavity 30 located in substrate 26. In one embodiment, edge coupler 10 may be centered above cavity 30. Cavity 30 includes chamber 32 and chamber 34 connected to and merged with chamber 32. Chamber 32 communicates with opening 28, chamber 34 communicates with opening 29, and chambers 32 and 34 merge during etching due to the lateral etching component. Cavity 30 may have a length L between end 36 and end 38 opposite to end 36, and cavity 30 may extend over the entire length of edge coupler 10. Cavity 30 has a width W greater than the width of edge coupler 10. Cavity 30 is closed at opposite ends 36 and 38, and portions of substrate 26 serve as corresponding longitudinal boundaries at opposite ends 36 and 38. The isotropic etching process can be controlled so that neither of the ends 36, 38 is opened by intersecting, for example, the edge of the substrate 26.

[0041] The cavity 30 is completely sealed from above by a dielectric layer 24 and from below and sides by a substrate 26, except for subsequently sealed openings 28 and 29. The cavity 32 includes curved sidewalls 33, and the cavity 34 includes curved sidewalls 35 intersecting the sidewalls 33 to define a ridge 40 as a cusp. In embodiments where openings 28 and 29 are symmetrically arranged relative to the edge coupler 10, the ridge 40 may be located directly below segments 20 and 22 of the segment 12 and waveguide core 14.

[0042] Please refer to Figure 7 , 8 8A, 8B, where similar reference numerals indicate Figure 5 , 6 Similar features to those in 6A and 6B are incorporated, and in the next manufacturing stage, plugs 42 are formed in openings 28 and 29. Plugs 42 can be formed by chemical vapor deposition of a dielectric layer over the edge coupler 10 and dielectric layer 25, followed by planarization of the dielectric layer through chemical mechanical polishing. Plugs 42 can be composed of a dielectric material such as silicon dioxide.

[0043] The plugs 42 fill and occlude at least a portion of each of the openings 28, 29 in the dielectric layers 24, 25 as occlusions of the openings 28, 29. After the plugs 42 are formed, the cavities 30 are completely sealed, thereby defining air gaps that can contain atmospheric air at or near atmospheric pressure, can contain another gas at or near atmospheric pressure, or can contain atmospheric air or another gas at sub-atmospheric pressure (e.g., a partial vacuum). The air gaps defined by the sealed cavities 30 can be characterized by a dielectric constant close to one (i.e., the vacuum dielectric constant), which is less than the dielectric constant of the solid dielectric material. The index of refraction of the sealed cavities 30 (which is proportional to the dielectric constant) is significantly lower than the index of refraction of the solid dielectric material.

[0044] The structures including the edge coupler 10 and the sealed cavities 30 in any of the embodiments described herein can be integrated in a photonic chip that includes electronic components and additional optical components. For example, the electronic components can include field effect transistors fabricated by CMOS processing.

[0045] The edge coupler 10 is undercut by the sealed cavities 30 in the substrate 26. Due to the low index of refraction open space introduced by the sealed cavities 30 between the edge coupler 10 and the substrate 26, the structure including the edge coupler 10 and the sealed cavities 30 can exhibit reduced optical leakage loss from the edge coupler 10 to the substrate 26 during operation. The structure including the edge coupler 10 and the sealed cavities 30 can also enhance thermal isolation of the edge coupler 10 from the substrate 26 by eliminating a thermal conduction path from the edge coupler 10 to the substrate 26.

[0046] Referring to Figure 9 , 10 , 10A, 10B and in accordance with alternative embodiments of the present application, the openings 28 and 29 can be arranged in a tapered array in which the spacing S between adjacent pairs of openings 28 and 29 varies longitudinally from narrow to wide spacing in different rows of the array. This variation in the spacing S can result in a variation in the shape of the cavities 30 at different locations along the direction between the ends 36 and 38 and parallel to the longitudinal axis 13 of the edge coupler 10. For example, due to the variation in the spacing S, the shape of the ridge 40 can vary over the length of the cavities 30 at different locations along the direction between the ends 36 and 38. In one embodiment, the variation in the shape of the cavities 30 along their length can be continuous.

[0047] Referring to Figure 11And according to alternative embodiments of the application, the openings 28 and 29 can be offsetly arranged to provide an interleaved arrangement within the rows of the array, such that the pitch S varies periodically between a smaller pitch and a larger pitch in the direction between the ends 36 and 38. The varying position of the openings 28, 29 can result in a variation in the shape of the cavities 30 (e.g., a variation in the shape of the ridges 40) at different positions between the ends 36 and 38, generally as shown in Figure 10A , 10B shown in FIGS. 15A and 15B. The shape of the cavities 30 can vary locally depending on the amount of offset variation.

[0048] The above-described method is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator as raw chips, as a part of the computer system they are used in, or as a part of other products such as a smartphone.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Language of approximation, such as "approximately," "substantially," and "about," can be used to describe a value, parameter, state, or condition, that can vary with measurement instrumentation or analysis techniques. Unless otherwise stated, a value, parameter, state, or condition can vary by +10% or more.

[0050] Terms such as "vertical," "horizontal," and the like are used herein with references to the example frame of reference and are not intended to be limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "lateral" refer to directions that are perpendicular to the horizontal as just defined. The term "lateral" refers to a direction in the horizontal plane.

[0051] A feature that is "connected," or "coupled," to another feature can be directly connected or coupled to the other feature or can be indirectly connected or coupled to the other feature by way of one or more intermediate features. If there are no intermediate features, then the feature is "directly connected," or "directly coupled," to the other feature. If there are one or more intermediate features, then the feature is "indirectly connected," or "indirectly coupled," to the other feature. A feature that is "on" or "contacting" another feature can be directly on or contacting the other feature or can be indirectly on or contacting the other feature by way of one or more intermediate features. If there are no intermediate features, then the feature is "directly on" or "directly contacting" the other feature. If there are one or more intermediate features, then the feature is "not directly on" or "not directly contacting" the other feature. Different features can be "overlapped" if one feature extends over the other feature and covers part of it, either in direct contact or not in direct contact.

[0052] The description of various embodiments of the application has been made for the purpose of exemplification, and is not intended to be exhaustive or to be limited to the embodiments disclosed. Many modifications and variations will become apparent to those of ordinary skill in the art, without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure of a photonic chip, characterized by, The structure includes: a substrate including a sealed cavity; an edge coupler including a waveguide core having a first sidewall and a second sidewall, the edge coupler having a longitudinal axis; and a dielectric layer between the waveguide core and the sealed cavity, the dielectric layer including a first plurality of blockage openings extending into the sealed cavity adjacent the first sidewall of the waveguide core and a second plurality of blockage openings extending into the sealed cavity adjacent the second sidewall of the waveguide core, the first plurality of blockage openings and the second plurality of blockage openings being arranged in a tapered array, a spacing between the first plurality of blockage openings and the second plurality of blockage openings varying along a position of the longitudinal axis, wherein the waveguide core is above the substrate and the dielectric layer, the sealed cavity has a shape that varies along the position of the longitudinal axis, and the waveguide core overlaps the sealed cavity in the substrate.

2. The structure of claim 1, wherein The dielectric layer and the substrate collectively surround the sealed cavity.

3. The structure of claim 2, wherein The dielectric layer includes a first plurality of plugs blocking the first plurality of blockage openings and a second plurality of plugs blocking the second plurality of blockage openings.

4. The structure of claim 1, wherein The sealed cavity includes a first chamber and a second chamber, the sealed cavity having a first end and a second end spaced from the first end along the longitudinal axis, the first chamber having a curved first sidewall, the second chamber having a curved second sidewall, and the first sidewall of the first chamber and the second sidewall of the second chamber intersecting at a ridge, the ridge extending from the first end to the second end.

5. The structure of claim 4, wherein The edge coupler is centered with respect to the first chamber and the second chamber.

6. The structure of claim 1, wherein The sealed cavity has a first end and a second end spaced from the first end along the longitudinal axis, and a shape of the sealed cavity varies between the first end and the second end.

7. The structure of claim 1, wherein The dielectric layer includes a first plurality of plugs blocking the first plurality of blockage openings and a second plurality of plugs blocking the second plurality of blockage openings.

8. The structure of claim 1, wherein The edge coupler includes single-crystal silicon.

9. A method of forming a structure of a photonic chip, characterized by, The method includes: forming an edge coupler including a waveguide core having a first sidewall and a second sidewall, wherein the edge coupler has a longitudinal axis; and forming a sealed cavity in a substrate, wherein a dielectric layer is disposed between the edge coupler and the sealed cavity, the edge coupler is above the substrate and the dielectric layer, the dielectric layer includes a first plurality of blockage openings extending into the sealed cavity adjacent the first sidewall of the waveguide core and a second plurality of blockage openings extending into the sealed cavity adjacent the second sidewall of the waveguide core, the first plurality of blockage openings and the second plurality of blockage openings are arranged in a tapered array, a spacing between the first plurality of blockage openings and the second plurality of blockage openings varies along a position of the longitudinal axis, the sealed cavity has a shape that varies along the position of the longitudinal axis, and the edge coupler overlaps the sealed cavity in the substrate.

10. The method of claim 9, wherein, The sealed cavity is formed after the waveguide core of the edge coupler is formed.

Images