RISC-V-based control method, system, chip and storage medium

Abstract

The application relates to the technical field of chip control and discloses a control method and system based on RISC-V, a chip and a storage medium, the control method based on RISC-V is applied to a control system based on RISC-V, the control system based on RISC-V comprises an instruction decoding unit, an open-source instruction set RISC-V processor and an input and output port GPIO, the method comprises the following steps: acquiring a control instruction read by the RISC-V processor through the instruction decoding unit, and determining a decoding instruction corresponding to the control instruction; determining direction switching information according to the decoding instruction and prestored historical switching information; determining a target processing unit corresponding to the direction switching information, and controlling the GPIO according to the decoding instruction through the target processing unit, so that the control efficiency of chip input and output is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip control, and particularly to a control method and system based on RISC-V, a chip and a storage medium. BACKGROUND

[0002] With the continuous development of chip technology, chips are used more and more frequently in various fields. Based on the pursuit of control efficiency, higher requirements are put forward for the input and output control of chips.

[0003] The traditional chip input and output control mode is GPIO (General-purpose input / output) as a slave device, connected to the SoC (System on Chip) bus in a memory mapping manner; the processor inside the chip as a master device is connected to the SoC bus; the processor controls the control register in the GPIO module by issuing memory read / write instructions, thereby controlling / reading the level of the chip IO (input / output) pin. This chip input and output control mode has great defects, and the memory read / write instructions issued by the chip processor need to pass through the bus logic before reaching the GPIO, that is, this chip input and output control mode will cause the chip input and output control efficiency to be not high because the read / write instructions need to pass through the bus logic before the input / output can be realized. SUMMARY

[0004] The main purpose of the present application is to provide a control method and system based on RISC-V, a chip and a storage medium, which aims to improve the control efficiency of chip input and output.

[0005] To achieve the above purpose, the present application provides a control method based on RISC-V, which is applied to a control system based on RISC-V, the control system based on RISC-V comprising an instruction decoding unit, an open source instruction set RISC-V processor and an input and output port GPIO, the control method based on RISC-V comprising the following steps:

[0006] The instruction decoding unit acquires the control instruction read by the RISC-V processor, and determines the decoding instruction corresponding to the control instruction;

[0007] The direction switching information is determined according to the decoding instruction and the pre-stored historical switching information;

[0008] The target processing unit corresponding to the direction switching information is determined, and the GPIO is controlled by the target processing unit according to the decoding instruction.

[0009] Optionally, the step of determining the direction switching information according to the decoded instruction and the pre-stored historical switching information comprises:

[0010] determining an instruction feature corresponding to the decoded instruction, and detecting whether the instruction feature matches a preset direction switching instruction feature;

[0011] if the instruction feature does not match the preset direction switching instruction feature, determining a transmission direction corresponding to the pre-stored historical switching information, and taking the transmission direction as the direction switching information.

[0012] Optionally, after the step of detecting whether the instruction feature matches the preset direction switching instruction feature, the method further comprises:

[0013] if the instruction feature matches the preset direction switching instruction feature, determining a direction instruction corresponding to the decoded instruction;

[0014] controlling the GPIO to switch directions by the direction switching unit according to the direction instruction, and performing the step of obtaining the control instruction read by the RISC-V processor by the instruction decoding unit based on the GPIO after the direction switching.

[0015] Optionally, the RISC-V-based control system comprises an input processing unit and an output processing unit, and the step of determining a target processing unit corresponding to the direction switching information comprises:

[0016] determining a transmission direction in the direction switching information, and detecting whether the transmission direction matches a preset input direction;

[0017] if the transmission direction matches the preset input direction, determining that the target processing unit is the input processing unit;

[0018] if the transmission direction does not match the preset input direction, determining that the target processing unit is the output processing unit.

[0019] Optionally, the step of controlling the GPIO according to the decoded instruction by the target processing unit comprises:

[0020] if the target processing unit is the input processing unit, determining a level return requirement corresponding to the decoded instruction;

[0021] determining an input value corresponding to an original level of the GPIO input based on the level return requirement, and / or determining an instruction operation corresponding to the decoded instruction, and determining a return value corresponding to a preset source operand of the original level based on the instruction operation.

[0022] Optionally, the step of controlling the GPIO according to the decoded instruction by the target processing unit further comprises:

[0023] If the target processing unit is an output processing unit, determining an output value instruction in the decoding instruction;

[0024] Determining an output value corresponding to the GPIO output based on the output value instruction and the decoding instruction.

[0025] Optionally, the step of determining an output value corresponding to the GPIO output based on the output value instruction and the decoding instruction comprises:

[0026] Determining a first source operand value and a second source operand value corresponding to the output value instruction, and determining a value operation instruction in the decoding instruction;

[0027] Determining an output value of the GPIO output based on the value operation instruction on the first source operand value and the second source operand value.

[0028] In addition, to achieve the above object, the present application also provides a RISC-V based control system, which comprises:

[0029] A reading decoding module is configured to acquire a control instruction read by a RISC-V processor through an instruction decoding unit, and determine a decoding instruction corresponding to the control instruction;

[0030] A direction switching module is configured to determine direction switching information according to the decoding instruction and pre-stored historical switching information;

[0031] An instruction processing module is configured to determine a target processing unit corresponding to the direction switching information, and control a GPIO through the target processing unit according to the decoding instruction.

[0032] In addition, to achieve the above object, the present application also provides a RISC-V based control chip, which comprises a memory, a processor, and a RISC-V based control program stored in the memory and executable on the processor, wherein the RISC-V based control program is used to implement the steps of the above-mentioned RISC-V based control method when executed by the processor.

[0033] In addition, to achieve the above object, the present application also provides a RISC-V based control storage medium, wherein the storage medium stores a RISC-V based control program, and the RISC-V based control program is used to implement the steps of the above-mentioned RISC-V based control method when executed by a processor.

[0034] The application discloses a control method based on RISC-V, which comprises the following steps: acquiring a control instruction read by a RISC-V processor through an instruction decoding unit, and determining a decoding instruction corresponding to the control instruction; determining direction switching information according to the decoding instruction and pre-stored historical switching information; determining a target processing unit corresponding to the direction switching information, and controlling a GPIO according to the decoding instruction through the target processing unit. The control instruction read by the RISC-V processor is acquired through the instruction decoding unit, then the target processing unit corresponding to the direction switching information is determined after the control instruction is decoded, and the GPIO is controlled according to the decoding instruction through the target processing unit, so that the control of the GPIO input and output is realized.

[0035] Therefore, the application avoids the phenomenon that the memory read and write instructions issued by the chip processor need to pass through bus logic before reaching the GPIO in the prior art. The control method based on RISC-V can not only guarantee the open source of the control instruction through the control instruction read by the RISC-V processor, increase the instruction modification and expansion function used by the user, but also control the GPIO according to the decoding instruction through the target processing unit, thereby improving the control efficiency of the chip input and output. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a hardware running environment control chip structure schematic diagram based on RISC-V related to the embodiment scheme of the application.

[0037] Figure 2 It is a flowchart of the control method based on RISC-V.

[0038] Figure 3 It is a structure schematic diagram of the control system based on RISC-V.

[0039] Figure 4 It is a schematic diagram of an embodiment of the control system based on RISC-V.

[0040] Figure 5 It is a schematic diagram of the existing GPIO control structure.

[0041] Figure 6 It is a module schematic diagram of the control system based on RISC-V.

[0042] Explanation of the attached drawings:

[0043] Reference Name Reference Name 10 Open-source instruction set RISC-V processor 11 Register file 12 Instruction interface 20 Instruction decoding unit 30 Direction switching unit 40 Input processing unit 50 Output processing unit 60 General-purpose input-output port GPIO 00 RISC-V-based control chip 01～0N Peripheral 1~Peripheral N

[0044] The purpose of the application, the functional characteristics and the advantages will be further explained in combination with the embodiments and with reference to the drawings. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0046] Referring to Figure 1 Figure 1 The RISC-V-based control chip structure diagram of the hardware running environment involved in the embodiment of the present application.

[0047] As Figure 1 shown, the RISC-V-based control chip can include a processor 0003, such as a central processing unit (CPU), a communication bus 0001, an acquisition interface 0002, a processing interface 0004, and a memory 0005. The communication bus 0001 is used to realize the connection and communication between the components. The acquisition interface 0002 can include an information collection device, an acquisition unit such as a computer, and can also include a standard wired interface and a wireless interface. The processing interface 0004 can optionally include a standard wired interface and a wireless interface. The memory 0005 can be a high-speed random access memory (RAM), and can also be a stable non-volatile memory (NVM) such as a disk memory. The memory 0005 can also be an independent storage device from the aforementioned processor 0003.

[0048] Those skilled in the art can understand that Figure 1 the structure shown in the figure does not constitute a limitation on the RISC-V-based control chip, and can include more or fewer components than the figure, or combine certain components, or different component arrangements.

[0049] As Figure 1 shown, the memory 0005 as a storage medium can include an operating system, an acquisition interface module, a processing interface module, and a RISC-V-based control program.

[0050] In Figure 1 ​The communication bus 0001 in the RISC-V-based control chip shown is mainly used to realize the connection and communication between components; the acquisition interface 0002 is mainly used to connect the background server and communicate data with the background server; the processing interface 0004 is mainly used to connect the deployment end (user end) and communicate data with the deployment end; the processor 0003 and the memory 0005 in the RISC-V-based control chip can be arranged in the RISC-V-based control chip, and the RISC-V-based control chip calls the RISC-V-based control program stored in the memory 0005 through the processor 0003 and executes the RISC-V-based control system provided in the embodiment of the application.

[0051] Based on the above hardware structure, the RISC-V-based control method embodiment of the application is proposed.

[0052] The first embodiment of the RISC-V-based control method of the application is proposed, and the RISC-V-based control method is described with reference to Figure 2 , Figure 2 The flowchart of the RISC-V-based control method is shown, and the RISC-V-based control method comprises:

[0053] In step S10, the control instruction read by the RISC-V processor is obtained through the instruction decoding unit, and the decoding instruction corresponding to the control instruction is determined.

[0054] In this embodiment, after the RISC-V processor reads the control instruction according to the instruction information input by the user or the instruction in the memory, the control instruction read by the RISC-V processor is obtained through the instruction decoding unit, and the decoding instruction corresponding to the control instruction is determined. The instruction information refers to the instruction input by the user, and the corresponding control instruction is read by the RISC-V processor according to the instruction. After obtaining the control instruction, the decoding instruction is obtained by decoding in the instruction decoding unit, and finally the decoding instruction can be sent to the corresponding processing unit according to the internal instruction characteristics of the decoding instruction, so as to ensure the accuracy of the processing instruction.

[0055] In step S20, the direction switching information is determined according to the decoding instruction and the pre-stored historical switching information.

[0056] In this embodiment, after obtaining the decoding instruction, the direction switching information is determined according to the decoding instruction and the pre-stored historical switching information. The pre-stored historical switching information refers to the direction information corresponding to the previous decoding instruction. For example, if the direction information corresponding to the previous decoding instruction is the output direction, the output direction will be used as the pre-stored historical switching information. The direction switching information refers to the switching information of the input and output direction of the GPIO. The step of determining the direction switching information according to the decoding instruction and the pre-stored historical switching information comprises:

[0057] Step A10, determine the instruction feature corresponding to the decoding instruction, and detect whether the instruction feature matches the preset direction switching instruction feature;

[0058] In the embodiment, when determining the direction switching information, it is necessary to determine the instruction feature corresponding to the decoding instruction, and detect whether the instruction feature matches the preset direction switching instruction feature, because there are at least three cases of the decoding instruction, one is the decoding instruction for switching direction, one is the decoding instruction for input control, and one is the decoding instruction for output control. The instruction feature refers to the feature of the control of the decoding instruction obtained through the instruction decoding unit. The preset direction switching instruction feature refers to the instruction feature of the direction switching instruction. By detecting whether the instruction feature matches the preset direction switching instruction feature, it can be determined whether the decoding instruction is a direction switching instruction. After the step of detecting whether the instruction feature matches the preset direction switching instruction feature, the following steps are included:

[0059] Step B10, if the instruction feature matches the preset direction switching instruction feature, determine the direction instruction corresponding to the decoding instruction;

[0060] Step B20, control the GPIO to switch direction through the direction switching unit according to the direction instruction, and execute the step of obtaining the control instruction read by the RISC-V processor through the instruction decoding unit based on the GPIO after direction switching.

[0061] In the embodiment, when the instruction feature matches the preset direction switching instruction feature, it is determined that the decoded instruction corresponds to a direction instruction, that is, it is determined that the decoded instruction is a direction switching instruction. The direction instruction refers to an instruction for switching the input or output direction of the GPIO. For example, Io.set rs1=1, rd, which is defined as switching the input direction of the GPIO according to the value of rs1 being 1; Io.set rs1=0, rd, which is defined as switching the output direction of the GPIO according to the value of rs1 being 0. After executing the GPIO output / input direction, rd is returned to show that the execution is successful. The return execution success value of rd can be customized by the user or set as a default value. After the value of rs1 is determined in the decoded instruction, the instruction feature corresponding to the value is determined, and then it is determined whether it is an input or output direction switching according to the instruction feature of the value, that is, it is actually determined that Io.set rs1=1 in the decoded instruction, and then it is determined whether it is a direction switching instruction feature, and then it is determined whether it is an input or output direction switching instruction according to the value of rs1. After determining the direction switching instruction, the decoded instruction is sent to the corresponding direction switching unit. The direction switching unit controls the GPIO to switch the direction according to the direction instruction, and also stores the direction instruction as the pre-stored historical switching information. After switching, the step of acquiring the control instruction read by the RISC-V processor through the instruction decoding unit is performed, that is, after switching the direction of the GPIO, the step of acquiring the control instruction read by the RISC-V processor through the instruction decoding unit is performed to realize the input and output control of the GPIO, and further improve the efficiency of the input and output control of the GPIO. The transmission process of the bus logic and protocol through the bus is not required, and the efficiency of the input and output of the entire GPIO can be greatly improved.

[0062] In step A20, if the instruction feature does not match the preset direction switching instruction feature, the pre-stored historical switching information corresponding to the transmission direction is determined, and the transmission direction is used as the direction switching information.

[0063] In the embodiment, when it is determined that the instruction feature does not match the preset direction switching instruction feature, the transmission direction corresponding to the pre-stored historical switching information is determined, and the transmission direction is taken as the direction switching information. That is, when the instruction feature does not match the preset direction switching instruction feature, it can be known that the decoding instruction is an input or output control instruction. The transmission direction corresponding to the decoding instruction is determined by determining the transmission direction corresponding to the pre-stored historical switching information. The transmission direction refers to the input or output direction. That is, the transmission direction of the current decoding instruction is determined according to the last decoding instruction. Because the last decoding instruction and the current decoding instruction are instructions that cause direction switching, the transmission direction of the last decoding instruction needs to be continued for the current decoding instruction. When the transmission direction of the input or output control instruction is different from the transmission direction corresponding to the historical switching information, the instruction fails, and the rd returns a failure value. On the other hand, after the decoding instruction is determined, it is determined whether the instruction feature of the decoding instruction matches the preset input direction instruction feature. If yes, the input direction is determined as the direction switching information. Otherwise, the output direction is determined as the direction switching information. For example, when the decoding instruction is Io.out.raw rs1, rd, it is determined that the instruction feature in the decoding instruction is out, and then it is determined that the preset output direction instruction feature is matched. Otherwise, when the decoding instruction is Io.in.tail1 rd, it is determined that the instruction feature in the decoding instruction is in, and then it is determined that the preset input direction instruction feature is matched. The preset input / output direction instruction feature refers to the control instruction feature of the input / output in the decoding instruction. By determining the direction switching information, the destination to which the decoding instruction needs to be sent can be determined, and the accuracy of the decoding instruction control can be improved.

[0064] In step S30, the target processing unit corresponding to the direction switching information is determined, and the GPIO is controlled according to the decoding instruction through the target processing unit.

[0065] In the embodiment, after the direction switching information is determined, the target processing unit corresponding to the direction switching information is determined, and finally the decoding instruction is sent to the target processing unit for GPIO control. The target processing unit refers to the processing unit corresponding to the instruction, which can be a direction switching unit, an input processing unit or an output processing unit. The step of determining the target processing unit corresponding to the direction switching information includes:

[0066] In step C10, the transmission direction in the direction switching information is determined, and it is detected whether the transmission direction matches the preset input direction.

[0067] In step C20, if the transmission direction matches the preset input direction, the target processing unit is determined as an input processing unit.

[0068] Step C30, if the transmission direction does not match the preset input direction, determining that the target processing unit is an output processing unit.

[0069] In the embodiment, the transmission direction in the direction switching information is determined, and then the transmission direction is detected. It is detected whether the transmission direction matches the preset input direction. When the two match, it is determined that the target processing unit is an input processing unit, and the decoding instruction is sent to the input processing unit. The GPIO is controlled by the input processing unit. Otherwise, the two do not match, it is determined that the target processing unit is an output processing unit, and the decoding instruction is sent to the output processing unit. The GPIO is controlled by the output processing unit. It can also be detected whether the transmission direction matches the preset output direction. The preset input / output direction refers to the input / output direction of the GPIO. The step of controlling the GPIO by the target processing unit according to the decoding instruction includes:

[0070] Step D10, if the target processing unit is an input processing unit, determining that the decoding instruction corresponds to a level return requirement;

[0071] Step D20, determining an input value corresponding to a raw level of GPIO input based on the level return requirement, and / or determining an instruction operation corresponding to the decoding instruction. A return value corresponding to the raw level and a preset source operand is determined based on the instruction operation.

[0072] In the embodiment, when the target processing unit is an input processing unit, the level return requirement corresponding to the decoded instruction is determined, and then the input value corresponding to the original level of the GPIO input is determined according to the level return requirement, and / or the instruction operation corresponding to the decoded instruction is determined, the return value corresponding to the original level and the preset source operand is determined based on the instruction operation, and the return value is taken as the input value, that is, the original level value of the input can be returned to the RISC-V processor after some operations (such as calculating the leading 0, calculating the number of 1s, performing bit operation with the source operand rs2, etc.) are performed. The level return requirement refers to the return requirement of the input level, the original level refers to the level of the GPIO input, and the input value refers to the value corresponding to the original level after the level return requirement processing. For example, the decoded instruction is IO.in.raw / lead1 / tail1 / count1 rd, which respectively corresponds to the original level value as the input value, the value of the first bit 1 position in the original level value as the input value, the value of the last bit 1 position in the original level value as the input value, and the number of bit 1 in the original level value as the input value. It can also be defined that the source operand is taken as the input value, the source operand requirement corresponding to the decoded instruction is determined, and the input value corresponding to the original level of the GPIO input is determined based on the source operand requirement. The source operand requirement refers to the return requirement of the source operand, and is not related to the original level of the input. For example, IO.in.bit rs1, rd means that the specified bit state of rs1 is determined as the input value, the specified bit can be rs1=2, and the second bit state is determined. The input is controlled through the decoded instruction, which not only improves the control diversity, but also improves the input efficiency through bus processing.

[0073] The step of controlling the GPIO through the target processing unit according to the decoded instruction further comprises:

[0074] Step E10, if the target processing unit is an output processing unit, determining the output numerical instruction in the decoded instruction;

[0075] Step E20, determining the output value corresponding to the GPIO output based on the output numerical instruction and the decoded instruction.

[0076] In this embodiment, when the target processing unit is an output processing unit, the output value instruction corresponding to the decoding instruction is determined. Then, the output value corresponding to the GPIO output is determined based on the output value instruction and the decoding instruction. The output value instruction refers to the stored source operand value, and the output value refers to the output value after processing by the output value instruction and the decoding instruction. For example, the decoding instruction is `Io.out.raw rs1,rd`, which uses the value of `rs1` as the GPIO output value; `Io.out.andrs1,rs2,rd` means using the bitwise AND operation of `rs1` and `rs2` as the GPIO output value; `Io.out.set / clear rs1,rd` means setting the specified bit of `rs1` in the GPIO to 1 / 0, while keeping other bits unchanged as the output value; `Io.out.not rs1,rd` means toggling the specified bit of `rs1` in the GPIO, while keeping other bits unchanged as the output value. Controlling the output through the decoding instruction not only improves control versatility but also avoids bus processing, thus improving output efficiency. The step of determining the output value corresponding to the GPIO output based on the output value instruction and the decoding instruction includes:

[0077] Step F10: Determine the first source operation value and the second source operation value corresponding to the output value instruction, and determine the value operation instruction in the decoding instruction;

[0078] Step F20: Based on the numerical operation instructions, perform instruction operations on the first source operation value and the second source operation value to determine the output value of the GPIO output.

[0079] In this embodiment, the output value control of GPIO output is mainly based on the first source operand and the second source operand stored in the register file. The GPIO output value is then output based on the values ​​of the two source operands and the relationship defined by the instruction. By determining the first and second source operand values ​​corresponding to the output value instruction (the first and second source operand values ​​are the values ​​of the first and second source operand operations respectively), the value operation instruction in the decoding instruction is determined. The value operation instruction is an instruction that operates on the values ​​of the two source operands, such as bitwise AND, bitwise OR, or NOT instructions. The GPIO output value is determined by performing instruction operations on the first and second source operand values. Instruction operation refers to the method of performing instruction operations on the two values, which can be the aforementioned bitwise AND, bitwise OR, NOT instructions, or other instructions. This determines the GPIO output value, realizing GPIO output control, and ensuring the efficiency of GPIO output through the bus.

[0080] Further, the embodiment further provides a RISC-V-based control system, referring to Figure 3 , Figure 3 FIG. 1 is a structural schematic diagram of the RISC-V-based control system according to the embodiment of the present application.

[0081] In the embodiment, the RISC-V-based control system comprises an open-source instruction set RISC-V processor 10, an instruction decoding unit 20, a direction switching unit 30, an input processing unit 40, an output processing unit 50 and a general-purpose input / output port GPIO 60, and the RISC-V processor 10 comprises an instruction interface 12 and a register stack 11.

[0082] The instruction interface 12 is connected with the register stack 11, the instruction decoding unit 20, the input processing unit 40 and the output processing unit 50 respectively, and the instruction interface 12 is used for transmitting a control instruction generated by the RISC-V processor 10.

[0083] The instruction decoding unit 20 is connected with the direction switching unit 30, the input processing unit 40 and the output processing unit 50 respectively, and the instruction decoding unit 20 is used for determining a decoding instruction according to the control instruction and determining direction switching information based on the decoding instruction.

[0084] The GPIO 60 is connected with the direction switching unit 30, the input processing unit 40 and the output processing unit 50 respectively, the input processing unit 40 is used for controlling input of the GPIO 60 according to the direction switching information and the decoding instruction, and the output processing unit 50 is used for controlling output of the GPIO 60 according to the direction switching information and the decoding instruction.

[0085] Referring to Figure 5 , Figure 5The existing GPIO control structure is shown in the figure. The GPIO is a slave device connected to the SoC bus in a memory mapping manner; the chip processor is a master device connected to the SoC bus; the processor controls the control register in the GPIO module by issuing a memory read / write instruction, thereby controlling / reading the IO pin of the chip from the external device. Because of the existence of the bus, the control delay of the GPIO is large. The memory read / write instruction issued from the chip processor needs to pass through the bus logic before reaching the GPIO module, so the delay is large. Therefore, in the scene where the IO response speed is required, the requirement cannot be met. On the other hand, the calculation and control are separated. Usually, the output value of the chip processor controlling the GPIO is from the calculation of the previous instruction. For example, first, the variables a and b are operated (addition, subtraction, multiplication, division, etc.), and the result c is obtained, and then c is written into the output control register of the GPIO to control the IO pin level of the chip. This process needs at least two instructions to realize. The first instruction operates a and b, and the second instruction writes the value of c into the control register. The separation of calculation and control also affects the response speed of the IO and reduces the real-time performance of the system. The last point is that the IO direction switching is slow. The switching of the GPIO direction is also controlled by the register hung on the bus, and the problem of large bus delay also exists. Therefore, the technical scheme of the present application is proposed to solve the operability of the chip control and improve the control efficiency of the chip input and output.

[0086] In the embodiment, the instruction generating unit in the open source instruction set RISC-V processor 10 is used to generate a control instruction, the control instruction is an instruction for controlling the direction switching unit 30 to perform direction switching, or the input processing unit 40 to perform input control, or the output processing unit 50 to perform output control, the register file 11 is used to store the source operand required by the control instruction, and the return value after the execution of the control instruction. After the open source instruction set RISC-V processor 10 generates the control instruction, the control instruction is sent to the instruction decoding unit 20 through the instruction interface 12 for decoding to obtain a decoded instruction, and then the direction switching information corresponding to the decoded instruction is determined, and finally the direction switching information and the decoded instruction are sent to the direction switching unit 30, the input processing unit 40, and the output processing unit 50, thereby realizing the direction of the input and output port GPIO 60 and the input and output control. The decoded instruction is the instruction after the decoding of the control instruction, and the decoding can be the decoding of the control target and the control principle of the instruction. The direction switching information is the input direction or the output direction corresponding to the input and output port GPIO 60. Through the determination of the direction switching information and the decoded instruction, the direction switching of the input and output port GPIO 60 can be realized through the direction switching unit 30, or the input control of the input and output port GPIO 60 can be realized through the input processing unit 40, or the output control of the input and output port GPIO 60 can be realized through the output processing unit 50. On the other hand, the characteristics of the open source instruction set RISC-V processor 10 itself can be customized by the user, and the instruction modification and extension function used by the user can be increased due to the open source of the instruction set. It is worth mentioning that the direction switching unit, the input / output processing unit can be a micro single-chip microcomputer chip executing instructions, or can be directly controlled by the open source instruction set RISC-V processor 10, and the register file is a storage location for storing the source operand in the open source instruction set RISC-V processor 10. The instruction interface can be a port for transmitting instructions. Through the above control mode, the phenomenon that the memory read / write instruction issued by the chip processor needs to pass through the bus logic before reaching the GPIO can be avoided, and the input and output direction switching control of the GPIO is realized through the direction switching unit, or the input control of the GPIO is realized through the input processing unit, or the output control of the GPIO is realized through the output processing unit, thereby improving the control efficiency of the chip input and output.

[0087] The application acquires the control instruction read by the RISC-V processor through the instruction decoding unit, and determines the decoding instruction corresponding to the control instruction; determines the direction switching information according to the decoding instruction and the pre-stored historical switching information; determines the target processing unit corresponding to the direction switching information, and controls the GPIO according to the decoding instruction through the target processing unit. The control instruction read by the RISC-V processor is acquired through the instruction decoding unit, and then the target processing unit corresponding to the direction switching information is determined after the control instruction is decoded, and then the GPIO is controlled according to the decoding instruction through the target processing unit, so as to realize the control of the GPIO input and output.

[0088] Therefore, the application avoids the phenomenon that the memory read and write instructions issued by the chip processor need to pass through the bus logic before reaching the GPIO in the prior art. This RISC-V-based control method not only guarantees the open source of the control instruction through the control instruction read by the RISC-V processor, increases the instruction modification and expansion function of the user, but also controls the GPIO according to the decoding instruction through the target processing unit, thereby improving the control efficiency of the chip input and output.

[0089] The application also provides a RISC-V-based control system module schematic diagram, referring to Figure 6 , the RISC-V-based control system comprises:

[0090] The read-in decoding module A01 is used for acquiring the control instruction read by the RISC-V processor through the instruction decoding unit, and determining the decoding instruction corresponding to the control instruction.

[0091] The direction switching module A02 is used for determining the direction switching information according to the decoding instruction and the pre-stored historical switching information.

[0092] The instruction processing module A03 is used for determining the target processing unit corresponding to the direction switching information, and controlling the GPIO according to the decoding instruction through the target processing unit.

[0093] Optionally, the direction switching module A02 is also used for:

[0094] determining the instruction feature corresponding to the decoding instruction, and detecting whether the instruction feature matches the preset direction switching instruction feature;

[0095] if the instruction feature does not match the preset direction switching instruction feature, determining the transmission direction corresponding to the pre-stored historical switching information, and taking the transmission direction as the direction switching information.

[0096] Optionally, the direction switching module A02 is also used for:

[0097] If the instruction feature matches the preset direction switching instruction feature, it is determined that the decoded instruction corresponds to a direction instruction.

[0098] The direction switching unit controls the GPIO to switch the direction according to the direction instruction, and the step of obtaining the control instruction read by the RISC-V processor by the instruction decoding unit is performed based on the GPIO after the direction switching.

[0099] Optionally, the instruction processing module A03 is further configured to:

[0100] Determine the transmission direction in the direction switching information, and detect whether the transmission direction matches a preset input direction;

[0101] If the transmission direction matches the preset input direction, it is determined that the target processing unit is an input processing unit;

[0102] If the transmission direction does not match the preset input direction, it is determined that the target processing unit is an output processing unit.

[0103] Optionally, the instruction processing module A03 is further configured to:

[0104] If the target processing unit is an input processing unit, it is determined that the decoded instruction corresponds to a level return requirement;

[0105] Based on the level return requirement, an input value corresponding to an original level of GPIO input is determined, and / or an instruction operation corresponding to the decoded instruction is determined, and based on the instruction operation, a return value corresponding to the original level and a preset source operand is determined.

[0106] Optionally, the instruction processing module A03 is further configured to:

[0107] If the target processing unit is an output processing unit, it is determined that the decoded instruction includes an output numerical instruction;

[0108] Based on the output numerical instruction and the decoded instruction, an output value corresponding to GPIO output is determined.

[0109] Optionally, the instruction processing module A03 is further configured to:

[0110] Determine a first source operand value and a second source operand value corresponding to the output numerical instruction, and determine a numerical operation instruction in the decoded instruction;

[0111] Based on the numerical operation instruction, the first source operand value and the second source operand value are subjected to instruction operation to determine the output value of GPIO output.

[0112] Further, based on the first embodiment of the RISC-V-based control system,

[0113] The application further provides a RISC-V-based control chip.

[0114] The chip comprises a memory, a processor and a RISC-V-based control program stored in the memory and executable on the processor, and the RISC-V-based control program is executed by the processor to implement the steps of the RISC-V-based control method.

[0115] The application further provides a storage medium.

[0116] The storage medium stores a RISC-V-based control program, and the RISC-V-based control program is executed by the processor to implement the steps of the RISC-V-based control method.

[0117] The method implemented by the RISC-V-based control program executable on the processor can refer to the embodiments of the RISC-V-based control method, and will not be described here.

[0118] It should be noted that, in this document, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or system. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or system including the element.

[0119] The above-mentioned embodiment numbers of the application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and necessary general hardware platforms, of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the application or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server or network device) execute the methods described in the embodiments of the application.

[0121] The above merely describes the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application, and any equivalent structure or equivalent process conversion, or direct or indirect application in other related technical fields, which are made by using the content of the present application specification and drawings, are also included in the patent protection scope of the present application.

Claims

1. A RISC-V based control method, characterized in that, The RISC-V-based control method is applied to a RISC-V-based control system, and the RISC-V-based control system comprises an instruction decoding unit, an open-source instruction set RISC-V processor and an input and output port GPIO. The instruction decoding unit obtains a control instruction read by the RISC-V processor, and determines a decoding instruction corresponding to the control instruction. The decoding instruction and the pre-stored historical switching information are used to determine direction switching information, and the step of determining the direction switching information based on the decoding instruction and the pre-stored historical switching information comprises: The instruction feature corresponding to the decoding instruction is determined, and it is detected whether the instruction feature matches a preset direction switching instruction feature; if the instruction feature does not match the preset direction switching instruction feature, a transmission direction corresponding to the pre-stored historical switching information is determined, and the transmission direction is used as the direction switching information; The target processing unit corresponding to the direction switching information is determined, and the GPIO is controlled by the target processing unit according to the decoding instruction.

2. The RISC-V based control method of claim 1, wherein, After the step of detecting whether the instruction feature matches the preset direction switching instruction feature, the following steps are included: If the instruction feature matches the preset direction switching instruction feature, a direction instruction corresponding to the decoding instruction is determined; The GPIO is controlled by the direction switching unit according to the direction instruction to switch the direction, and the step of obtaining the control instruction read by the RISC-V processor by the instruction decoding unit is executed based on the GPIO after the direction switching.

3. The RISC-V based control method of claim 1, wherein, The RISC-V-based control system comprises an input processing unit and an output processing unit, and the step of determining the target processing unit corresponding to the direction switching information comprises: The transmission direction in the direction switching information is determined, and it is detected whether the transmission direction matches a preset input direction; If the transmission direction matches the preset input direction, the target processing unit is determined as the input processing unit; If the transmission direction does not match the preset input direction, the target processing unit is determined as the output processing unit.

4. The RISC-V based control method of claim 1, wherein, The step of controlling the GPIO by the target processing unit according to the decoding instruction comprises: If the target processing unit is the input processing unit, a level return requirement corresponding to the decoding instruction is determined; The original level of the GPIO input corresponding to the input value is determined based on the level return requirement, and / or the instruction operation corresponding to the decoding instruction is determined, and the return value corresponding to the original level and a preset source operand is determined based on the instruction operation.

5. The RISC-V based control method of claim 1, wherein, The step of controlling the GPIO by the target processing unit according to the decoding instruction further comprises: If the target processing unit is the output processing unit, an output numerical instruction in the decoding instruction is determined; The output value corresponding to the GPIO output is determined based on the output numerical instruction and the decoding instruction.

6. The RISC-V based control method of claim 5, wherein, The step of determining the output value corresponding to the GPIO output based on the output numerical instruction and the decoding instruction comprises: determine a first source operand value and a second source operand value corresponding to the output numerical instruction, and determine a numerical operation instruction in the decoded instruction; perform an instruction operation on the first source operand value and the second source operand value based on the numerical operation instruction to determine an output value of the GPIO output.

7. A RISC-V based control system, characterized in that, The RISC-V-based control system comprises: a read-in decoding module configured to acquire a control instruction read in by a RISC-V processor through an instruction decoding unit, and determine a decoded instruction corresponding to the control instruction; a direction switching module configured to determine direction switching information according to the decoded instruction and pre-stored historical switching information, wherein the step of determining the direction switching information according to the decoded instruction and the pre-stored historical switching information comprises: determining an instruction feature corresponding to the decoded instruction, detecting whether the instruction feature matches a preset direction switching instruction feature, determining a transmission direction corresponding to the pre-stored historical switching information if the instruction feature does not match the preset direction switching instruction feature, and taking the transmission direction as the direction switching information; an instruction processing module configured to determine a target processing unit corresponding to the direction switching information, and control a GPIO according to the decoded instruction through the target processing unit.

8. A RISC-V based control chip, characterized in that, The RISC-V-based control chip comprises a memory, a processor, and a RISC-V-based control program stored on the memory and executable on the processor, and the RISC-V-based control program implements the steps of the RISC-V-based control method according to any one of claims 1 to 6 when executed by the processor.

9. A storage medium, characterized by The storage medium stores a RISC-V-based control program, and the RISC-V-based control program implements the steps of the RISC-V-based control method according to any one of claims 1 to 6 when executed by a processor.

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